instruction set architecture

1. INSTRUCTION SET ARCHITECHTURE

2. DEFINITION:
 The ISA acts as an interface between the hardware and the software, specifying both
what the processor is capable of doing as well as how it gets done.
The ISA provides the only way through which a user is able to interact with the
hardware.
An Instruction Set Architecture (ISA) is part of the abstract model of a computer that
defines how the CPU is controlled by the software.

3. TYPES OF OPERATION:
Data transfer between Register and Memory
Arithmetic and logic unit
Program control and sequencing
I/O transfer

4. Data Transfer Between Register and Memory:
The primary difference between register and memory is that register holds the data that the CPU is
currently processing.
The memory holds the data that will be required for processing.
The Register ranges from 32-bits register to 64-bits register whereas, the memory capacity ranges
from some GB to some TB.

5. Arithmetic and Logical Unit:
An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations.
 It represents the fundamental building block of the central processing unit (CPU) of a computer.
Modern CPUs contain very powerful and complex ALUs. In addition to ALUs, modern CPUs
contain a control unit (CU).

6. Program Control and Sequence Control:
Program control:
Program control instructions modify or change the flow of a program. It is the instruction that
alters the sequence of the program's execution, which means it changes the value of the program
counter, due to which the execution of the program changes.
Sequence control:
Sequence control is the mechanism by which a programming language controls the order in which
statements are executed in a program. Types of Sequence Control: Implicit sequence control is the
default behavior of a programming language, where statements are executed in the order in which
they appear in the program.

7. Input /Output data Transfer:
Input-output (I/O) data transfer techniques in input-output processors are used to transfer data
from I/O devices to memory and vice versa.
There are three common data transfer techniques used in I/O processors:
1.Programmed I/O
2.Interrupt-driven I/O
3.Direct memory access

8. MemoryLocations,Address,
Instructions and Instruction Sequencing

9. MEMORY LOCATIONS:
 Memory locations refer to specific addresses where data is stored in a computer's memory. Each
location has a unique identifier, typically expressed as a hexadecimal number. The CPU uses these
addresses to read or write data during program execution.
 The two main types of memory are
1.RAM (Random Access Memory) for temporary storage
2.ROM (Read-Only Memory) for permanent storage
Main memory is the second major subsystem in a computer. It consists of a collection of storage
locations, each with a unique identifier, called an address.

10. REPRESENTATION
OF MEMORY
 The memory of a computer can
be schematically represented as a
collection of words
 Data is transferred to and from
memory in groups of bits called
words. A word can be a group of
8 bits, 16 bits, 32 bits or 64 bits
(and growing).

11. WORD ALIGNMENT
 If the wordlength is 32-bit, then word boundaries occur at addresses 0, 4,8, . . . . We say that the word
 locations have aligned addresses. In general, words are said to be aligned in memory if they begin at a byte
 address that is a multiple of the number of bytes in a word. In genaral, the number of bytes in a word is a
 power of 2. Hence, if the word length is 16 (2 bytes), aligned words begin at byte addresses 0, 2, 4, . . . ,
 and for a word length of 64 (23 bytes), alignedwords begin at byte addresses 0, 8, 16, . . . .There is no
 fundamental reason why words cannot begin at an arbitrary byte address. In that case, words are said to
 have unaligned addresses.

12. ADDRESSES:
 Addresses are essential for the CPU to interact with memory during program execution.
The size of an address determines the range of memory that can be accessed, and it is often
expressed in bits. For example, a 32-bit address can represent 2^32 different memory locations.
 The concept of addresses is crucial for understanding how data is stored and managed in a
computer system.
Each address corresponds to a specific memory location where data can be stored or retrieved.
Addresses in computer architecture are numerical values used to uniquely identify locations in the
computer's memory.

13. ASSIGNMENT OF BYTE ADDRESSES:
Little Endian (e.g., in DEC, Intel)
low order byte stored at lowest address byte0
byte1 byte2 byte3
Big Endian (e.g., in IBM, Motorolla, Sun, HP)
High order byte stored at lowest address byte3
byte2 byte1 byte0

14. Instructions and Instruction Sequencing:
 Instructions in computer architecture are the basic operations that a processor can execute. Instruction
sequencing refers to the order in which these instructions are processed by the CPU.
 Processors follow a fetch-decode-execute cycle:
 1. *Fetch*: The processor retrieves the next instruction from memory.
 2. *Decode*: The instruction is decoded to determine the operation to be performed.
 3. *Execute*: The decoded instruction is executed, modifying the processor's state.
 Sequencing involves arranging these steps to execute a program. Branch instructions can alter the sequence,
causing the processor to jump to a different instruction based on a condition. Instruction sequencing is crucial
for proper program execution and efficient use of the CPU.

15. FLYNN’S
TAXONOMY
Flynn’s taxonomy is a
classification of parallel computer
architectures that are based on
the number of concurrent
instruction and data streams
available in the architecture

16. Single Instruction, Single Data (SISD):
 This is a uniprocessor machine which is capable of executing a single instruction, operating on a single data
stream. The machine instructions are processed in a sequential manner and computers adopting this model are
popularly called sequential computers.
 Most conventional computers have SISD architecture. All the instructions and data to be processed have to be
stored in primary memory.
Multiple Instruction, Single Data (MISD):
 An MISD computing system is a multiprocessor machine capable of executing different instructions on
different Processing Elements but all of them operating on the same dataset
FLYNN’S TAXONOMY

17. FLYNN’S TAXONOMY
Single Instruction, Multiple Data (SIMD):
 This machine capable of executing the same instruction on all the CPUs but operating on different data
streams.
 Machines based on an SIMD model are well suited to scientific computing since they involve lots of vector
and matrix operations.
Multiple Instruction, Multiple Data (MIMD):
 This is capable of executing multiple instructions on multiple data sets.
 Each PE in the MIMD model has separate instruction and data streams; therefore machines built using this
model are capable to any kind of application.

18. TYPES OF INSTRUCTION
Three address instruction:
Syntax: Operation source 1, source 2, destination
Eg: ADD D,E,F where D,E,F are memory location
Advantage: Single instruction can perform the complete operation
Disadvantage : Instruction code will be too large to fit in one word location in memory

19. TYPES OF INSTRUCTION
TWO ADDRESS INSTRUCTION:
 Syntax : Operation source, destination
 Eg: MOVE E,F MOVE D,F ADD D,F OR ADD E,F
 Perform ADD A,B,C using 2 instructions
 Disadvantage: Single instruction is not sufficient to perform the entire operation.
ONE ADDRESS INSTRUCTION:
 Syntax Operation source/destination
‐
 In this type either a source or destination operand is mentioned in the instruction
 Other operand is implied to be a processor register called Accumulator Eg: ADD B (general)
 Zero address instruction
 Location of all operands are defined implicitly
 Operands are stored in a structure called pushdown stack

20. INSTRUCTION
EXECUTION
 Straight line sequencing: If fetching
and executing of instructions is
carried out one by one from
successive addresses of memory, it
is called straight line sequencing.
 An example is given at the right
hand side

21. BRANCHING
 Branch instruction are those which changes the normal
sequence of execution.
 Sequence can be changed either conditionally or
unconditionally.
 Accordingly we have conditional branch instructions and
unconditional branch instruction.
 Conditional branch instruction changes the sequence only
when certain conditions are met.
 Unconditional branch instruction changes the sequence of
execution irrespective of condition of the results.
 An example is given at the right hand side

22. THANK YOU