Innovating the Software Development Process at Cadence Design Systems

Exec 10
© 2007 IBM Corporation
What keeps me Rational?
IBM Rational Software Development Conference 2007
®
Innovating the Process of Product Design, Development, and
Delivery at Cadence Design Systems
Dr. Rahul Razdan, Corporate Vice President, Cadence Design Systems
June 12, 2007

2
Exec 10What keeps me Rational?
Discussion Points
 Cadence Design Systems, Inc. – Who we are
 Confronting our Software Development challenges
 Our Software Development solution and evolution
 Next Steps – Expanding the solution to drive Product Development
for Cadence’ customers

3
Discussion Points

4
Market Cap: $5.5B*
2006 Revenue: $1.5B
WW offices: 57
Employees: 5200
Europe
19%
Japan
17%
Asia
10%
North
America
54%
Cadence Design Systems
Global leader of design automation solutions
*February 2006
• Founded in 1988
• Headquartered in San Jose, CA

5
2004-2009 Total
IC Market by
System Type
($B)
Source: SIA, IC Insights
AUTOMOTIVE GOV/MILCONSUMERCOMPUTING COMMS INDUSTRIAL
Semiconductor consumption driven by 3 ‘Cs’
Consumer. Computing. Communications

6
Cadence Design Systems
Holistic solutions for product development
Services

7
Discussion Points

8
Problems Faced…
Built by merger
and acquisition
Complexity
Increasing
Requirements
Increasing
Crushed by our
own success
Globalization
Parallelized
Development

9
WAS…

10

11

12
SW Development Heartbeat
 Core SW Development:
 Build-Link-Validate Cycle
 Scaled for developers across geographies
 Scaled for multiple steams
 Accelerating Time-to-market or Increasing Quality involves fundamental
restructure of this core process across the enterprise.
 Measure with metrics
M/S
C C/B T
Triage
Bugs
Collect
Reqs
U
U
U
C C/B T
C C/B T
C/B TMerge

13
Enterprise-Wide Process Metrics
Optimizing All Aspects of Productivity
 Productivity:
 time to first test
 incremental time to create new tests
 coverage/day
 gates/functions verified/engr mm
 time to derivative environments
 Predictability:
 total coverage
 coverage convergence rate
 bug convergence rate
 project resource & convergence stats
 to plan next project better
 Quality:
 # respins
 # functional bugs ID'd in post silicon
 # field recalls
 breakout of hardware vs. software bugs
 Human Resource Utilization:
 % reuse of verification plans
 % reuse of verif’n environments
 % reuse of verification components
 Compute Resource Utilization:
 % of sims running 24x7
 cycles used for last 10% coverage
 Best Practices Deployment:
 Automation deployment level
 block, chip, system, project levels
 Verification maturity scale
 Directed testing
 Automated testing
 Coverage driven
 Scalable coverage driven
 Reuse

14
Discussion Points

15
Environment Maturity Model
 Motivation (the why) drives
downward from the upper
layers to trigger change
 Implementation and
process schema (the how)
provide the foundation for
the modelDevelopment
Environment
Development
Processes
Business
Processes
Infrastructure
Solutions

16
Foundations
 Central storage structure
 Common language (Perl)
 Core modules
Command-line processing
Messaging and logging
Common parsing framework
Site customization
Object Data Definitions
Platform classification

17
Infrastructure and Policies
 Infrastructure
Fault-tolerant central storage
Robust local network
Controlled image configurations
Dedicated servers
Monitoring & Management
 Policies
Managed growth
Defined API for tools
Resource management

18
Configuration Management
 Tools
ClearCase
MultiSite
 Resources
Central VOB/View servers
Central registry and licensing servers
 Methodology
Branching and Merging
Trigger conventions

19
Project/Variant
 Context for developer activity
Policy-based control
Standard build/install
 Managed data
Dependency kits
User environment
Build components
Project policy
Configuration Management
Testing environments

20
Server Farm
 Foundation
Hardware
Tools
DRM (eg LSF)
 Services
Meeting the user need
 Bridging the gap
Management services
BuildJob
TestJob
AutoControl sequencing

21
KitExchange
 Inter-project collaboration
Software integration
Distributed build support
Development merge support
 Managed Data
KitExchange meta-data
Content depots
 Flexible Architecture
Communication plugins
Fall-back data sources

22
Development Processes
 Coordination
 Merge schedules
 External dependency validation
 Quality
 Perpetual release readiness
 Release Engineering
 Decision criteria
 Unified Release
 Applied Governance
 Control and measurement
 Policies to address internal and external
compliance
 Drive consistency and best practices
 Benefits-driven model

23
Business Processes
 Early Adopter engagements
 Requirements gathering
 Product release model
 Solutions integration

24
Results after 6 years
 6.6 million avg daily tests [10.2 million
peak]
 349 projects
 7 sites [plus other satellite locations]
 270 R&D/PV engineers
 7 release streams [current and future]
 2187 cpu [1041 hosts] server farm
 200,000 avg daily tests
 Unknown # of projects
 1 sites
 80 R&D/PV engineers
 3 release streams
 ? cpu [? hosts] server farm
Before After

25
Results after 6 years
 Increased product complexity from acquisitions and mergers involving our
technologies
 Entire product has been ported to additional platforms
 Accelerated releasing process through
 Early Adopter
 Point Release
 Unified Release
 Maintained top rankings in customer satisfaction despite enormous
changes

26
And Less Chaos…

27

28

29
Discussion Points

30
.35u .25u .18u .13u 90nm 65nm
1
10
100
1000
10000
100000
Process Technology
RelativeComplexity
.35u .25u .18u .13u 90nm 65nm
1
10
100
1000
10000
100000
Process Technology
RelativeComplexity
Based on: Cadence Design Systems, “It's about time: Requirements for the functional verification of nanometer-scale ICs”
Design
1E3-1E4 gates,
1E6-1E8 cycles
1E3-1E4 gates,
1E6-1E8 cycles
10-1E3 gates,
100-1E6 cycles
10-1E3 gates,
100-1E6 cycles
1E4-1E6 gates,
1E8-1E12
cycles
+Acceleration
1E4-1E6 gates,
1E8-1E12
cycles
+Acceleration
1E6-1E8 gates,
1E12-1E16
cycles
+Emulation/Co
Sim
1E6-1E8 gates,
1E12-1E16
cycles
+Emulation/Co
Sim
1E8+ gates,
1E16+ cycles
+System Level
Design
+OS/SW
Development
Functional
Verification
Design and functional verification complexity explosion

31
SW Integration Efforts Outweigh Pure HW
Factors into productivity, quality, predictability risks –
PROBABLY KILL PAGE
10
4
1
Application
Middleware
OS
Firmware
HW
Solution
Whole Product
View
HW
Mgr
SW
Mgr
Team
Ratios
The Desired Process
Software
Hardware
Chip
Design Phase
Concurrent Flow
Design Build
HW Integration
& Debug
CodeDesign
System
Integration
& SW Debug
Chip Debug FabDesign
The Process Today
Design Code
System
Integration
& Debug
Chip
Respins
Design Phase Sequential Flow
FabDesign Chip
Debug
Software
Hardware
Chip
Design Build
Hardware
Integration
& Debug

32
The Enterprise System Level Challenge
How does the
design react to
corner cases?
What bugs
are in the
logic?
Does the firmware
work on HW?
Do HW and SW
work together?
Does the system
perform and function
as expected?
Will it get done with
quality and on time?
Can response times to
changes improve?
Can costs be lowered and
resources minimized
Verification
Engineers
HW Design
Engineers
System
Validation
Engineers
System
Engineers
Embedded SW
Developers
Exec & Project Manager
Specifications
Emails
Written reports
Post-it notes
Scripts
Hallway conversations

33
Product Verification Solution Summary
Reduce risk and improve quality
- Project predictability
- Early system level quality
- Productivity and resource utilization
... With industry best practices
- Process automation & management
- Across block, chip, & full system
- With plan-to-closure methodology
...Tailored for
- Design engineers
- Design teams also performing verification
- Multi-specialist enterprise teams
Firmware
Mixed-Signal IF
Yield/Reliability
IR Drops
Power Consumption
Noise/SI
Logical/Functional
10% 70%30% 50%

34
Cadence & IBM Joint Customer Solution View
Design to Silicon
System Validation, Logic Signoff
SW Design,
Debug, and
Environment
HW Design,
Verification,
Implementation
System Level Design & Verification
Design & Verification Plan to Closure
System Wide Management
Verification
Engineers
HW Design
Engineers
System Validation
Engineers
Embedded SW
Developers
Exec & Project Manager
System
Engineers
Embedded
Software
SoC
Verification
Methodology
Lifecycle
Automation
Embedded SW Developers

35
Enterprise Resource Utilization
Dynamic Allocation to the Highest Return on Investment
Regional
File and CPU
Server Farms
Software
Specialist
Project/Verification
Manager
Verification
Specialist
Systems
Specialist
HW Design
Specialist
Project A
Project
Metric
Database
Resource Policies and Management
Project D
Project
Metric
Database
Project B
Project
Metric
Database
Project C
Project
Metric
Database
Project-Specific
Data and Process
Decisions
System
Validation
Specialist
Client-Server Domain Applications
Multiple Projects Competing For Scarce Resources
Build
Specialist

36
Verification Solution Map
Practitioner
productivity
Team
collaboration
Enterprise
performance
Cadence Logic
Design Solution
IBM Rational
Design & Test Tools
Cadence
Incisive Enterprise
Simulator w/ VPA
IBM Rational
Team Unifying
Platform
Cadence
Incisive Enterprise
System Level
IBM Rational
Software Delivery
Platform
The joint IBM Rational-Cadence solution provides
several entry points. In addition, joint methodology for
hardware/software verification is a key differentiator.

37
Dr. Rahul Razdan
Corporate Vice President
Cadence Design Systems, Inc.
Thank You

38
Enterprise HW/SW Verification Solution
Manages the process from Plan-to-Closure
vPlanvPlan
Plan
Measure
React Execute
Closure
Plan
Measure
React Execute
Plan
Measure
React Execute
Plan
Measure
React Execute
Plan
Measure
React Execute
vPlan
vPlan
vPlan
vPlan
Plan
Measure
React Execute
vPlan
Management
System, HW, SW
Specifications
vPlan
vPlan
vPlan

39
Lessons Learned
 Treat as a whole system – cannot look at piece parts
 Swallow hard and make the decision to go for it – it must be central to
the business
 Need to make the investment with the right focus
 Processes developed internally can open the door for an infrastructure
element in the products delivered to your customers – leads to
opportunity for IBM and Cadence to partner further to deliver to the
industry
 It’s not pie-in-the-sky. It works !!

40
Rational Portfolio Manager
Design
Analyze
and model
Develop
Implement
and iterate
Build
Build
and stage
Deploy
Deploy
to target
Rational Method Composer
and DoDAF Rational Test RealTime
Rational Systems Developer Rational Manual Tester
E+ SysML
Rational Functional
Tester
E+ DoorKeeper Rational PurifyPlus
Rational Rose Technical Developer
Rational RequisitePro, Rational ClearCase, Rational ClearQuest, Rational ClearQuest MultiSite, Rational ClearQuest
TestManager
Rational Build Forge
Wind River WorkBench
Eclipse framework: open and extensible
Model-driven systems development with IBM RUP for systems engineering
Validate
and test
Test
Verification Solution Map
Enterprise Scope
Design
Team
Verification
Team
System/Validation
Team
Software
Team
EnterpriseValue
Enterprise Scope
Team
Predictability
Product
Risk
Quality &
Productivity
Project
Predictability
Engines &
Languages
Design
Verification
Cadence Logic
Design Solution
Incisive Enterprise
Simulator w/ VPA
Incisive Enterprise
System Level (ESL)
Simulation, Formal, Acceleration, Emulation

41
Questions

42
Our Success – the Compelling Reason to Change
 Acquisitions and growth impacts to productivity and time to value
 Globally-distributed software development teams
 Expanded Product Line with new verification languages
 Introduction of newly-supported Platforms
 Not organized for growth:
 Internally – product focused versus infrastructure focused
 Externally – new verification languages, OS changes

43
Complexity Driving Risk of Failure & Retooling
ASIC Complex ASIC SoC & Systems
Design
challenge
Functional
Combinations
To Verify
Hundreds
Thousands
Millions
(HW+SW)
Simulator Debug
Logic Simulation
Simulator/
Debug
Emulation
Testbench Coverage VIP
Formal
‘Process Automation’
Logic Design with Verification
Block to Chip Level
Verification Process Automation (VPA)
Enterprise System Level (ESL)
Design
Verification

44
Productivity Risks
• Ability to create massive # of tests
• > 1 week chip/system level run times
• Poor block, chip, & system links
• Complexity of product builds
Confidence
Time Scheduled Tapeout
95%+
Final Tapeout
Predictability Risks
 Rippling effects of spec change
 No executable plan
 Limited progress visibility
Taking the risks out…
Quality Risks
 Lack of metrics for ‘done’
 Incomplete spec & plan
 Missed system scenarios

45
Cadence Innovations
“CADENCE INTRODUCES INDUSTRY'S FIRST COMPLETE CUSTOM
IC SIMULATION AND VERIFICATION SOLUTION -
Virtuoso Multi-Mode Simulation Solution Enables Fast and Accurate
Verification of Designs Across Analog, RF, Custom Digital, Memory and
Mixed-Signal Domains”
“UNISYS IMPROVES LOGIC DESIGN TEAM PRODUCTIVITY WITH
CADENCE INCISIVE FORMAL VERIFIER -
Citing Increased Productivity, Unisys Incorporates Assertion-Based
Verification Methodology into Its Production Design Flow”
Made possible with the Incisive Verification Platform

46
Predictability Comes From Visibility of Metrics
WW27 WW47WW43WW39WW35WW31
LAN Ingress
LAN Egress
JPEG
MPEG Encoder

Innovating the Software Development Process at Cadence Design Systems

Recommended

Recommended

More Related Content

What's hot

What's hot (20)

Similar to Innovating the Software Development Process at Cadence Design Systems

Similar to Innovating the Software Development Process at Cadence Design Systems (20)

Recently uploaded

Recently uploaded (20)

Innovating the Software Development Process at Cadence Design Systems