1. Himani Upadhyay | Email: himani.upadhyay812@gmail.com | C-19, Sector – D1, LDA
Colony, Kanpur Road, Lucknow (UP), India - 226012
Education:
MS by Research (ECE-VLSI) | IIIT Hyderabad, 2012-2015 | CGPA: 7.67
B. Tech (ECE) | Galgotias College of Eng. & Technology (UPTU) | 81.5%
12th
Board (ISC) | CMS Degree College, Lucknow | 90.33%
10th
Board (ICSE) | CMS Degree College, Lucknow | 88.66%
Technical Skill Set:
Programming Languages : C, C++, HTML/CSS
Scripting Languages : Shell, Tcl/Tk,Python, MySQL (Basics)
EDA Tools : Cadence, AWR, Tanner, ModelSim-Altera, MATLAB 10.0a.
HDLs : Verilog HDLs.
Area of Interest : Digital Design, CMOS Design, Layout.
Industrial Experience:
Internship at Vitesse Semiconductors Private Limited. (January 2015-present)
 Training on “ETHERNET Solutions and IOT” which involves understanding of Validation environment and
flow.
 Learning of Ethernet testers like SMB, IXIA and working through GUI mode. Working with reference and
validation boards. Gained knowledge about network protocols like spanning tree, VLAN, Ethernet, MACsec
etc.
 Working on a PROJECT in System Validation for 10G and 1G PHY with encryption and de-cryption i.e MAC
security protocol for flow of data from end to end in a network with features like MPLS label bypass and
VLAN tag bypass.
 Part of PCB design group at the company.
Research Publications:
1. “A High Speed and Low Performance 8 BIT x 8 BIT Multiplier using Novel Two Transistor (2T) XOR
Gates” w.r.t power, delay, PDP and area in 65nm, 90nm and 130nm technologies - Journal of Low Power
Electronics, Volume 11, Number 1, pages: 37-48, March (2015), American Scientific Publishers.
2. “Design of high speed and low power 5:3 compressor architectures using novel two transistor XOR gates”-
International Journal of Electrical, Electronics and Computer Systems (IJEECS), IRD India.
MS by Research Projects (Academic):
1. A Novel Simple and High Performance Structure for Improving CMRR
A novel and simple structure for improving while preserving CMRR bandwidth which is a novel
technique in order to improve CMRR.
2. Superfast Random Sequence Generator
Designing of a 4-bit random number generator used for test pattern generation using the Linear Feedback
Shift Register approach with minimal speed.
3. Transceiver design
Design of transmitter and receiver blocks at 5 GHz frequency.
4. Latch Designs for Nano-scale CMOS Technology at 180 nm
i. In our project, we proposed three high performance, low cost and robust latches in 180 nm
CMOS technology  HLR, HLR-CG1, HLR-CG2.
ii. The proposed latches are completely insensitive to transient faults at their internal nodes
and output node independent of the size and technology of the CMOS transistor.

2. iii. The proposed latches tolerate transient faults regardless of the energy of the striking
particles.
5. Implementation of Simple Adders
To learn basic Cadence, we implemented the half, full, ripple, carry ahead, etc. adders on cadence and
observed different parameters like power consumed, delay, area etc.
6. Discrete-Time Mixing Receiver Architecture for RF-Sampling Software Defined Radio
Design of a block of receiver i.e. sampler.
B. Tech Project:
1. Automatic Target Shooter
Technology: Microcontroller 89S52, Assembly Language.
Achievements:
 Participated in the “SIXTH INTERNATIONAL CONVENTION” on “STUDENT QUALITY
CONTROL CIRCLES” at school level.
 Participated in Sixth National Science Olympiad held in India and abroad.
 Got Meritorious Position in MATHS & CHEMISTRY OLYMPIAD conducted by “TALENT
SEARCH INSTITUTES” and reached up to 3rd level.
 Awarded with certificate of TALENT from “NATIONAL SOCIETY FOR EDUCATION &
RESEARCH”.
 Participated in “PROCOM” quiz contest at North India Level.
 Co-ordinated several events during the college fest “G-Quasar 2011”.
 GOLD MEDALIST at graduation level for having highest marks in Uttar Pradesh Technical
University.
Trainings:
Training in Railways (2009-2010)
A one month training program during 2nd year of B.TECH at RESEARCH DESIGN AND STANDARDS
ORGANIZATION in the field of "SIGNALS AND SYSTEM".
Training in HAL (2010-2011)
A one month training program during 3rd year of B.TECH at HINDUSTAN AERONAUTICS LIMITED in the field
of designing an aircraft DHRUVA.
Training in ACCENTURE (2011-2012)
A one month training program known as HEAD START FOUNDATION PROGRAM organized by Accenture which
gave basic ideas about many languages like SQL, UNIX,HTML/CSS, JavaScript.
Training in ERICSSON (2011-2012)
A two week program named "ERICSSON EMPOWERMENT PROGRAM" giving the idea about the work done at
the company. It was mainly based on GSM basics, 3G technologies and IP fundamentals. A visit to the campus and to
understand the work environment.
Other Details:
Gender: Female | Date of Birth: July 1, 1989
Marital Status: Single | Nationality: Indian
Hobbies: Athletics, Reading, Singing, Sketching, Dance, Calligraphy, Cooking, Badminton
I hereby declare that all the information given here are true to my knowledge and belief.
Himani Upadhyay