The document outlines hardware synthesis design processes, focusing on RTL architecture with optimizations like variable and operation merging, register sharing, and pipelining techniques. It discusses scheduling algorithms and emphasizes the need for system-level design to manage growing complexities in technology. Future work includes exploring timed transaction-level modeling (TLM), incorporating RTOS models, and synthesizing designs for FPGA prototyping.

1. Hardware synthesis

2. Outline
• Design flow
• RTL Architecture
• Input specification
• Specification profiling

3. HW Synthesis design flow

4. RTL Architecture

5. RTL Architecture with FSM
Controller

6. RTL Architecture with
Programmable controller

7. Input Specification

8. C Code for Ones counter

9. CDFG

10. FSMD for Ones counter

11. CDFG and FSMD for ones counter

12. RTL Specification for Ones counter

13. HDL Description of Ones counter

14. Square root Algorithm (SRA)

15. Variable and Operation Usage

16. Connectivity Usage

17. Datapath synthesis

18. Gain in register sharing

19. General partitioning algorithm

20. Variable merging for SRA

21. Variable merging for SRA

22. Variable merging for SRA

23. Datapath with shared registers

24. Gain in funtional unit sharing

25. Operation merging for SRA

26. Operation merging for SRA

27. Datapath with shared registers and
FUs

28. Connection usage for SRA

29. Connection merging for SRA

30. Datapath with shared registers,
FUs and buses

31. Register merging into RFs

32. Datapath with shared RF

33. Datapath with chaining

34. Datapath with chained and Multi-
cycled FUs

35. pipelining

36. FU pipelining

37. FU pipelining

38. Dapath pipelining

39. Dapath pipelining

40. Dapath and control pipelining

41. Dapath and control pipelining

42. Scheduling

43. C and CDFG for SRA

44. ASAP and ALAP Scheduling

45. RC Scheduling

46. RC Scheduling

47. TC Scheduling

48. Distribution graphs for TC
scheduling

49. Distribution graphs for TC
scheduling

50. Distribution graphs for TC
scheduling

51. TC scheduling

52. Interface synthesis

53. Bus Interface controller

54. Bus Interface controller

55. Transducer Bridge

56. Summary
• Generation of hardware designs for some
models like CDFG and FSMD is studied. Several
procedures to optimize such designs like
• merging the registers ,
• connections and operators are studied.
• Optimization techniques like chaining and
multicycling are also studied. Finally two
scheduling algorithms are studied.

57. Conclusion
• The technological advances and ever increasing
market demands for new applications system
complexities are growing at exponential rate.
In-order to deal with complexity we need to
move to system level design. For that we need
to have models with well defined semantics for
automatic generation and synthesis. Model
based approach helps in reducing the system
design time by having intermediate models
which are the TLMs in the design flow. TLMs
allow us to generate hardware and software
automatically.

58. Future Work
• Generation and simulation of timed TLM.
• Including RTOS models to the design so that
multiple processes can be mapped to a single
processor.
• Study of Including hardware blocks into the
design.
• Study of other academic tools from various
universities and their functionalities.
• Synthesizing the design to a FPGA board to
make the first prototype.