1. Technology Review of High Aspect Ratio
Through-Silicon-Via
Eric Johnson, Chulyong Kim, Bon Woong Ku,
Amechi Toya, Shuchen Zhang
Georgia Institute of Technology

2. Agenda
1. Introduction and Background
2. Process Flow
3. Electrical Properties
4. Mechanical Properties
5. Design Impact
6. Future Technologies
Cross section of a TSV
Source: [3]

3. TSV Background
Sources: [1,2]

4. TSV Background
Sources: [1,2]

5. Source: www.samsung.com

6. Benefits Of TSV
Source: [2]

7. Why High Aspect Ratio?
TSV Scaling and Function Density
Source: [2]
2009 2015
TSV Size (um) 1.5 1.0 0.55
Device Area (um2
) 0.82 0.20
TSV-to-Device 2.74 5.00 2.74

8. TSV Scaling
Aspect Ratio = 10 Aspect Ratio = 10 Aspect Ratio = 16.7
Source: [3]

9. TSV fabrication
(a) SiO2
deposition
(b) Photoresist patterning
(c) SiO2
patterning
(d) Etching
(e) SiO2
deposition
(f) Backside thinning
(g) Backside SiO2
deposition
(h-j) Electroplating
(k) CMP
Source: [Modified from 4]

10. Etching
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11. Etching
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•
Source: [10]

12. Isolator Deposition
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Source: [11]

13. •
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Isolator Deposition
Source: [12]

14. Barrier / seed layer deposition
➔ Barrier Deposition
● Electroless barrier deposition
- Ni-B, Ni-W-B, Co-B, Co-W-B (Ni- and Co-alloys)
○ Better Step coverage, good uniformity.
○ High adhesion strength. (~56MPa)
○ Holds up against Cu diffusion up to ~300-400℃
● Chemical Grafting
- NiB
○ Conducting, eliminates the need for a seed
layer.
○ Forms strong bond with isolation polymer
(P4VP).
○ Uniformity, good step coverage.
➔ Seed Deposition
● Electroless Cu seed deposition.
- Good step coverage (prevents voids)
Source [14]

15. Cu Filling
● Electroplating
- Needs conducting seed layer with
good step coverage.
- Additives have to be introduced to
ensure the copper ions get to the
bottom of the via for better filling.
-
● Electroless plating
- Conductivity of surface is irrelevant.
- No void.
- Bottom-up filling is possible with
additives that have high diffusion
coefficient.
Source [9]
Source [13]

16. COST BREAKDOWN OF 3D IC FABRICATION
Source: [8]

17. General Electrical Properties
● Short interconnect length compared to wirebonding
○ Lower interconnect delay
○ Higher Bandwidth
● Marginal electrical changes with higher aspect ratio
Wirebond Traditional TSV HAR TSV
Interconnect Length Long Short Short
I/O Density Low Med High
Back of Line Delay High Low Low

18. HAR TSV Electrical Properties
Source: [6]

19. Mechanical Reliability of TSV
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Thermomechanical Properties of the Materials

20. Mechanical Reliability of TSV
•
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21. Mechanical Reliability of TSV
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22. Limitation of normal TSV usage
Huge silicon area / parasitic overhead
Normal TSV HAR TSV
Source: [5]

23. Design Impact of HAR TSV usage
Physical design result shows that HAR TSV maximizes 3D IC
37% area saving, 12% performance saving, little power consumption overhead
Source: [5]

24. Future of 3D interconnect technology
Monolithic 3D: To fabricate the top tier monolithically
minimizing vertical interconnection overhead
Source: [7]

25. TSV 3D vs. Monolithic 3D
High Alignment Precision leads to small 3D via
Source: [15,16]
Monolithic Inter-tier Via
TSV

26. Conclusion
TSV scaling and HAR TSV technology is required
because device scaling continues, but also for the miniaturization of the system
We discussed
HAR TSV-specific fabrication issues and potential solutions, and its characteristics
We reviewed
HAR TSV leads to minimum 3D interconnection overhead, and maximum 3D benefit
Future technology of 3D interconnect
Moves from HAR TSV toward Monolithic 3D that provides with nm-scale 3D via

27. References
[1] Rao R. Tummala, Introduction to SIP Stacked ICs and Packages (SIP), Lecture, Georgia Tech, 10/6/2016.
[2] Rao R. Tummala et al, Introduction to System-On-Package, 2004.
[3] Sesh Ramaswami, Through Silicon Via (TSV) Interconnect, Lecture, Georgia Tech, 10/4/2016.
[4] A. Yu et al., “Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With
High-Density Interconnects,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 9, pp. 1336–1344, 2011.
[5] D. H. Kim and S. K. Lim, “Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices,” IEEE Journal on
Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 240–248, 2012.
[6] H. He, J. J. Q. Lu, Z. Xu and X. Gu, "TSV density impact on 3D power delivery with high aspect ratio TSVs," ASMC 2013 SEMI Advanced
Semiconductor Manufacturing Conference, Saratoga Springs, NY, 2013, pp. 70-74.
[7] Shreepad Panth, Kambiz Samadi, Yang Du, and Sung Kyu Lim, "Design and CAD Methodologies for Low Power Gate-level Monolithic 3D ICs,"
IEEE International Symposium on Low Power Electronics and Design, 2014.
[8] Claudio Truzzi, A Novel Approach to TSV Metallizaiton based on Ectrografted Copper Nucleation Layers,” Lecture, Alchimer, 9/25/2008.
[9] Myong-Hoon Rho, et al., “Various Cu Filling Methods of TSV for Three Dimensional Packaging,” Journal of KWJS Vol. 31 No. 3. Pp11-16. 2013.
[10] Arturo A. Ayon, PEUG talk, may 2001.
[11] Dow Corning Corporation, Midland, MI
[12] T. Dequivre, E. Alam, J. Maurais, “Electrografted P4VP for high aspect ratio copper TSV insulation in Via-last process flow,” pp. 340-344, 2016.
[13] Zengling Wang, et al., “Bottom-up fill of submicrometer copper via holes of ULSIs by electroless plating,” Journal of The Electrochemical
Society, 151 (12) C781-C785 (2004).
[14] Fumihiro Inoue, et al., “All-Wet Fabrication Technology for High Aspect Ratio TSV Using Electroless Barrier and Seed Layers,” Kansai
University, 3-3-35 Yamate-cho, Suita, Osaka, Japan.
[15] Brunet, Laurent, et al. "(Invited) Direct Bonding: A Key Enabler for 3D Monolithic Integration." ECS Transactions 64.5 (2014): 381-390.
[16] C. Liu and S. K. Lim, "A design tradeoff study with monolithic 3D integration," Thirteenth International Symposium on Quality Electronic Design,
Santa Clara, CA, 2012, pp. 529-536.

28. Questions?