GUN Make is a tool used to automate the building of executables from source code. It determines which files need to be recompiled based on timestamps and builds the necessary targets. Rules define dependencies and commands to transform files. Variables, macros, conditionals, and functions allow for complex logic and reuse in the makefile. Includes allow splitting makefiles into modular pieces.

1. GUN Make
Reference: O’Reilly – Managing Projects with GNU Make 3th.
Eric Hsieh

2. Outline
• Rule
• Variable and macro
• Functions

3. Introduction
• Why do we need GUN Make?
• Source -> Object -> Executable
• Goal: The make program is intended to
automate the mundane aspects of
transforming source code into an executable.
• Base on timestamp.

4. Rule
Target: Prereq1 Prereq2 …
<Tab> commands1
<Tab> commands2
Example:
hello: hello.c
gcc hello.c –o hello

5. Rule
$make
gcc hello.c –o hello
#make again
$make
make: `hello.c’ is up to date.
(1)

6. Rule
Just print
$make - -just-print or –n
Comment character
# gcc hello.c –o hello
(M)

7. Rule
• Default goal
• Top-down (2)

8. Command Modifiers
• @ Do not echo the command. If you want to
apply this modifier to all, you can use the
--silent (or -s) option.
• - The dash prefix indicates that errors in the
command should be ignored by make.
You can use --ignore-errors (or -i) option.
• + The plus modifier tells make to execute the
command even if the --just-print (or -n)
command-line option is given to make.

9. Phony target
Goal: phony target is out of date.
Example:
clean:
rm –rf *.o
$touch clean
$make clean
make: `clean’ is up to date.

10. Phony target
• Remember! Make cannot distinguish the
different between target and phony target. So,
we need define following:
.PHONY: clean
clean:
rm –rf *.o
(2)

11. Standard phony target list

12. Empty target (Cookie)
Example: pl1029 opensource hello
.PHONY: install disclean
$(SOURCE)/.configured:
cd $(SOURCE) && LDFLAGS='-s' CFLAGS='-Os' ./configure
.......
touch $@
install: $(SOURCE)/.configured
make -C $(SOURCE) install-strip
distclean:
make -C $(SOURCE) distclean
rm -f $(SOURCE)/.configured

13. Variable name
• #define
• A = 1234
• CC := cc
• #use
• $A or $(A) or ${A}
• $(CC) or ${CC}

14. Variable name
• Run on Bash
hello:
@echo "Hello, $${USER}" #shell variable USER
@echo "Hello, ${USER}" #make variable USER
or
hello:
@echo "Hello, $$USER" #shell variable USER
@echo "Hello, $(USER)" #make variable USER

15. Automatic variable
• $@ target
• $% archive member,
Example: $@ is foo.a, $% is bar.o
foo.a(bar.o): bar.o
commands…
• $< the first prereq
• $? The names of all prerequisites that
are newer than the target

16. Automatic variable
• $^ The names of all the prerequisites. This list
has duplicate names removed.
• $+ Similar to $^, but it includes duplicates.
• $* The stem of the target filename.
Example: $* is hello
hello.o: hello.c
gcc hello.c –o hello.o
(3)

17. VPATH and vpath
• We can use VPATH or vpath to tell make where to
find the source code.
.
|-- inc
| `-- saydone.h
|-- log
|-- Makefile
`-- src
|-- hello.c
|-- saydone.c

18. VPATH and vpath
• Without VPATH or vpath, we make it and we
will get~
$make
make: *** No rule to make target `hello.c', needed by
`hello.o'. Stop.
• So, we need to tell make where to find source
code by VPATH or vpath.(4)

19. Pattern rule
For example:
hello: hello.o
hello.o: hello.c
$make
cc -c -o hello.o hello.c
cc hello.o -o hello
We need to key “make - -print-data-base” to
understand pattern rule.(5)

20. Dependencies
$ echo "#include <stdio.h>" > stdio.c
$ gcc -M stdio.c
stdio.o: stdio.c /usr/include/stdio.h /usr/include/features.h
/usr/include/bits/predefs.h /usr/include/sys/cdefs.h
/usr/include/bits/wordsize.h /usr/include/gnu/stubs.h
/usr/include/gnu/stubs-32.h
/usr/lib/gcc/i686-linux-gnu/4.4.5/include/stddef.h
/usr/include/bits/types.h /usr/include/bits/typesizes.h
/usr/include/libio.h /usr/include/_G_config.h
/usr/include/wchar.h
/usr/lib/gcc/i686-linux-gnu/4.4.5/include/stdarg.h
/usr/include/bits/stdio_lim.h /usr/include/bits/sys_errlist.h

21. Dependencies
• So, we need to .d and include it.(6)

22. Manager archive library
libsay.a: libsay.a(saydone.o) libsay.a(hello.o)
libsay.a(saydone.o): saydone.o
ar rv $@ $^
libsay.a(hello.o): hello.o
ar rv $@ $^
Same as
libsay.a: saydone.o hello.o
commands…
(8)

23. Assign variable
• Simply expanded variable --- immediately expanded
MAKE_DEPEND := $(CC) –M
• Recursively expanded variable --- lazily expanded
CURRENT_TIME = $(shell date)
• Conditional variable assignment operator
OUTPUT_DIR ?= $(PRERIX)
• Append operator
CPPFLAG += -lpthread

24. When Variables Are Expanded

25. When Variables Are Expanded
• The righthand side of += is expanded
immediately if the lefthand side was originally
defined as a simple variable. Otherwise, its
evaluation is deferred.
• For rules, the targets and prerequisites are
always immediately expanded while the
commands are always deferred.
• (7.1)

26. Macro
• Syntax
define macro-name
commands1
commands2
endef

27. Macro
For example:
define ericEcho
@echo Eric....
@echo $(CC)
@echo $(CPPFLAGS)
endef
#use
$(ericEcho) or $(call ericEcho)

28. Target- and Pattern-Specific Variables
Example:
gui.o: gui.h
$(COMPILE.c) -DUSE_NEW_MALLOC=1 $(OUTPUT_OPTION) $<
or you can do it same as following
gui.o: CPPFLAGS += -DUSE_NEW_MALLOC=1
gui.o: gui.h
#default pattern rule
Another example is libffmpeg.

29. Where Variables Come From
• Command line: (V)
– make CFLAGS=-g CPPFLAGS=‘-DBSD –DDEBUG’
• File:
– by include
• Environment:
– by export or unexport

30. Conditional
• ifdef or ifndef
ifdef RANLIB
$(RANLIB) $@
endif
• ifeq or ifneq
ifeq “$(strip $(OPTIONS))” “-d”
CPPFLAGS += - -DDEBUG
endif
(3)

31. include
• The include directive is used like this:
include definitions.mk
• Special characteristic.
(4)
• If any of the include files is updated by a rule,
make then clears its internal database and
rereads the entire makefile.

32. Standard make Variables
• MAKE_VERSION:
– This is the version number of GNU make.
• CURDIR:
– This variable contains the current working directory of the
executing make process.
• MAKECMDGOALS:
– It contains a list of all the targets specified on the
command line for the current execution of make.
ifneq "$(MAKECMDGOALS)" "clean"
-include $(DEPEND)
Endif
(v)

33. Functions
• $(call macro,parm1 ….)
• $(shell command)
– CURRENT := $(shell date)
• $(filter pattern,text) or $(filter-out pattern,text)
HEADER := $(filter %.h, $(SOURCES))

34. Functions
• $(subst search-string,replace-string,text)
OBJECTS := $(subst .c,.o,$(SOURCES))
• $(patsubst search-pattern,replace-pattern,text)
and $(variable:search=replace)
OBJECTS := $(patsubst %.c,%.o,$(SOURCES))
DEPENDS := $(SOURCES:%.c=%.d)

35. Functions
• $(wildcard pattern…)
SRCS := $(wildcard *.c)
• $(suffix name)
See example
• $(addsuffix suffix,name)
common := $(addsuffix /common.mk,prefix)
#common = prefix/common.mk
• $(error text)

36. Functions
• $(warning text)
• $(strip text)
• $(if condition,true-part,false-part)
PATH_SEP := $(if $(COMSPEC),;,: )