The document discusses various concepts related to diode-based circuits in electrical engineering. It includes calculations for peak output voltage, diode current, average DC levels, and ripple voltage in rectifiers, along with examples of circuit analysis. Additionally, it covers filter capacitor design to reduce ripple voltage and outlines methods for calculating ripple factor and average output voltage.

1. ELL 100 - Introduction to Electrical Engineering
LECTURE 19: DIODE BASED CIRCUITS

2. Diode Types
2

3. Diode Types
3
Symbol for various types of Diodes

4. A full-wave center-tapped rectifier circuit is shown below.
Assume each diode has a cut-in voltage V = 0.6V and a
forward resistance rf = 15. The load resistor, R = 95 .
(a) Determine peak output voltage vo across the load, R
(b) Sketch the output voltage vo and label its peak value.
Numerical 1

5. SOLUTION:
vs (peak) = 125 / 25 = 5V
V + IDrf + IDR - vs(peak) = 0
0.6 + 15ID+ 95ID - 5 = 0
ID = (5 – 0.6) / 110 = 0.04 A
vo (peak) = 95 x 0.04 = 3.8 V
3.8V
Vo
t

6. Consider the battery charging circuit shown below.
Assume VB = 6 V, R = 120 Ω, VS = 18.6 V and vγ = 0.6 V. .
Determine the peak diode current, maximum reverse-bias diode voltage,
and the fraction of the wave cycle over which the diode is conducting.
Numerical 2

7. Numerical 2
( ) 18.6 0.6 6
( ) 100
120
s B
D
v peak v v
I peak mA
R

   
  
Solution:
Peak diode current
Maximum reverse-bias diode voltage
VRB = VB + VS = 6 + 18.6 = 24.6 V
- VRB +
+
-

8. 1 1
1
1 1
18.6sin 0.6 6.0 6.6
6.6
sin ( ) 20.783
18.6
B
v t V V V
t



  
     
  
The diode conduction is started with phase angle of the wave
2 2 180 20.783 159.217
t 
 
   
So the % of conduction of diode with respect to
full cycle of the wave is
2 1 159.217 20.783
*100 *100 38.453%
360 360
 
 
 

9. Numerical 3
(a) Sketch the output voltage vo(t) and determine its average dc level
assuming the diode to be ideal.
(b) Repeat part (a) for a real silicon diode with vγ = 0.7 V.

10. Solution: (a)
For half-wave rectifier, the avg dc level is
Vdc = -Vm/π = -0.318(20 V) = -6.36 V
The negative sign indicates that the polarity of the output is opposite to
the defined polarity of figure below

11. (b) For a silicon diode, the output has the appearance below
Vdc = -0.318(Vm - 0.7) V = -0.318(19.3 V) = -6.14 V
The resulting drop in dc level is 0.22 V, or about 3.5%.

12. Determine the output waveform vo(t) for the network below. Calculate the
average dc level and the required PIV for each diode.
Numerical 4

13. Solution:
1
2
o i
v v

max max
1 1 (10 ) 5
2 2
o i
V V V V
  
PIV = Vo(max) = 5 V

14. Vdc = 2vo,max/π = 0.636(5 V) = 3.18 V
For the negative part of the input, the roles of the diodes are interchanged
but vo remains the same => circuit acts as full-wave rectifier

15. Numerical 5
Determine vo(t) for the network below.

16. Solution:
Determining the transition level
For vi ≥ 4 V, vo = vi
For vi ≤ 4 V, vo = 4 V

17. Numerical 6
Determine vo(t) for the network below.

18. Solution: Note that the frequency is 1000 Hz, resulting in a period of 1 ms
and an interval of 0.5 ms between transitions. Consider the negative input
half-cycle first,
The result is vo = 5 V for this interval.
Applying Kirchhoff’s voltage law around the input loop results in
-20 + VC − 5 = 0 => VC = 25 V

19. The capacitor will therefore charge up to 25 V. Now consider the positive input
half-cycle,
Applying Kirchhoff’s Voltage Law around the outside loop results in,
10 + 25 − vo = 0 => vo = 35 V

20. The time constant of the discharging network is determined as
τ = RC = (100 kΩ)(0.1 μF) = 0.01 s = 10 ms >> 0.5 ms
Thus, it is certainly a good approximation that the capacitor will hold its
voltage during the positive period of the input signal.

21. Clamping Network with a Sinusoidal Input

22. Numerical 7
Determine vo for the network below.

24. Voltage Ripple in Rectifier circuits
In any case of rectification, the amount of AC voltage mixed with
rectifier's pure DC output is called ripple voltage.
If power levels are not too high, filtering networks may be
employed to reduce amount of ripple in output voltage.

25. OUTPUT FILTER CAPACITOR DESIGN TO
LIMIT THE OUTPUT VOLTAGE RIPPLE
Full wave rectifier with
centre tapped
transformer
Equivalent Circuit model with
added capacitive filter
25

26. 26
Vo(max) = Vm
Ripple voltage Vr(pp) = Vo(max) - Vo(min)
α

27. 27
α
(min)
1
(min) sin( ) sin
o
o m
m
V
V V or
V
    
   
 

28. α
28
𝑣𝑜 𝑡 = 𝑉
𝑚𝑒
−
𝑡
𝑅𝐿𝐶𝑒
(min)
( ) ...(2)
d
L e
t
R C
o d o m
v t t V V e

  
(min)
ln .....(3)
m
d L e
o
V
t R C
V
 
  
 
 
=>

29. Substituting the expressions for td and α into above equation,
(min)
1
(min)
(min)
1
(min)
ln 2 2 sin
Therefore,the filter capacitor can be found from
2 sin
..............(4)
ln
o
m
L e
m
o
e
o
m
e
m
L
o
V
V
R C
V
V
C
V
V
C
V
R
V
   




   
   
   
   
 
 
  
 

 
 
 
  29
......(1)
2
d
t 
  
  

30. α
( )
0
( ) cos( ) ( )
1 sin ......(5)
L e
L e
t
R C
m
o av
R C
m
L e
V
V e d t t d t
V
R C e

 



  

 



 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
30
Redefining the time origin
(ωt = 0) at π/2 when the
discharging interval begins,
we can find the average
output voltage Vo(av) as

31. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
We can derive simpler explicit expressions for the ripple voltage in terms of the
capacitor value if we make the following assumptions:
(1) The charging time tc is small compared to the discharging time td i.e. td >> tc,
we can relate td to the period T of the input supply as
td = T/2 - tc ≈ T/2 = 1/2f
(2) Use Taylor series expansion of e−x ≈ 1 − x for a small value of x << 1,
assuming the capacitor doesn’t discharge much
(min) 1 .....(7)
d L e
t R C d
o m m
L e
t
V V e V
R C
  
  
 
 
31

32. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
The peak-to-peak ripple voltage Vr(pp) is:
The above expression can be used to find the value of capacitor Ce with a
reasonable accuracy for most practical purposes as long as the ripple factor (i.e.
Vr(pp)/2Vo(av)) is within 10%.
The ripple voltage depends inversely on the supply frequency f, the filter
capacitance Ce, and the load resistance RL.
( ) (min) .........(8)
2
d m
r pp m o m
L e L e
t V
V V V V
R C fR C
   
32

33. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
If we assume that the output voltage decreases linearly from Vo(max)(=Vm) to Vo(min)
during the discharging interval, the average output voltage can be found
approximately from
33
(min)
( )
( )
1
1 ....(9)
2 2
Which after substituting becomes
1 1 1
1 2 ..(10)
2 2 2 2
m o d
o av m m
L e
d
m
o av m m
L e L e
V V t
V V V
R C
t
V
V V V
R fC R fC
 
  
   
 
 
 
 
 
   
    
 
   
   
 

34. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
The ripple factor RF can be found from
• The peak input voltage Vm is generally fixed by the supply, where the
minimum voltage Vo(min) can be varied from almost 0 to Vm by varying the
values of Ce and/or RL.
• Therefore, it is possible to design for an average output voltage Vo(dc) in the
range from 2Vm/π to Vm.
34
( )
( )
/ 2 1
.............(11)
4 1
r pp
o av L e
V
RF
V R fC
 


35. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
In summary, expressions for Ripple Factor (RF), average output (dc)
voltage (Vo(av)) and filter capacitor Ce are related as:
( )
1
2
2 2
m
o av
L e
V
V
R fC
 
 
 
 
1
4 1
L e
RF
R fC


1 1
1
4
e
C
fR RF
 
 
 
 
35

36. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
Numerical Example:
A single-phase bridge-rectifier is supplied from a 120-V, 60-Hz
source. The load resistance is R = 500 Ω.
(a) Design a C filter so that the ripple factor of the output
voltage is less than 5%.
(b) With the value of capacitor C in part (a), calculate the
average load voltage Vdc.
36

37. OUTPUT FILTER CAPACITOR DESIGN TO LIMIT THE
OUTPUT VOLTAGE RIPPLE
Solution:
RF =5% =0.05 ,
(a)
(b)
37
1 1 1 1
1 1 175
4 4 60 500 0.05
C F
fR RF

   
    
   
 
   
120 2 169.7 169
m
V V V
   
( )
1 169 1
2 2 161V
2 2 2 500 2 60
m
o av
L e e
V
V
R fC C
   
    
   
  
   