The document describes the fabrication process of an integrated circuit with a PMOS transistor. Key steps include: 1) Starting with a silicon wafer and doping it with an N-type impurity. 2) Depositing silicon dioxide and using photolithography to pattern areas for doping. 3) Doping with boron to create P-well, P-type source and drain regions. 4) Depositing polysilicon and patterning it to form the transistor gate. 5) Connecting the doped regions and gate with aluminum interconnects to complete the PMOS transistor.

1. BY:-
K16ES07
TOPIC :- K16ES41 .
FABRICATION OF INTEGRATED CIRCUITE K16ES39 .

2. Integrated circuit
A chip or microchip, is a semiconductor wafer
on which thousands or millions of tiny
resistors, capacitors, and transistors are
fabricated .

3. 1) Wafer production
2) Masking
3) Etching
4) Doping
5) Metallization

4. 1) Wafer production
 Wafer is round silica of semiconductor material such
as silicon
 First purified polycrystalline silicon is created from
the sand
 it is heated to produce molten liquid
 A small piece of solid silicon is dipped on the
molten liquid
 Solid silicon (seed) is slowly pulled from the melt
 Liquid cools to form single crystal ingot

5. 2) Masking
 PHOTOLITHOGRAPHY is a technique that is used to transfer
The geometry patterns mask to wafer.

6. 3) Etching
 Etching is used to remove material selectively in order
to create patterns.
 The unmasked material can be removed either by etching.

7. 4) Doping
 To alter the electrical character of silicon, atom with one
less electron than silicon such as boron and atom with one
electron greater then silicon such as phosphorous are
Introduced into the area
 The P-type (boron) and N-type (phosphorous)
are created to reflect their conducting characteristics.
Ion
implantation
Atomic diffusion

8. 5) Metallization
 It is used to create contact with silicon and to make
interconnections on chip
 A thin layer of aluminum is deposited over the
whole wafer

9. P-WELL
A B C

11. P-WELL
n+ P+ n+ n+P+ P+
P-well
P-WELL

12. P-WELL
Primarily, start the process with a N-substrate

13. P-WELL
The oxidation process is done by using high-purity
oxygen and hydrogen. To form the layer of SiO2

14. P-WELL
A light-sensitive polymer that softens whenever exposed to
light is called as Photoresist layer. It is formed.

15. P-WELL
The photoresist is exposed to UV rays through
the P-well mask

16. P-WELL
A part of the photoresist layer is removed by treating the
wafer with the basic or acidic solution.

17. P-WELL
The SiO2 oxidation layer is removed through the open area
made by the removal of photoresist using hydrofluoric acid.

18. P-WELL
The entire photoresist layer is stripped off

19. P-WELL
using ion implantation or diffusion process P-well is
formed.
P-well

20. P-WELL
Using the hydrofluoric acid, the remaining SiO2 is
removed.
P-wellP-well

21. P-WELL
Chemical Vapor Deposition (CVD) process is used to deposit a very thin
layer of gate oxide.
P-wellP-well

22. P-WELL
Except the two small regions required for forming the Gates of
NMOS and PMOS, the remaining layer is stripped off
P-wellP-well

23. P-WELL
an oxidation layer is formed on this layer with two small regions for
the formation of the gate terminals of NMOS and PMOS.
P-well
P-well

24. P-WELL
By using the masking process small gaps are made for
the purpose of P-diffusion
P-wellP-well

25. P-WELL
The p-type (p+) dopants are diffused or ion implanted, and the three
p+ are formed for the formation of the terminals of PMOS.
P+ P+ P+
P-wellP-well

26. P-WELL
The remaining oxidation layer is stripped off
P+ P+ P+
P+ P+
P+
P-wellP-well

27. P-WELL
Similar to the above P-diffusion process, the N-diffusion regions
are diffused to form the terminals of the PMOS.
P+ P+ P+
P+ P+n+ n+ n+ P+
P-wellP-well

28. P-WELL
A thick-field oxide is formed in all regions except the
terminals of the PMOS and NMOS.
P+ P+n+ n+ n+ P+
P+ P+n+ n+ n+ P+
P-well P-well

29. P-WELL
Aluminum is sputtered on the whole wafer.
P+ P+n+ n+ n+ P+
P+ P+n+ n+ n+ P+
P-wellP-well

30. P-WELL
The excess metal is removed from the wafer layer.
P+ P+n+ n+ n+ P+
P-wellP-well

31. P-WELL
The terminals of the PMOS and NMOS are made from
respective gaps
P+n+ P+ n+n+ P+
n+ P+ n+ n+P+ P+
P-wellP-well
P-mos
N-mos

33. P-WELL P-mos
 A PMOS transistor is made up of p-type source and
drain and a n-type substrate.
 A high voltage on the gate will cause a PMOS not to
conduct, while a low voltage on the gate will cause it to
conduct
 PMOS technology is low cost and has a good noise
immunity.

34. P-WELL P-mos
 Take Pure Si single crystal

35. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 N-type impurity is lightly doped

36. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 SiO2 Deposited over si surface
Thick SiO2
(1 µm)

37. P-WELL P-mos
Thick SiO2
(1 µm)
Photoresist
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Photoresist is deposited over SiO2 layer

38. P-WELL P-mos
Photoresist
Thick SiO2
(1 µm)
UV Light
Mask-1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 Photoresist layer is exposed
to UV Light through a mask

39. P-WELL P-mos
Polymerised
Photoresist
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Developer
removes
unpolymerised
photoresist. It will
cause no effect on
Si surface

40. P-WELL P-mos
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 Etching [HF acid is used] will remove SiO2 layer which is in
direct contact with etching solution

41. P-WELL P-mos
Thick SiO2
(1 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 unpolymerised photoresist is also etched away [using H2SO4]

42. P-WELL P-mos
Thick SiO2
(1 µm)
Thin SiO2
(0.1 µm)
Polysilicon layer
(1 – 2 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 A thin layer of polysilicon is grown over the entire chip
surface to form GATE

43. P-WELL P-mos
Thick SiO2
(1 µm)
Thin SiO2
(0.1 µm)
Polysilicon
layer
Photoresist
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 A layer of photoresist is grown over polysilicon layer

44. P-WELL P-mos
UV Light
Mask-2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Mask-2 is used to deposit
Polysilicon to form gate.
 Photoresist is exposed to UV Light

45. P-WELL P-mos
Thick SiO2
(1 µm)
Thin SiO2
(0.1 µm)
Polysilicon
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 Etching will remove that portion
of Thin SiO2 which is not exposed to
UV light

46. P-WELL P-mos
Thick SiO2
(1 µm)
Thin SiO2
(0.1 µm)
Polysilicon used as GATE
(1 – 2 µm)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 Polymerised photoresist is also stripped away

47. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
Thin SiO2
(0.1 µm)
GATE
- - -
- - -
n+
- - - -
- -
n+
SOURCE DRAIN
p p
 P+ Doping to form SOURCE and DRAIN

48. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
p p
 A thick layer of SiO2 (1 µm) is again grown.

49. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Photoresist
Mask-3
UV Light
Mask-3 is used to make contact cuts for S, D and G.
p p
 Photoresist is grown over thick
SiO2. Selected areas of the poly GATE
and SOURCE and DRAIN are exposed
where contact cuts are to be made

50. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Photoresist
Mask-3
p p
The region of photoresist which is not
exposed by UV light will become
soft. This unpolymerised photoresist and
SiO2 below it are etched away.

51. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Photoresist
Mask-3
p p
 The contact cuts are formed for S,
D and G (hardened photoresist is
stripped away).

52. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Metal (1µm)
p p
 Metal (aluminium) is deposited over the surface of whole
chip (1 µm thickness).

53. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Metal (1µm)
Photoresist
p p
 Photoresist is deposited over the metal.

54. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Metal (1µm)
Photoresist
UV Light
Mask-4
Mask-4 is used to deposit metal in contact cuts of S, D and G.
p p
 UV Light is passed through Mask-4
(with a aim of removing all metal
other than metal in contact-cuts).

55. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Thick SiO2
(1 µm)
- - -
- - -
n+
- - - -
- -
n+ Thick SiO2
(1 µm)
Metal (1µm)
Photoresist
Mask-4
p p
 Photoresist and metal which is not exposed to UV
light are etched away

56. P-WELL P-mos
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - -
- - -
n+
- - - -
- -
n+
SOURCE DRAIN
GATE
p p
 Final P-MOS Transistor

58. P-WELL P-mos
n+ P+ n+ n+P+ P+
P-well
P-mos
N-mos

59. P-WELL P-mos
Step1:
N or p type substrate is taken Initially
Step2:
Epitaxial Layer Deposition, Lightly Doped Epitaxial
Layer is Deposited above n+ or p+ Substrate.
Step3:
Tub Formation
n -well-Formation
Protect certain region in this by using an oxide nitride
mask
Phosphorus implantation
Form n-well
The oxide is going to be formed only over the n-well

60. P-WELL P-mos
Step4:
p -well-Formation
Protect certain region in this by using an oxide nitride mask
Boron implantation
Form p-well
Entire substrate to an oxidation process
Implant The p-well
Step 5:
Polysilicon gates Are Formed for n-well and p-well by Using Photo-Etching
Process
Step 6:
n+ Diffusion is Formed in p-well
p+ Diffusion is Formed in n-well
Step 7:
Metalization Process (Metal Contacts Are Created)