Enabling the Duo-phase Data Management to Realize Longevity Bit-alterable Flash Memory Paper presentation

1. Enabling the Duo-phase Data
Management to Realize Longevity
Bit-alterable Flash Memory
Speaker: Po-Chuan Chen

2. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Flash memory
• Bit-alterable flash memory
• Related works
• Duo-Phase Data Management Scheme
• Bit-count Regulator
• Hot-page monitor
• Data placement strategy
• Duo-phase G.C.
• Algorithm for operations
• Memory footprint analysis
• Further discussions
• Evaluation
• Conclusion

3. Abstract
• Bit-alterable flash memory is a cutting-edge technology that enables a
novel operation, called page-level erase operation.
• But it introduces a new wear-leveling problem that flash pages within
the same block will receive different program/erase (P/E) cycles
during runtime.

4. About this paper
• A duo-phase data management scheme considering the page-level
wear-leveling issue.
• This mechanism simultaneously cares about page- and block-level
wear-leveling issues.

5. Introduction
• Bit-alterable flash memory, might totally avoid the live-page-copying
overhead because of the enabled page level erase operation.

6. Page level wear-leveling issue
• Because some flash pages within the bit-alterable flash memory will
be frequently erased by page level erase operations for avoiding
copying live pages.
• So, the frequently-erased flash pages will reach the limited number of
erase cycles soon.

7. A duo-phase method
 Bit-count regulator
 Hot-page monitor
 Data placement strategy
 Duo-phase garbage collector

8. Contribution
• The pioneer to propose a complete solution for the page-level wear-leveling
issue with the bit-alterable flash memory.
• A lightweight solution for FTL management.
(193.52KB size for 128 GB flash memory)
• It can prolong the lifetime of bit-alterable flash memory by 1.5 to 1.9 times.

9. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Flash memory
• Bit-alterable flash memory
• Related works
• Duo-Phase Data Management Scheme
• Bit-count Regulator
• Hot-page monitor
• Data placement strategy
• Duo-phase G.C.
• Algorithm for operations
• Memory footprint analysis
• Further discussions
• Evaluation
• Conclusion

10. The differences between a conventional and bit-alterable flash memory.
It doesn’t need to copy valid pages anymore.
This is because the bit-alterable flash memory
can simultaneously modify multiple
selected bits in a flash page
to support a page erase operation

11. Bit-alterable Flash Memory
GSL : Ground Select Line
WL : Word Line
SSL : Source Select Line

12. Related Works
• For bit-alterable flash memory, about the page-level and block-level
management, some researchers just claimed that the traditional FTL
can resolve the related issue. But actually it can’t.
• And the page-level wear-leveling issue is still an unsolved and urgent
problem since the bit-alterable flash memory can support page-level
erase operations.

13. Page-level wear-leveling issue
The main problem for this study is how
to achieve page-level wear-leveling
inside a flash block with a nearly-zero
performance overhead
and small memory footprint.

14. Some challenges
 A lightweight method should be developed for achieving page-level
wear-leveling in a flash block.
 Hot pages should be monitored and processed for avoiding accumulating
erase counts on these flash pages.
 A new garbage collection mechanism which choosing the appropriate
victim flash block with the considerations of both performance efficiency
and flash memory lifetime.

15. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Flash memory
• Bit-alterable flash memory
• Related works
• Duo-Phase Data Management Scheme
• Bit-count Regulator
• Hot-page monitor
• Data placement strategy
• Duo-phase G.C.
• Algorithm for operations
• Memory footprint analysis
• Further discussions
• Evaluation
• Conclusion

16. Overview
1. A bit counter as a regulator to
count the number of page-level
erase operations on flash pages.
2. The hot-page monitor will
allocate iron-hot flash pages
for icy-cold data
3. Data placement strategy
within the proposed duo-phase
scheme will cope with all write
requests from the host system
side or garbage collection (GC)
processes.
4. Specialized garbage collector
dedicates on victim selection
and inner/inter block wear-
leveling issues.
(a page or block-level erase
operation for reclaiming invalid
spaces)

17. Bit-count Regulator
• Goal :
It helps the proposed scheme to identify hot flash pages by using few bits.
• Method :
With the bit-count regulator, the number of page-level operations per
flash page will be represented by a few bits stored in the spare area of
the flash page.

18. Hot-page monitor
• Goal :
A hot-page monitor that maintains some iron hot flash pages.
• Method :
It needs , an urgent list to keep the information of iron hot flash pages;
and is enlisted in the hot page monitor. (insertion/deletion)
So, the duo-phase data management scheme has the ability to store
icy cold data into iron hot flash pages.

19. Data placement strategy
• Goal :
To place data into the right flash page space.
• Method :
The duo-phase scheme classified free flash blocks into six different
lists according to its program/erase cycle (young/old) and the MSB
information of the free page within the block (1/0/mixed).
Old
Young

20. When new data write
• Based on the free list design, the data placement strategy will allocate
free spaces to all new written/updated data by finding the free flash
page in the order from P6 to P1 (young to old).

21. When garbage collection
• Categorizing the garbage collection (GC) data into two types:
Old and new data.
• Allocating the free space for the old GC data by checking the free pages
in the urgent list.
• If no free pages are in the urgent list, the data placement strategy will
allocate the space for old GC data by checking free lists in the order
from P1 to P6 (old to young), it can cool down hot flash pages.

22. Duo-phase GC
• Goal :
Try to solve the page-level wear-leveling issue
• Method :
The duo-phase scheme includes a duo-phase garbage collector that can
select the most performance-efficient way to do garbage collection,
considering the inner-block wear-leveling issue.
(performance-oriented victim selector / a page-level wear-leveling strategy)

23. Performance-oriented Victim Selection
• Based on the latencies of page-level and block-level garbage
collection processes.
• If the threshold is positive, choosing block-level GC, otherwise
choose page-level GC
T_Eb : block erase latency
T_Cp : the latency of copying a valid page
N_Valp : the number of valid pages
T_Ep : page erase latency
N_Ialp : the number of invalid pages

24. Calculating efficiency
• Equation 2 presents how to evaluate the efficiency of a garbage
collection process when a block-level GC operation is selected.
• While a flash block is reclaimed its invalid spaces by a page-level GC
operation, the performance efficiency of the flash block can be
estimated by Equation 3.
T_Eb : block erase latency
T_Cp : the latency of copying a valid page
N_Valp : the number of valid pages
T_Ep : page erase latency
N_Ialp : the number of invalid pages
N_IWLp : the number of pages used in
inner-block wear leveling strategy

25. Inner-block Wear-leveling Strategy
• The inner-block wear-leveling strategy will move data stored in the
flash page with MSB 0 to another free page with MSB 1.
N_Valp : the number of valid pages
N_Ialp : the number of invalid pages
N_MSB1 : the number of flash pages
whose MSB is 1
N_MSB0 : the number of flash pages
whose MSB is 0
N_IWLp : the number of pages used in
inner-block wear leveling strategy
Valid → Invalid / MSB 0 → MSB 1

26. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Flash memory
• Bit-alterable flash memory
• Related works
• Duo-Phase Data Management Scheme
• Bit-count Regulator
• Hot-page monitor
• Data placement strategy
• Duo-phase G.C.
• Algorithm for operations
• Memory footprint analysis
• Further discussions
• Evaluation
• Conclusion

27. Operations of Duo-phase Data Management
• Algorithm 1 is data allocation process.
• Algorithm 2 summarizes the operations of a block-level garbage
collection process.

28. Data allocation
 Check the request is “write”
 Check the free space list from 6 → 1 (young to old)
 The free page with MSB 0 will be firstly selected
(in block 5 ~ block 2)
 After 3, if the block still has free pages, it won’t
be removed from free space list
 But if no free space in the free space list,
the Algorithm will check urgent list, and it will
return the allocated block & page numbers
to the address translator
1
2
3
4
5

29. Data movement
 If is the block level, it will move the valid data to the appropriate
pages according to the age of valid data.
 If the valid data are young, treating as newly-written data.
 Or old valid data will be copied to the old block; first check the
space maintained in the urgent list. If there are no free pages, it
will find a free space by searching the free space lists in the
order from 1 to 6.
 Because of old data, the data movement process will firstly
select free pages with MSB 1 to be the destination for live-page
copying, while P2 or P5 is visited.
 If it picks up a page-level garbage collection process, all invalid
pages will be erased at first, and the inner-block wear-leveling
process will be taken.
2
3
4

30. Memory footprint analysis
• Based on this case, the memory footprint is the sum of 128 KB
(derived from 32,768 × four bytes), 24 Bytes (derived from 6 × four
bytes), and 65.5 KB (derived from 8,389 × eight bytes).
• Compared with the capacity of flash memory, the memory footprint is
only 193.52 KB that is negligible.
N_B : the number of block
S_TS : the size of time stamp
S_P : the size of pointer
N_PU : the number of flash pages
S_UL : the size of urgent list

31. Further discussions
• Multi-level Cell Flash Memory (TLC/QLC locality)
• Multi-channel Flash Memory Drive (individual do GC in mlti-chip)

32. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Flash memory
• Bit-alterable flash memory
• Related works
• Duo-Phase Data Management Scheme
• Bit-count Regulator
• Hot-page monitor
• Data placement strategy
• Duo-phase G.C.
• Algorithm for operations
• Memory footprint analysis
• Further discussions
• Evaluation
• Conclusion

33. Set up

34. The real-world I/O trace (Write-intensive)

35. The proxy trace (Read intensive)

36. Advanced analysis
• Page erase latency : stable & acceptable
• The number of bit in regulator :
The lifetime decrease as the number of bits in the
regulator counter increase because the gap
between the maximum and minimum erase count
in the same block become large.
• The 95/99th Percentile Latency :
the longest latency but acceptable

37. Conclusion
• This study is the first work to point out the page-level wear-leveling
issue with the bit-alterable flash memory.
• Proposing a novel data management solution, namely the duo-phase
data management scheme.
• The proposed data management scheme can extend the bit-alterable
flash memory lifespan by 1.5 to 1.9 times, compared with other
solutions.