EGRE 254- Digital Logic Design

Jose Ramirez EGRE 254-Digital Logic State Machine
EGRE 254 – Digital Logic Design
State Machine: Traffic Light
Jose Ramirez

Abstract: This report examines the implementation of a state machine which incorporates ten states that
mimic the operation of a two different traffic light intersection road models. A busy road model and a quiet
road model. Designed, built, and assessed using D flip-flops, standard gates (AND, OR, & NOT), and six
LED’s (2 Red, 2 Green, and 2Yellow).
I. Theoretical Background
Consider a Traffic light Intersection, an example of state machine, Using D flip-flops and
standard gates, a two different models of traffic light intersection, a busy road model and quite
model, may be mimicked using 10 states, (five red states, four green states, and one yellow
state). A state diagram implemented illustrates the behavior of the each stable state, holding a
reasonable abstraction on how the traffic light intersections transition its state conditions from
one previous state to another.
Refer to (Figure 1), A state diagram of a two models of Traffic light intersections holding 10
states (R0,R1,R2,R3,R4,G0,G1,G2,G3,& Y1) , S1-10 respectively. Each state corresponding to a
4 binary bit number with a 2 bit input specified „00‟,‟01‟,‟10‟or „11‟ that signifies when and
where one state will transition to the next. (Figure 1) below holds a key color coded for the
combination of the 2 bit input, “E‟= Busy „1‟ or Quite „0‟ road model where as the “F‟ is when
the red state is triggered.‟1‟ on „0‟. When triggered the stop light should finish it cycle through
all the states until it gets back to the red state, where then it will stay at the red state until the “F”
is de-asserted to „0‟ allowing for the cycle through the states to continue.
Figure 1: Traffic Light Intersection Model State Diagram
Comprehension of how the state diagram works and how the bits transition from one state to
another, Allows for an implementation of truth table in which some of the inputs are the current
state, and the outputs include the next state, along with the corresponding outputs, Maps out the
Previous State (PS) and Next State (NS) inputs in correspondence to the outputs, Refer to figure

(Table 1) for state transition table, (Table 1.b) for State bit table , showing how all the 4 bit
combinations for each transition , with the (Table 1.a) signifying all 4 bit combinations for each
different state.
Table 1: State Transition Table
Table 1.a: State Assignment Table 1.b: State Transition Bit Table
(Table 1.b) hold a (Previous State=PS) cell corresponding to the previous state, labeled ABCD
respectively and the (Next State=NS) „00‟,‟01‟,‟10‟or „11‟ 2 bit input, with specified output for
WXYZ respectively. Each combination of bits corresponds to a cell on a Karnaugh map. For
each next state output W,X,Y,Z you get a specific equation corresponding to each respectively.
PSA‟0‟ PSB „0‟ PSC „0‟ PSD „0‟ NS0X  outputs „0, and so on for the rest of the cells 0-63 on

each map. Refer to (Kmap-W) (Kmap-X) ,(Kmap-Y) ,(Kmap-Z) and corresponding functions
with respected equations. Given that the problem holds 6 variables to take into account, 6
variable kmaps had to be implemented show all possible combinations, to give us specified
equations that are then easier to implement using a D flip-flops and Standard Logic Gates.
All four Kmaps hold the same don‟t cares functions that symbolize bits „1010‟-„1111‟ that are
not used in the state transition table refer to table (Table 1)
Each equations from each K-map corresponds to an input to a D-flip-flop and each output of the
D flip-flop corresponds to the specific bit input A,B,C,D. Allowing for the state machine to keep
it State in memory until the it transitions to the next state. The state machine holds two user
inputs (E) and (F) which is controlled by a switch. The state machine, when passed a „00‟ bit as
its input, symbolizes E=0, and F=0. Showing in (Figure 1), (E) is the bit which signifies a busy

model for the intersection or a quite model for the intersection. Whereas the (F) bit signifies
when both stoplights in the intersection regarding the state cycle to the red state and hold their
state at the red (R0) or (R4) when „1‟ the bit respectively, „0‟ to release. The E state models a
busy road when „1‟ is passed holding 2 states of red , 4 green and 1 yellow, Whereas when „0‟ is
passed moves to the quite model holding 3 states of red, 3 green and 1 yellow.
Each output (RED, GREEN, or YELLOW) for the each of the lights (LIGHT 1) and (LIGHT 2)
showing in (Table 1.b) holds its own specific equation, from the state bit stable (Table 1.b) an
equation can also be derived from a K-map where each bit (PS) A,B,C,D respectively hold a
specific equation for the specified output for each light 1 and 2. Each light has a specified K-
map which a function and equation is obtained. Refer to (K-map_Red-1,2), (K-map_Green-
1,2), (Kmap_Yellow-1,2) for Light #1 For Light #2 respectively ,below with specified functions
and equations.
(K-map_Red-1,2)
(K-map_Green-1,2)
(Kmap_Yellow-1,2)

Acquiring all equations at simplest terms from the k-maps, one can derive a complete schematic
implementation using D Flip-Flops and standard logic gates. Where the outputs of
K-map_W,X,Y,Z respectively each go into a specified D flip-flop‟s „D‟ input and the output of
the flip-flops each hold inputs to the output equations.(K-map_Yellow-1,2),(Green-1,2),(Red-
1,2) respectively. Refer to (Schematic W), (Schematic X), (Schematic Y) ,&(Schematic Z) for
inputs equations for the D Flip-flops A-D. Specified equations shown below each schematic.
(Schematic W)
W=CDB+E’CB+FCDFAD
(Schematic X) (Schematic Y)
X=C’B+ADF’+B’F’CD+BD’E Y=A’C’D+ECD’+B’CD’+EA’B’C’
(Schematic Z)
Z=A’C’D’+ECD’+FB’C+A’C’B’E+FAD+A’B’D’+A’D’E

Similarly the equations from the RED1&2 , YELLOW1&2, and GREEN1&2 output Kmaps ,
represent the schematics below (Schematic Red-1), (Schematic Red-2), (Schematic Green-1)
(Schematic Green-2), (Schematic Yellow-1), (Schematic Yellow-2), with specified equations
below. Each schematic also takes the input of the D flips flops and the specified output is the are
the Light 1 or Light 2‟s LED‟s: , Red , Green or Yellow respectively.
(Schematic Red-1) (Schematic Red-2)
Red-1=A’B’+B’C’D Red-2=A’B+AB’C’
(Schematic Green-1) (Schematic Green-2)
Green-1=A’B Green-2=A’B’C’+A’B’D’
(Schematic Yellow-1) (Schematic Yellow-2)
Yellow-1=AB’C’D’ Yellow-2= A’B’CD

II. Procedure:
To verify that the theoretical results, form the K-maps are functionally correct, An
implementation the traffic light intersection design was build and assessed using Xilinx ISE
software and a BASYS2 board with PMOD connectors as well as light emitting diodes. 6
LED‟s Colored (2Green, 2Red, 2Yellow) on a CADET training Board. Comparing the results
to the output of the traffic light simulated using Xilinx software, observe and verify that the
timing diagram confirms the output of the implementation of the LEDs timing on the proto-
board. Similarly verify that the right number of clock cycles correspond to the different states
R0,R1,R2,R3,G1,G2,G3,Y1, for when the traffic light intersection is switched from a busy
model to a quite model. Finally test input is correctly implemented, switching the state from
„0‟ to „1‟, should hold the state to the „Red‟ regardless of the timing of the clock at that
specific time. Verify all bits when imputed output the correct states in the state diagram table
(Table 1) for the different bit „00‟,‟01‟,‟10‟,‟11‟.
III. Results:
Main Schematic 1: Traffic Light Intersection Model

The output for the Traffic Light intersection schematic should resemble the timing diagram seen
below (Diagram 1). Green and yellow , should not be at the same time as Red, for that would be
unreasonalble combination. The state diagram assess that will never occur.
Diagram 1: Timing Diagram for Traffic Light Schematic with Test Bench
Traffic Light Intersection Implementation on Using BASYS2 board on CADET
Training Board using 6 LED’s and resistors,
Results confirmed Theoretical Background

IV. Conclusion:
A traffic light intersection, an example of a Moore-type state machine fully powered by D
Flip-Flops and Standards logic gates in Xilinx Software. This state machine may be fully
implemented and tested on a CADET training board with a BASYS2 board for added simplistic
measures Specified inputs which go through a series of logic gates to for a specified output, as
shown K-maps W,X,Y,Z, and K-maps Red1-2, Green1-2, and Yellow1-2 for the output logic
Respectively above, outputs of those functions obtained, are imputed into a present state storage
device, D Flip Flop, whose output is then passed back to the next state decoding logic or to the
output decoding logic , all happening synchronously with a clock signal.
Understanding the basic underlying workings of how a Moore state machine operates,
and obtaining the necessary equations for the inputs „E‟ and „F‟ and how they affect the path the
machine takes as seen in (Figure 1) above based on the specified inputs. The state machine,
when passed a ‟11 ,„01‟ or „10‟, „00‟ bits as the inputs respectively „E‟, „F‟. (Figure 1) above
shows the transition and outcomes of each combination. A simulation of a busy model or quite
model „1‟,‟0‟ for „E‟ respectively. Understanding how this works allows to further manipulation
the state machine to any desire number of states and outputs.
Implementation of this state machine on a Basys2 board allows for a far simpler
simulation implementation for the intersection. Relieving the user from a plethora of wiring,
using a Basys2 board or similar in manner. Shows the dexterity and power one may achieve with
today‟s technology for much more difficult and complex implementations of schematics
simulated using Xilinx ISE software.

EGRE 254- Digital Logic Design

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