This document summarizes the work of a group that designed and tested a static logic circuit. It includes the schematic and layout of both a complex and non-complex version of the circuit. Test results show the non-complex version has a larger area but lower leakage power and similar propagation delays. The group measured pre-layout and post-layout power and timing results, with minimal changes after layout.

1. AOI 321 Static Logic
Group Members :
• Najeeb Mohammad Khan- MT23217
• Farha Naz Ansari- MT23212
• Srasti Tiwari-MT23197
• Varun Gautam- MT23202
Group Number:11

2. Schematic + Sizing
Dimensions:
Wp = 1.54um
Wn = 1.02um
Lp = Ln = 0.15

3. Stimuli For Verification & Verification Plan

4. Stick diagram of Complex Circuit
Euler’s Path:
E -> D -> A -> B -> C -> F

5. Stick Diagram For Non-Complex

6. Layout of Complex
Wp = 1.54um
Wn = 1.02um
Ln=Lp= 0.15um
Area = 3.86*3.64 um^2

7. Non Complex layout without merging

8. Layout of Non-Complex after merging
Wp = 1.54um
Wn = 1.02um
Ln=Lp= 0.15um
Area = 7.99 * 3.64 um^2

9. LVS Reports
Complex Non Complex

10. Pre Complex Result
Parameters Pre-Post
Stimuli
Delay
(PVT: SS,
1.2V, -40C)
Delay
(PVT: SS,
1.2V, 125C)
Delay
(PVT: TT,
1.62V, 25C)
Delay
(PVT: FF,
1.8V, -40C)
Rise
Propagation
Delay
011110 
011010
3.284277 ns 0.9230308 ns 0.3052756 ns 0.1714242 ns
Fall
Propagation
Delay
110000 
111000
0.6305289 ns 0.7958079 ns 0.2447119 ns 0.1472172 ns
Rise
Contamination
Delay
000001 
000000
1.472759 ns 0.4140013 ns 0.1277128 ns 0.07085070 ns
Fall
Contamination
Delay
011010 
111111
0.1119829 ns 0.1220449 ns 0.04875733 ns 0.03466573 ns

11. Post Complex Result
Parameters Pre-Post
Stimuli
Delay
(PVT: SS,
1.2V, -40C)
Delay
(PVT: SS,
1.2V, 125C)
Delay
(PVT: TT,
1.62V, 25C)
Delay
(PVT: FF,
1.8V, -40C)
Rise
Propagation
Delay
011110 
011010
3.2849656 ns 0.9345815 ns 0.3097853 ns 0.1735832 ns
Fall
Propagation
Delay
110000 
111000
0.6312927 ns 0.8055868 ns 0.2519932 ns 0.1538435 ns
Rise
Contamination
Delay
000001 
000000
1.4732227 ns 0.4154002 ns 0.1275154 ns 0.07001901 ns
Fall
Contamination
Delay
011010 
111111
0.1119698 ns 0.1273313 ns 0.05555847 ns 0.0407864 ns

12. Pre Non-Complex Result
Parameters Pre-Post
Stimuli
Delay
(PVT: SS,
1.2V, -40C)
Delay
(PVT: SS,
1.2V, 125C)
Delay
(PVT: TT,
1.62V, 25C)
Delay
(PVT: FF,
1.8V, -40C)
Rise
Propagation
Delay
111000 
110000
1.262608 ns 0.6555060 ns 0.3097853 ns 0.1156088 ns
Fall
Propagation
Delay
110000 
111000
0.8630389 ns 0.6694178 ns 0.204033 ns 0.1485944 ns
Rise
Contamination
Delay
000001 
000000
1.0417971 ns 0.5456316 ns 0.1639647 ns 0.09142897 ns
Fall
Contamination
Delay
011010 
111111
0.4527108 ns 0.3819874 ns 0.1498188 ns 0.1033913 ns

13. Post Non-Complex Results
Parameters Pre-Post
Stimuli
Delay
(PVT: SS,
1.2V, -40C)
Delay
(PVT: SS,
1.2V, 125C)
Delay
(PVT: TT,
1.62V, 25C)
Delay
(PVT: FF,
1.8V, -40C)
Rise
Propagation
Delay
111000 
110000
1.375057 ns 0.7181779 ns 0.2231840 ns 0.1268425 ns
Fall
Propagation
Delay
110000 
111000
0.9716824 ns 0.7357060 ns 0.2533302 ns 0.1600795 ns
Rise
Contamination
Delay
000001 
000000
1.133741 ns 0.6030830 ns 0.1811502 ns 0.1011926 ns
Fall
Contamination
Delay
011010 
111111
0.5007009 ns 0.4099488 ns 0.1589804 ns 0.1085043 ns

14. Leakage Power - Complex v/s Non Complex
Complex Non Complex
Maximum Leakage 763.4686nW 3273.364nW
Minimum Leakage 1.120173nW 936.9990nW
Post Layout

15. Dynamic Power Comparison
Pre-Layout Post-Layout
Tpd_r 208.6515nW 210.8760nW
Tpd_f 10.07325nW 10.06325nW
Tcd_f 1.665322nW 2.432093nW
Tcd_r 193.3565nW 193.58nW
Pre-Layout Post-Layout
Tpd_r 255.9667nW 266.4759nW
Tpd_f 48.87005nW 58.37180nW
Tcd_f 67.87751nW 78.10449nW
Tcd_r 229.9827nW 240.9371nW
Complex
Non-Complex

16. Area Analysis
Complex Non-Complex
Area 3.86*3.64(um^2) 7.99*3.644(um^2)
The ratio of the area of non-complex layout to complex layout is 2.069 times.
(51.6% improvement)

17. Thank You