DIRECT MEMORY
ACCESS (DMA)
Sachin Motwani | ECE 3| 422
sachinmotwani20@ieee.org
Contents
BUS ARBITRATION DIRECT MEMORY ACCESS
(DMA)
DMA MODES
Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org Monday, November 16, 2020 2
Bus Arbitration
◦ The process by which the current bus master accesses and then leaves the control of
the bus and passes it to the another bus requesting processor unit.
◦ Bus Master: The controller that has access to a bus at an instance.
◦ Direct Memory Access (DMA) is the most common method of bus arbitration.
◦ Some other ways are fixed priority bus arbitration (figure on right bottom) or Daisy
chained bus arbitration (immediate bottom).
Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org Monday, November 16, 2020 3
arbitration /ɑːbɪˈtreɪʃ(ə)n/
noun. the hearing and determining of a dispute
or the settling of differences between parties by
a person or persons chosen or agreed to by
them
BRQ : Bus Request
BGT : Bus Grant
SACK : Selective
Acknowledgement
Direct Memory Access(DMA)
◦ In DMA, CPU is bypassed when transferring data from peripherals to memory.
◦ The DMA controller is used for this sole purpose and takes over the control of the bus.
◦ Important, as 𝜇𝑃 relinquishes control of the system to the DMA and carries out its regular tasks.
◦ Achievement:
- No unnecessary storing/ restoring of state due to ISR call (highly inefficient).
- Interrupt latency completely eliminated.
- Regular program need not wait for execution due to data transferring processes.
Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 4
Direct Memory Access(DMA) cont.
The task of a DMA-controller (DMAC) is to execute the copy
operation of data from one resource location to another.
The copy of data can be performed from:
Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 5
I/O
devices
memory
Memory
I/O
devices
Memory Memory
I/O
devices
I/O
devices
From To
“ A direct memory access (DMA) is an operation in which the data is copied (transponded) from one resource to another
recourse in a computer system without the involvement of the CPU.”
DMA Modes
◦ The DMA controller transfers the data in three modes:
1. Burst Mode; In this, once the DMAC gains control over the system bus, it releases the bus only after completion of the data transfer. Until
then, the CPU has to wait for the system buses.
2. Cycle Stealing Mode: In this, the DMA controller forces the CPU to stop its operations and relinquish the control over the bus for a short-
term to DMAC. After the transfer of every byte, the DMAC releases the bus and then again generates request for the system bus. In a way,
the DMAC steals the clock cycle for transferring every byte.
3. Transparent Mode: Here, the DMAC takes the charge of the system bus only if the processor doesn’t require the system bus.
Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 6
Thank You
Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 7

Direct memory access (dma)

  • 1.
    DIRECT MEMORY ACCESS (DMA) SachinMotwani | ECE 3| 422 sachinmotwani20@ieee.org
  • 2.
    Contents BUS ARBITRATION DIRECTMEMORY ACCESS (DMA) DMA MODES Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org Monday, November 16, 2020 2
  • 3.
    Bus Arbitration ◦ Theprocess by which the current bus master accesses and then leaves the control of the bus and passes it to the another bus requesting processor unit. ◦ Bus Master: The controller that has access to a bus at an instance. ◦ Direct Memory Access (DMA) is the most common method of bus arbitration. ◦ Some other ways are fixed priority bus arbitration (figure on right bottom) or Daisy chained bus arbitration (immediate bottom). Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org Monday, November 16, 2020 3 arbitration /ɑːbɪˈtreɪʃ(ə)n/ noun. the hearing and determining of a dispute or the settling of differences between parties by a person or persons chosen or agreed to by them BRQ : Bus Request BGT : Bus Grant SACK : Selective Acknowledgement
  • 4.
    Direct Memory Access(DMA) ◦In DMA, CPU is bypassed when transferring data from peripherals to memory. ◦ The DMA controller is used for this sole purpose and takes over the control of the bus. ◦ Important, as 𝜇𝑃 relinquishes control of the system to the DMA and carries out its regular tasks. ◦ Achievement: - No unnecessary storing/ restoring of state due to ISR call (highly inefficient). - Interrupt latency completely eliminated. - Regular program need not wait for execution due to data transferring processes. Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 4
  • 5.
    Direct Memory Access(DMA)cont. The task of a DMA-controller (DMAC) is to execute the copy operation of data from one resource location to another. The copy of data can be performed from: Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 5 I/O devices memory Memory I/O devices Memory Memory I/O devices I/O devices From To “ A direct memory access (DMA) is an operation in which the data is copied (transponded) from one resource to another recourse in a computer system without the involvement of the CPU.”
  • 6.
    DMA Modes ◦ TheDMA controller transfers the data in three modes: 1. Burst Mode; In this, once the DMAC gains control over the system bus, it releases the bus only after completion of the data transfer. Until then, the CPU has to wait for the system buses. 2. Cycle Stealing Mode: In this, the DMA controller forces the CPU to stop its operations and relinquish the control over the bus for a short- term to DMAC. After the transfer of every byte, the DMAC releases the bus and then again generates request for the system bus. In a way, the DMAC steals the clock cycle for transferring every byte. 3. Transparent Mode: Here, the DMAC takes the charge of the system bus only if the processor doesn’t require the system bus. Monday, November 16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 6
  • 7.
    Thank You Monday, November16, 2020Embedded Systems | Direct Memory Access (DMA) |Sachin Motwani | sachinmotwani20@ieee.org 7