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An Autonomous Institute
Affiliated to VTU, Belagavi,
Approved by AICTE, New Delhi,
Recognized by UGC with 2(f) & 12(B)
Accredited by NBA & NAAC
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT CODE : MVJ20EC36
SUBJECT NAME: COMPUTER ORGANIZATION AND ARCHITECTURE
LECTURE PRESENTATION MODULE – 1
FACULTY : Ms. Shruthi. N, Asst. Prof, Dept. of ECE .
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Syllabus for Course
• Module 1
• Basic Structure of Computers: Computer Types, Functional Units, Basic Operational Concepts, Bus
Structures, Software, Performance – Processor Clock, Basic Performance Equation
• Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE standard
for Floating point Numbers, Memory Location and Addresses, Memory Operations, Instructions and
Instruction Sequencing.
• Activity: To recognize various Components of a PC.
• Module 2
• Addressing Modes, Assembly Language, Basic Input and Output Operations, Stacks and Queues,
Subroutines, Additional Instructions.
• Activity: Write an ALP to find the sum of two numbers and verify if the sum is an even or odd number.
2
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• Module 3
• Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and
Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Direct Memory Access,
Buses.
• Activity: Study any one input/output device and examine its various input output ports working.
• Module 4
• Memory System: Basic Concepts, Semiconductor RAM Memories-Internal organization of memory
chips, Static memories, Asynchronous DRAMS, Read Only Memories, Cache Memories, Mapping
Functions, Replacement Algorithm, Virtual Memories, Secondary Storage-Magnetic Hard Disks.
• Activity: Implement and simulate a simple memory unit which is capable of reading and writing data
within a single clock cycle.
3
Syllabus for Course
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Syllabus for Course
• Module 5
• Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete
Instruction, Multiple Bus Organization, Hardwired Control, Microprogrammed Control
,Pipelining ,Basic concepts, Role of Cache memory, Pipeline Performance
• Activity: Show the possible control sequence for implementing any instruction for a single
bus organisation.
4
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Module 1 Structure
• Basic Structure of Computers:
• Computer Types, Functional Units,
• Basic Operational Concepts,
• Bus Structures, Software,
• Performance – Processor Clock, Basic Performance Equation
5
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Module 1 Structure
• Machine Instructions and Programs:
• Numbers, Arithmetic Operations and Characters,
• IEEE standard for Floating point Numbers,
• Memory Location and Addresses, Memory Operations,
• Instructions and Instruction Sequencing.
• Activity: To recognize various Components of a PC.
6
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Reference Books
• Carl Hamacher, ZvonkoVranesic, SafwatZaky: Computer Organization, 5th Edition, 2000.
• David A. Patterson, John L. Hennessy: Computer Organization and Design – The
Hardware / Software Interface ARM Edition, 4th Edition, Elsevier, 2009.
• William Stallings: Computer Organization & Architecture, 7th Edition, PHI, 2006.
• Vincent P. Heuring& Harry F. Jordan: Computer Systems Design and Architecture, 2nd
Edition, Pearson Education, 2004.
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Course Outcomes
8
After studying this course, students will be able to:
•Explain the basic organization of a computer system.
•Familiarization with various addressing modes and instruction.
•Explain different ways of accessing an input / output device including interrupts.
•Illustrate the organization of different types of semiconductor and other secondary storage memories.
•Illustrate simple processor organization based on hardwired control and micro programmed control and
Pipelining.
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Bridge Material
• Types of computer (on the basis of functionality)
•Compiler
•Multiprocessor and multicontroller
•Decimal to Binary conversion
•ASCII Chart
•Status bits
10
Basic Structure of Computers
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What is computer
A contemporary computer is a fast electronics calculating
machine that accepts digitized information, processes it
according to the list of internally stored instructions and
produces the resulting output information.
What is program?
The list of the instructions is called as computer program
and internal storage is called as computer memory.
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https://www.javatpoint.com/what-is-computer
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Types of Computer
On the basis of functionality.
On the basis of Size, Speed and Cost.
According to functionality computer can be divided in to three types:
1) Analog
2) Digital
3) Hybrid
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Analog Computer
•“An analog (spelled analogue in British English) computer is a
form of computer that uses the continuously- changeable
aspects of physical fact such as electrical, mechanical, or
hydraulic quantities to model the problem being solved.”
•Analog means continuity of associated quantity just like an
analog clock measures time by means of the distance travelled by
the hand of the clock around a dial.
•Example: Thermometer, Analog clock,
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Digital Computer
• “A computer that performs calculations and logical operations with quantities
represented as digits, usually in the binary number system of “0” and “1”.
•“Computer capable of solving problems by processing information expressed in
discrete form. By manipulating combinations of binary digits (“0”, “1”), it can
perform mathematical calculations, organize and analyze data, control industrial
and other processes, and simulate dynamic systems such as global weather
patterns. ”
•EXAMPLES: IBM PC, Digital watches etc
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Hybrid Computer
•A hybrid computer is a combination of computers that are
capable of inputting and outputting in both digital and analog
signals.
•Traditionally, the analog components of the computer handle
complex mathematical computations. The digital components
take care of logical and numerical operations in addition to
serving as the controller for the system.
•Hybrid computers for example are used for scientific
calculations, in defence and radar systems.
•Example: Notebook, Laptop etc.
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•A desktop computer is a personal computer designed for regular use at a
single location on or near a desk or table due to its size and power
requirements.
•The most common configuration has a case that houses the power
supply, motherboard (a printed circuit board with a microprocessor as
the central processing unit (CPU), memory, bus, and other electronic
components), disk storage (usually one or more hard disk drives, solid state
drives, optical disc drives, and in early models a floppy disk drive);
a keyboard and mouse for input; and a computer monitor, speakers, and, often,
a printer for output.
• The case may be oriented horizontally or vertically and placed either
underneath, beside, or on top of a desk.
Types of digital computer
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•A laptop (also laptop computer), often called a notebook, is a small,
portable personal computer (PC) with a "clamshell" form factor, typically
having a thin LCD or LED computer screen mounted on the inside of the upper
lid of the clamshell and an alphanumeric keyboard on the inside of the lower
lid.
•The clamshell is opened up to use the computer. Laptops are folded shut for
transportation, and thus are suitable for mobile use.
• Its name comes from lap, as it was deemed to be placed on a person's lap
when being used. Although originally there was a distinction between laptops
and notebooks (the former being bigger and heavier than the latter), as of 2014,
there is often no longer any difference.
Types of digital computer
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•A workstation is a special computer designed for technical
or scientific applications. Intended primarily to be used by one person
at a time, they are commonly connected to a local area network and
run multi-user operating systems.
•The term workstation has also been used loosely to refer to everything
from a mainframe computer terminal to a PC connected to a network,
but the most common form refers to the class of hardware offered by
several current companies such as Sun Microsystems, Silicon
Graphics, Apollo Computer, DEC, HP, NeXT and IBM which opened
the door for the 3D graphics animation revolution of the late 1990s.
Types of digital computer
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Computer
(on the basis of size,
speed and
performance)
Micro Computer Super Computer Mini Computer
Main-Frame
Computer
Types of computers
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Carl Hamacher, ZvonkoVranesic, SafwatZaky: Computer Organization, 5th Edition, 2000.
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Micro Computers
•It is difficult to overstate the impact of the micro computer on the
computer industry. In 1975, the micro computer did not exist. In
1995, sales exceeded $116 billion. Microcomputers are the fastest
growing segment of the computer industry.
•The micro computer segment of the industry is complex; there are
different types of microcomputer platforms with varying
capabilities. The most common type of microcomputer is a Desktop
Computer, which is a non portable Personal Computer that fits
on top of a desk. (will describe below).
•Microcomputers are the smallest and cheapest.
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Mini Computer
•The mini computers are small digital computers, which normally
process and store less data than mainframe but more than a
microcomputer. Minicomputer systems provide faster operating
speeds and larger storage capacities than microcomputer systems.
They are sometimes called mid-range computers, and are designed
to meet the computing needs for several people simultaneously in a
small to medium size business environment. They are used in
industries, research organizations, colleges and universities.
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Main Frame Computer
•It is a multi-user computer system which is capable of
supporting hundreds of users simultaneously. Software
technology is different from minicomputer.
•Mainframe is very large in size and is an expensive
computer capable of supporting hundreds or even
thousands of users simultaneously. Mainframe executes
many programs concurrently and supports many
simultaneous execution of programs.
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https://en.wikipedia.org/wiki/Mainframe_computer
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Servers
•Beyond workstations, a range of large and very
powerful computer system exists called servers. Servers
contain sizable database and storage units and are
capable of handling large volumes of requests to access
the data.
•In many cases servers are widely accessible to the
education, business and personal user communities.
The requests and responses are usually transported over
Internet communication facilities. The internet and its
associated servers have become a dominant world wide
source of all types of information
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Super Computer
•It is an extremely fast computer which can execute hundreds of
millions of instructions per second.
•Supercomputers are one of the fastest computers currently
available.
• Supercomputers are very expensive and are employed for
specialized applications that require immense amount of
mathematical calculations. For example, weather forecasting,
scientific simulations, (animated) graphics, fluid dynamic
calculations, nuclear energy research, electronic design, and
analysis of geological data.
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Functional Units
I/O Processor
Output
Memory
Input and
Arithmetic
logic
Control
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Information Handled by a Computer
• Instructions/machine instructions
• Govern the transfer of information within a computer as well as between the computer
and its I/O devices
• Specify the arithmetic and logic operations to be performed
• Program
• Data
• Used as operands by the instructions
• Encoded in binary code – 0 and 1
• Alphanumeric Characters- ASCII and EBCDIC
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Input Unit
• In computing, an input device is a piece of equipment used to provide data and control
signals to an information processing system such as a computer or information appliance.
Examples of input devices include keyboards, mouse, scanners, digital cameras,
joysticks, and microphones.
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Memory Unit
• Store programs and data
• Two classes of storage
Primary storage
Fast
Programs must be stored in memory while they are being executed
Large number of semiconductor storage cells
Processed in words
Address, RAM and memory access time, Memory hierarchy – cache, main memory
Secondary storage – larger and cheaper
28
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Arithmetic and Logic Unit (ALU)
• Most computer operations are executed in ALU of the processor.
• Load the operands into memory – bring them to the processor – perform operation in ALU
– store the result back to memory or retain in the processor.
• Registers
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Output Unit
• An output device is any piece of
computer hardware equipment which
converts information into human-
readable form. It can be text,
graphics, audio, and video. Some of
the output devices are Visual
Display Units (VDU) i.e. a Monitor,
Printer, Graphic Output devices,
Speakers
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Control Unit
• All computer operations are controlled by the control unit.
• The timing signals that govern the I/O transfers are also generated by the control unit.
• Control unit is usually distributed throughout the machine instead of standing alone.
• Operations of a computer:
Accept information in the form of programs and data through an input unit and store it in
the memory
Fetch the information stored in the memory, under program control, into an ALU, where
the information is processed
Output the processed information through an output unit
Control all activities inside the machine through a control unit
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Basic Operational Concepts
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Review
• Activity in a computer is governed by instructions.
• To perform a task, an appropriate program consisting of a list of instructions is stored in
the memory.
• Individual instructions are brought from the memory into the processor, which executes
the specified operations.
• Data to be used as operands are also stored in the memory.
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A Typical Instruction
• Add LOCA, R0
• Add the operand at memory location LOCA to the operand in a register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• Instruction is fetched from the memory into the processor – the operand at LOCA is fetched
and added to the contents of R0 – the resulting sum is stored in register R0.
34
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Separate Memory Access and ALU Operation
• Load LOCA, R1
• Add R1, R0
• Whose contents will be overwritten?
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Connection Between the Processor and the
Memory
• Programs reside in the memory through
input devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR
• A Read signal is sent to the memory
• The first instruction is read out and loaded
into MDR
• The contents of MDR are transferred to IR
• Decode and execute the instruction
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Registers
• Instruction register (IR)
• Program counter (PC)
• General-purpose register (R0 – Rn-1)
• Memory address register (MAR)
• Memory data register (MDR)
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Typical Operating Steps (Cont’)
• Get operands for ALU
General-purpose register
Memory (address to MAR – Read – MDR to ALU)
• Perform operation in ALU
• Store the result back
To general-purpose register
To memory (address to MAR, result to MDR – Write)
• During the execution, PC is incremented to the next instruction
• Interrupts
38
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Example
• List the steps needed to execute the machine instruction
Add LOCA, R0
Solution
• Transfer the contents of register PC to register MAR
• Issue a Read command to memory, and then wait until it
has transferred the requested word into register MDR
• Transfer the instruction from MDR into IR and decode it
• Transfer the address LOCA from IR to MAR
• Issue a Read command and wait until MDR is loaded
• Transfer contents of MDR to the ALU
• Transfer contents of R0 to the ALU
• Perform addition of the two operands in the ALU and
transfer result into R0
• Transfer contents of PC to ALU
• Add 1 to operand in ALU and transfer incremented address
to PC
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Example 2
• Repeat the above problem for
Add R1, R2, R3
Solution
• Transfer the contents of register PC to register MAR
• Issue a Read command to memory, and then wait until it has transferred the requested word
into register MDR
• Transfer the instruction from MDR into IR and decode it
• Transfer contents of R1 and R2 to the ALU
• Perform addition of two operands in the ALU and transfer answer into R3
• Transfer contents of PC to ALU
• Add 1 to operand in ALU and transfer incremented address to PC
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Interrupt
• Normal execution of programs may be preempted if some device requires urgent
servicing.
• The normal execution of the current program must be interrupted – the device raises an
interrupt signal.
• Interrupt-service routine
• Current system information backup and restore (PC, general-purpose registers, control
information, specific information)
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Bus Structures
• There are many ways to connect different parts inside a computer together.
• A group of lines that serves as a connecting path for several devices is called a bus.
• Address/data/control
• Bus can be used for only one transfer at a time
• The main virtue of single bus structure is its low cost and its flexibility for attaching
peripheral devices
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Bus Structure
• Single-bus
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• The devices connected to a bus vary widely in their speed of operation. To synchronize their
operational speed, the approach is to include buffer registers with the devices to hold the
information during transfers
• Buffer registers prevent a high-speed processor from being locked to a slow I/O device during
a sequence of data transfers.
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Speed Issue
• Different devices have different transfer/operate speed.
• If the speed of bus is bounded by the slowest device connected to it, the efficiency will be
very low.
• How to solve this?
• A common approach – use buffers.
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Performance
• The most important measure of a computer is how quickly it can execute programs.
• The speed with which a computer executes programs is affected by the design of its
hardware and its machine language instruction.
• Because programs are usually written in high level language, performance is also affected
by the compiler that translates programs into machine language.
• For best performance , it is necessary to design the compiler, the machine instruction set,
and the hardware in a coordinated way.
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Performance
• Processor time to execute a program depends on the hardware involved in the execution of
individual machine instructions.
Main
memory Processor
Bus
Cache
memory
The processor cache.
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Performance
• The processor and a relatively small cache memory can be fabricated on a single
integrated circuit chip.
• The internal speed of performing the basic steps of instruction processing on such chips
is very high and is considerably faster than the speed at which instructions and data can
be fetched from the main memory.
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Processor Clock
• Processor circuits are controlled by a timing signal called a Clock
• The clock defines regular time intervals called clock cycles
• To execute a machine instruction, the processor divides the action to be performed into a
sequence of basic steps such that each step can be completed in one clock cycle
• Let P=length of one clock cycle R=clock rate. Relation between P and R is given by R=1/P
which is measured in cycles per second.
• Cycles per second is also called hertz(Hz)
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Basic Performance Equation
• T – processor time required to execute a program that has been prepared in high-level
language
• N – number of actual machine language instructions needed to complete the execution (note:
loop)
• S – average number of basic steps needed to execute one machine instruction. Each step
completes in one clock cycle
• R – clock rate
• Note: these are not independent to each other
R
S
N
T


How to improve T?
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Example
• Computer A has clock cycle time of 250 ps. and CPI of 2.0 for some program and Computer B
has clock cycle time of 500 ps. and CPI of 1.2. Which computer is faster for this program and by
how much?
• Solution:
• Assume each computer executes Ninstructions, so
• CPU timeA = N × 2.0 × 250 = 500 × N ps
• CPU timeB = N × 1.2 × 500 = 600 × N ps
• A is faster by the ratio of execution times:
= execution timeB /execution timeA = 600 × N /500 × N = 1.2
50
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Clock Rate
• Increase clock rate
Improve the integrated-circuit (IC) technology to make the circuits faster
Reduce the amount of processing done in one basic step (however, this may increase the
number of basic steps needed)
• Increases in R that are entirely caused by improvements in IC technology affect all
aspects of the processor’s operation equally except the time to access the main memory.
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Performance Measurement
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Machine Instructions and Programs
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Memory Locations, Addresses, and
Operations
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Memory Location, Addresses, and Operation
• Memory consists of many millions
of storage cells, each of which can
store 1 bit.
• Data is usually accessed in n-bit
groups. n is called word length.
• The memory of computer can be
schematically represented as a
collection of words.
second word
first word
n bits
last word
i th word
•
•
•
•
•
•
55
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Memory Location, Addresses, and Operation
• 32-bit word length example
(b) Four characters
character
character
character character
(a) A signed integer
Sign bit: for positive numbers
for negative numbers
ASCII
ASCII
ASCII
ASCII
32 bits
8 bits 8 bits 8 bits 8 bits
b 31 b 30 b 1 b 0
b 31 0
=
b 31 1
=
•
•
•
56
If the word length of a computer is 32 bit a single word can store a 32 bit 2’s complement number or
four ASCII characters each occupying 8 bits
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ASCII Chart
https://images.app.goo.gl/8KBmaerjFC4DVmym6
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Memory Location, Addresses, and Operation
• To retrieve information from memory, either for one word or one byte (8-bit), addresses for
each location are needed.
• A k-bit address memory has 2k memory locations, namely 0 – 2k-1, called memory space.
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240
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Memory Location, Addresses, and Operation
• It is impractical to assign distinct addresses to individual bit locations in the memory.
• The most practical assignment is to have successive addresses refer to successive byte
locations in the memory – byte-addressable memory.
• Byte locations have addresses 0, 1, 2, … If word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…
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Big-Endian and Little-Endian Assignments
2
k
4
- 2
k
3
- 2
k
2
- 2
k
1
- 2
k
4
-
2
k
4
-
0 1 2 3
4 5 6 7
0
0
4
2
k
1
- 2
k
2
- 2
k
3
- 2
k
4
-
3 2 1 0
7 6 5 4
Byte address
Byte address
(a) Big-endian assignment (b) Little-endian assignment
4
W ord
address
•
•
•
•
•
•
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the
word
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Big-Endian and Little-Endian Assignments
• Endianness specifies the order in which the data is stored in the memory by
processor operations in a multi byte system.
• Suppose the word length is two byte then data can be stored in memory in two
different ways:
1. Higher order of data byte at the higher memory and lower order of data byte at
location just below the higher memory – Little-Endian
◦ E.g.: Intel x86 Processors
2. Lower order of data byte at the higher memory and higher order of data byte at
location just below the higher memory – Big-Endian
◦ E.g.: Motorola 68000 Series Processors
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Little-endian scheme
• Little-endian means the lower-order byte of the data is stored in memory at the
lowest address, and the higher-order byte at the highest address. (The little end
comes first.)
• For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in
the memory as shown below:
Introduction to embedded system by Shibu K V.
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Big-endian scheme
• Big-endian means the higher-order byte of the data is stored in memory at the
lowest address, and the lower-order byte at the highest address. (The big end
comes first.)
• For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in
the memory as shown below:
Introduction to embedded system by Shibu K V.
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Memory Location, Addresses, and Operation
• Address ordering of bytes
• Word alignment
• Words are said to be aligned in memory if they begin at a byte addr. that is a multiple
of the num of bytes in a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….
64
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Memory Operation
 Load (or Read)
• Transfer a copy of the contents of a specific memory location to the processor.
• The memory contents remains unchanged
• To start a load operation the processor sends the address of the desire location to the memory and
requests that its contents be read.
• The memory reads the data stored at that address and sends them to the processor.
 Store (or Write)
• The Store operation transfer a item of information from the processor to a specific memory locations,
destroying the former contents of that location.
• The processor sends the address of the desire location to the memory together with the data to be
written into that location.
65
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Memory Operation
• Load (or Read or Fetch)
Copy the content. The memory content doesn’t change.
Address – Load
Registers can be used
• Store (or Write)
Overwrite the content in memory
Address and Data – Store
Registers can be used
66
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• The first instruction load R1, x loads the register R1 with the content of memory location x.
• The second instruction load R2, y loads the register R2 with the content of memory location y.
• The instruction add R3, R1, R2 adds the content of registers R1 and R2 and stores the result in
register R3.
• The next instruction store R3,z stores the content of register R3 in memory location z.
Load- Store Architecture (content beyond syllabus)
Introduction to embedded system by Shibu K V.
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Instruction and Instruction
Sequencing
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“Must-Perform” Operations
The computer must have instruction capable of performing 4 types of operation
• Data transfers between the memory and the processor registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
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Register Transfer Notation
• Identify a location by a symbolic name standing for its hardware binary address (LOC,
R0,…)
• Contents of a location are denoted by placing square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
• Register Transfer Notation (RTN)
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Assembly Language Notation
• Represent machine instructions and programs.
• Move LOC, R1 = R1←[LOC]
• Add R1, R2, R3 = R3 ←[R1]+[R2]
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CPU Organization
• Single Accumulator
• Result usually goes to the Accumulator
• Accumulator has to be saved to memory quite often
• General Register
• Registers hold operands thus reduce memory traffic
• Stack
• Operands and result are always in the stack
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Instruction Formats
• Three-Address Instructions
• ADD R1, R2, R3 R3 ← R1 + R2
• Two-Address Instructions
• ADD R1, R2 R2 ← R1 + R2
• One-Address Instructions
• ADD A AC ← [AC] + [A]
• LOAD A AC ← [A]
• STORE A A ← [AC]
• Zero-Address Instructions
• ADD TOS ← TOS + (TOS – 1)
• RISC Instructions
• Lots of registers. Memory is restricted to Load & Store
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Three-Address
1. ADD A, B,R1 ; R1 ← M[A] + M[B]
2. ADD C, D,R2 ; R2 ← M[C] + M[D]
3. MUL R1, R2,X ; M[X] ← R1  R2
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Two-Address
1. MOV A,R1 ; R1 ← M[A]
2. ADD B,R1 ; R1 ← R1 + M[B]
3. MOV C,R2 ; R2 ← M[C]
4. ADD D,R2 ; R2 ← R2 + M[D]
5. MUL R2,R1 ; R1 ← R1  R2
6. MOV R1,X ; M[X] ← R1
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
• One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC  M[T]
7. STORE X ; M[X] ← AC
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)(A+B)
8. POP X ; M[X] ← TOS
77
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Instruction Formats
Example: Evaluate (A+B)  (C+D)
• RISC
1. LOAD A,R1 ; R1 ← M[A]
2. LOAD B,R2 ; R2 ← M[B]
3. LOAD C,R3 ; R3 ← M[C]
4. LOAD D,R4 ; R4 ← M[D]
5. ADD R1, R2,R1 ; R1 ← R1 + R2
6. ADD R3, R4,R3 ; R3 ← R3 + R4
7. MUL R1, R3,R1 ; R1 ← R1  R3
8. STORE R1,X ; M[X] ← R1
78
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Using Registers
• Registers are faster
• Shorter instructions
• The number of registers is smaller (e.g. 32 registers need 5 bits)
• Potential speedup
• Minimize the frequency with which data is moved back and forth between the memory
and processor registers.
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Instruction Execution and Straight-Line
Sequencing
R0,C
B,R0
A,R0
Move
i + 8
Begin execution here Move
i
Contents
Address
C
B
A
the program
Data for
segment
program
3-instruction
Add
i + 4
Assumptions:
- One memory operand
per instruction
- 32-bit word length
- Memory is byte
addressable
- Full memory address
can be directly specified
in a single-word instruction
80
Two-phase procedure
-Instruction fetch
-Instruction execute
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Branching
NUM n
NUM2
NUM1
R0,SUM
NUM n ,R0
NUM3,R0
NUM2,R0
NUM1,R0
Add
Add
Move
SUM
i
Move
Add
i 4 n
+
i 4 n 4
-
+
i 8
+
i 4
+
•
•
•
•
•
•
•
•
•
81
A straight-line program for adding
n numbers.
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Branching
N,R1
Move
NUM n
NUM2
NUM1
R0,SUM
R1
"Next" number to R0
Using a loop to add n numbers.
LOOP
Decrement
Move
LOOP
loop
Program
Determine address of
"Next" number and add
N
SUM
n
R0
Clear
Branch>0
•
•
•
•
•
•
Branch target
Conditional branch
82
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Condition Codes
• The processor keeps track of information about the results of various operations for use by
subsequent conditional branch instructions. This is accomplished by recording the requited
information in individual bits, often called condition code flags.
• These flags are usually grouped together in a special processor register called the condition
code register or status register.
• N (negative)
• Z (zero)
• V (overflow)
• C (carry)
• Different instructions affect different flags
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NPTEL and other video links
1) Computer basics and number system : https://nptel.ac.in/courses/106/105/106105163/
2) Floating point representation: https://www.youtube.com/watch?v=-A2hHFBUIsQ
3) Memory addressing and operations: https://nptel.ac.in/courses/106/105/106105163/
4) Instruction Execution: https://www.youtube.com/watch?v=gfFgPvEDNYU
5) 2’s Complement subtraction: youtube.com/watch?v=PxrT6GUnbX0
6) Overflow condition in 2’s complement addition :
https://www.youtube.com/watch?v=vl1LYH26RCM
7) Basic performance equation : https://www.youtube.com/watch?v=jafpmMOw194
8) Conditional Flags : https://www.youtube.com/watch?v=wwz_Kmpte-4
9) Instruction sequencing : https://www.youtube.com/watch?v=dPa4T_EZ7Gs
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Contents Beyond The Syllabus
•Multiple Bus Structure https://www.youtube.com/watch?v=TgYAj7mlRT8
•Harvard and Von Nuemmann Architecture https://www.youtube.com/watch?v=zM9no7lHzGU
•https://www.youtube.com/watch?v=wj6HoSvFszU
•Conditional Flags https://www.youtube.com/watch?v=kXNPntGpNDs
•Number system conversion https://youtu.be/rsxT4FfRBaM
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•Inside your computer : https://www.youtube.com/watch?v=AkFi90lZmXA
•Computer System Architecture: https://www.youtube.com/watch?v=So9SR3qpWsM
Innovative links
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•Six Days Online FDP on Latest Trends and Challenges in IT Industry
https://www.youtube.com/watch?v=kDL6SFu_kr0
FDP Content
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Self Assessment Questions
• Which registers are responsible for fetching the data from memory?
• Which are the important parameters in basic performance equation? How they affect
processor performance?
• What is the address space generated by 24 bit address ?
• How to store data in big endian and little endian scheme? Which scheme is used by
Intel Processors?
•When branch instruction is performed, what is the status of CPU?
•How to identify overflow condition in subtraction using 2’s complement?
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Quiz questions
1. The ______ format is usually used to store data.
a) BCD
b) Decimal
c) Hexadecimal
d) Octal
2. Which unit is responsible for converting the data received from the user into
computer understandable format?
a) Memory Unit
b) Arithmetic & Logic Unit
c) Input Unit
d) Output Unit
3. The only language which the computer understands is ______________
a) Assembly Language
b) Binary Language
c) BASIC
d) C Language
https://docs.google.com/forms/d/1DyovSzCmxytvV063m2xp2aUdcSLZKGs9Lj5HlvBYFmg/edit
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Quiz questions
4. The smallest unit of data in computer is ________________
a) Byte
b) Nibble
c) Bit
d) KB
5. One nibble is equivalent to how many bits?
a) 2
b) 4
c) 8
d) 1
6. The input machine which originated in the United States
around 1880s is a ___________
a) Mouse
b) Joystick
c) Keyboard
d) Bar Code Reader
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Quiz questions
7. VDU stands for __________
a) Virtual Display Unit
b) Visual Display Unit
c) Virtual Detection Unit
d) Visual Detection Unit
8. Components that provide internal storage to the CPU are
______
a) Registers
b) Program Counters
c) Controllers
d) Internal chips
9. Which of the following is used to hold running program
instructions?
a) Primary Storage
b) Virtual Storage
c) Internal Storage
d) Minor Devices
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Quiz questions
10. The sign magnitude representation of -1 is __________
a) 0001
b) 1110
c) 1000
d) 1001
11. What does MAR stand for?
a) Main Address Register
b) Memory Access Register
c) Main Accessible Register
d) Memory Address Register
12. The 2’s complement of 15 is ____________
a) 0000
b) 0001
c) 0010
d) 0100
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Q.
No.
MODULE- 1 MARKS CO Code
Learning
Level
1 Represent 82.125 in IEEE floating point single and double precision
format
8
C206.1
L3
2 Convert the following numbers into 5 bit signed numbers and perform
subtraction using 2’s complement method. Also predict about overflow.
1) -5 and 8 2) -28 and 15
8 C206.1
L3
3
Write the performance equation for computer. Let us assume two
computers use same instruction set architecture. Computer A has clock
cycle time of 250 ps. And CPI of 2.0 for some program and Computer
B has clock cycle time of 500 ps. And CPI of 1.2. Which computer is
faster for this program and by how much?
7 C206.1
L3
4 Explain big endian and little endian scheme. If data 00, 01, 02, 03 be
stored at memory location 1000 using big endian scheme., then show
representation for the same
7 C206.1
L3
University Paper Questions
www.vtu.ac.in
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Case Study
1) Study the different components of Computer and learn how to connect two
computers in LAN.
2) To study ALU 74181 IC.
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Thank You
95

Digital Design and Computer Organization_Module_3.pptx

  • 1.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. An Autonomous Institute Affiliated to VTU, Belagavi, Approved by AICTE, New Delhi, Recognized by UGC with 2(f) & 12(B) Accredited by NBA & NAAC DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SUBJECT CODE : MVJ20EC36 SUBJECT NAME: COMPUTER ORGANIZATION AND ARCHITECTURE LECTURE PRESENTATION MODULE – 1 FACULTY : Ms. Shruthi. N, Asst. Prof, Dept. of ECE .
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 2 Syllabus for Course • Module 1 • Basic Structure of Computers: Computer Types, Functional Units, Basic Operational Concepts, Bus Structures, Software, Performance – Processor Clock, Basic Performance Equation • Machine Instructions and Programs: Numbers, Arithmetic Operations and Characters, IEEE standard for Floating point Numbers, Memory Location and Addresses, Memory Operations, Instructions and Instruction Sequencing. • Activity: To recognize various Components of a PC. • Module 2 • Addressing Modes, Assembly Language, Basic Input and Output Operations, Stacks and Queues, Subroutines, Additional Instructions. • Activity: Write an ALP to find the sum of two numbers and verify if the sum is an even or odd number. 2
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 3 • Module 3 • Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and Disabling Interrupts, Handling Multiple Devices, Controlling Device Requests, Direct Memory Access, Buses. • Activity: Study any one input/output device and examine its various input output ports working. • Module 4 • Memory System: Basic Concepts, Semiconductor RAM Memories-Internal organization of memory chips, Static memories, Asynchronous DRAMS, Read Only Memories, Cache Memories, Mapping Functions, Replacement Algorithm, Virtual Memories, Secondary Storage-Magnetic Hard Disks. • Activity: Implement and simulate a simple memory unit which is capable of reading and writing data within a single clock cycle. 3 Syllabus for Course
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 4 Syllabus for Course • Module 5 • Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete Instruction, Multiple Bus Organization, Hardwired Control, Microprogrammed Control ,Pipelining ,Basic concepts, Role of Cache memory, Pipeline Performance • Activity: Show the possible control sequence for implementing any instruction for a single bus organisation. 4
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 5 Module 1 Structure • Basic Structure of Computers: • Computer Types, Functional Units, • Basic Operational Concepts, • Bus Structures, Software, • Performance – Processor Clock, Basic Performance Equation 5
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 6 Module 1 Structure • Machine Instructions and Programs: • Numbers, Arithmetic Operations and Characters, • IEEE standard for Floating point Numbers, • Memory Location and Addresses, Memory Operations, • Instructions and Instruction Sequencing. • Activity: To recognize various Components of a PC. 6
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 7 Reference Books • Carl Hamacher, ZvonkoVranesic, SafwatZaky: Computer Organization, 5th Edition, 2000. • David A. Patterson, John L. Hennessy: Computer Organization and Design – The Hardware / Software Interface ARM Edition, 4th Edition, Elsevier, 2009. • William Stallings: Computer Organization & Architecture, 7th Edition, PHI, 2006. • Vincent P. Heuring& Harry F. Jordan: Computer Systems Design and Architecture, 2nd Edition, Pearson Education, 2004. 7
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    Course Outcomes 8 After studyingthis course, students will be able to: •Explain the basic organization of a computer system. •Familiarization with various addressing modes and instruction. •Explain different ways of accessing an input / output device including interrupts. •Illustrate the organization of different types of semiconductor and other secondary storage memories. •Illustrate simple processor organization based on hardwired control and micro programmed control and Pipelining. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    9 An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Bridge Material • Types of computer (on the basis of functionality) •Compiler •Multiprocessor and multicontroller •Decimal to Binary conversion •ASCII Chart •Status bits
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    10 Basic Structure ofComputers An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    11 What is computer Acontemporary computer is a fast electronics calculating machine that accepts digitized information, processes it according to the list of internally stored instructions and produces the resulting output information. What is program? The list of the instructions is called as computer program and internal storage is called as computer memory. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. https://www.javatpoint.com/what-is-computer
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    12 Types of Computer Onthe basis of functionality. On the basis of Size, Speed and Cost. According to functionality computer can be divided in to three types: 1) Analog 2) Digital 3) Hybrid An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    13 Analog Computer •“An analog(spelled analogue in British English) computer is a form of computer that uses the continuously- changeable aspects of physical fact such as electrical, mechanical, or hydraulic quantities to model the problem being solved.” •Analog means continuity of associated quantity just like an analog clock measures time by means of the distance travelled by the hand of the clock around a dial. •Example: Thermometer, Analog clock, An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. https://images.app.goo.gl/eVsgBBheqGPi6a7Q7
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    14 Digital Computer • “Acomputer that performs calculations and logical operations with quantities represented as digits, usually in the binary number system of “0” and “1”. •“Computer capable of solving problems by processing information expressed in discrete form. By manipulating combinations of binary digits (“0”, “1”), it can perform mathematical calculations, organize and analyze data, control industrial and other processes, and simulate dynamic systems such as global weather patterns. ” •EXAMPLES: IBM PC, Digital watches etc An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    15 Hybrid Computer •A hybridcomputer is a combination of computers that are capable of inputting and outputting in both digital and analog signals. •Traditionally, the analog components of the computer handle complex mathematical computations. The digital components take care of logical and numerical operations in addition to serving as the controller for the system. •Hybrid computers for example are used for scientific calculations, in defence and radar systems. •Example: Notebook, Laptop etc. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    16 •A desktop computeris a personal computer designed for regular use at a single location on or near a desk or table due to its size and power requirements. •The most common configuration has a case that houses the power supply, motherboard (a printed circuit board with a microprocessor as the central processing unit (CPU), memory, bus, and other electronic components), disk storage (usually one or more hard disk drives, solid state drives, optical disc drives, and in early models a floppy disk drive); a keyboard and mouse for input; and a computer monitor, speakers, and, often, a printer for output. • The case may be oriented horizontally or vertically and placed either underneath, beside, or on top of a desk. Types of digital computer An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    17 •A laptop (alsolaptop computer), often called a notebook, is a small, portable personal computer (PC) with a "clamshell" form factor, typically having a thin LCD or LED computer screen mounted on the inside of the upper lid of the clamshell and an alphanumeric keyboard on the inside of the lower lid. •The clamshell is opened up to use the computer. Laptops are folded shut for transportation, and thus are suitable for mobile use. • Its name comes from lap, as it was deemed to be placed on a person's lap when being used. Although originally there was a distinction between laptops and notebooks (the former being bigger and heavier than the latter), as of 2014, there is often no longer any difference. Types of digital computer An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    18 •A workstation isa special computer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating systems. •The term workstation has also been used loosely to refer to everything from a mainframe computer terminal to a PC connected to a network, but the most common form refers to the class of hardware offered by several current companies such as Sun Microsystems, Silicon Graphics, Apollo Computer, DEC, HP, NeXT and IBM which opened the door for the 3D graphics animation revolution of the late 1990s. Types of digital computer An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    19 Computer (on the basisof size, speed and performance) Micro Computer Super Computer Mini Computer Main-Frame Computer Types of computers An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Carl Hamacher, ZvonkoVranesic, SafwatZaky: Computer Organization, 5th Edition, 2000.
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    20 Micro Computers •It isdifficult to overstate the impact of the micro computer on the computer industry. In 1975, the micro computer did not exist. In 1995, sales exceeded $116 billion. Microcomputers are the fastest growing segment of the computer industry. •The micro computer segment of the industry is complex; there are different types of microcomputer platforms with varying capabilities. The most common type of microcomputer is a Desktop Computer, which is a non portable Personal Computer that fits on top of a desk. (will describe below). •Microcomputers are the smallest and cheapest. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    21 Mini Computer •The minicomputers are small digital computers, which normally process and store less data than mainframe but more than a microcomputer. Minicomputer systems provide faster operating speeds and larger storage capacities than microcomputer systems. They are sometimes called mid-range computers, and are designed to meet the computing needs for several people simultaneously in a small to medium size business environment. They are used in industries, research organizations, colleges and universities. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    22 Main Frame Computer •Itis a multi-user computer system which is capable of supporting hundreds of users simultaneously. Software technology is different from minicomputer. •Mainframe is very large in size and is an expensive computer capable of supporting hundreds or even thousands of users simultaneously. Mainframe executes many programs concurrently and supports many simultaneous execution of programs. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. https://en.wikipedia.org/wiki/Mainframe_computer
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    23 Servers •Beyond workstations, arange of large and very powerful computer system exists called servers. Servers contain sizable database and storage units and are capable of handling large volumes of requests to access the data. •In many cases servers are widely accessible to the education, business and personal user communities. The requests and responses are usually transported over Internet communication facilities. The internet and its associated servers have become a dominant world wide source of all types of information An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    24 Super Computer •It isan extremely fast computer which can execute hundreds of millions of instructions per second. •Supercomputers are one of the fastest computers currently available. • Supercomputers are very expensive and are employed for specialized applications that require immense amount of mathematical calculations. For example, weather forecasting, scientific simulations, (animated) graphics, fluid dynamic calculations, nuclear energy research, electronic design, and analysis of geological data. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC.
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 25 Functional Units I/O Processor Output Memory Input and Arithmetic logic Control 25 https://images.app.goo.gl/mfMJcNqCEcVuARcS9
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 26 Information Handled by a Computer • Instructions/machine instructions • Govern the transfer of information within a computer as well as between the computer and its I/O devices • Specify the arithmetic and logic operations to be performed • Program • Data • Used as operands by the instructions • Encoded in binary code – 0 and 1 • Alphanumeric Characters- ASCII and EBCDIC 26
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 27 Input Unit • In computing, an input device is a piece of equipment used to provide data and control signals to an information processing system such as a computer or information appliance. Examples of input devices include keyboards, mouse, scanners, digital cameras, joysticks, and microphones. 27
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 28 Memory Unit • Store programs and data • Two classes of storage Primary storage Fast Programs must be stored in memory while they are being executed Large number of semiconductor storage cells Processed in words Address, RAM and memory access time, Memory hierarchy – cache, main memory Secondary storage – larger and cheaper 28
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 29 Arithmetic and Logic Unit (ALU) • Most computer operations are executed in ALU of the processor. • Load the operands into memory – bring them to the processor – perform operation in ALU – store the result back to memory or retain in the processor. • Registers 29
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 30 Output Unit • An output device is any piece of computer hardware equipment which converts information into human- readable form. It can be text, graphics, audio, and video. Some of the output devices are Visual Display Units (VDU) i.e. a Monitor, Printer, Graphic Output devices, Speakers 30
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 31 Control Unit • All computer operations are controlled by the control unit. • The timing signals that govern the I/O transfers are also generated by the control unit. • Control unit is usually distributed throughout the machine instead of standing alone. • Operations of a computer: Accept information in the form of programs and data through an input unit and store it in the memory Fetch the information stored in the memory, under program control, into an ALU, where the information is processed Output the processed information through an output unit Control all activities inside the machine through a control unit 31
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 32 32 Basic Operational Concepts
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 33 Review • Activity in a computer is governed by instructions. • To perform a task, an appropriate program consisting of a list of instructions is stored in the memory. • Individual instructions are brought from the memory into the processor, which executes the specified operations. • Data to be used as operands are also stored in the memory. 33
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 34 A Typical Instruction • Add LOCA, R0 • Add the operand at memory location LOCA to the operand in a register R0 in the processor. • Place the sum into register R0. • The original contents of LOCA are preserved. • The original contents of R0 is overwritten. • Instruction is fetched from the memory into the processor – the operand at LOCA is fetched and added to the contents of R0 – the resulting sum is stored in register R0. 34
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 35 Separate Memory Access and ALU Operation • Load LOCA, R1 • Add R1, R0 • Whose contents will be overwritten? 35
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 36 Connection Between the Processor and the Memory • Programs reside in the memory through input devices • PC is set to point to the first instruction • The contents of PC are transferred to MAR • A Read signal is sent to the memory • The first instruction is read out and loaded into MDR • The contents of MDR are transferred to IR • Decode and execute the instruction 36
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 37 Registers • Instruction register (IR) • Program counter (PC) • General-purpose register (R0 – Rn-1) • Memory address register (MAR) • Memory data register (MDR) 37
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 38 Typical Operating Steps (Cont’) • Get operands for ALU General-purpose register Memory (address to MAR – Read – MDR to ALU) • Perform operation in ALU • Store the result back To general-purpose register To memory (address to MAR, result to MDR – Write) • During the execution, PC is incremented to the next instruction • Interrupts 38
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 39 Example • List the steps needed to execute the machine instruction Add LOCA, R0 Solution • Transfer the contents of register PC to register MAR • Issue a Read command to memory, and then wait until it has transferred the requested word into register MDR • Transfer the instruction from MDR into IR and decode it • Transfer the address LOCA from IR to MAR • Issue a Read command and wait until MDR is loaded • Transfer contents of MDR to the ALU • Transfer contents of R0 to the ALU • Perform addition of the two operands in the ALU and transfer result into R0 • Transfer contents of PC to ALU • Add 1 to operand in ALU and transfer incremented address to PC 39
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 40 Example 2 • Repeat the above problem for Add R1, R2, R3 Solution • Transfer the contents of register PC to register MAR • Issue a Read command to memory, and then wait until it has transferred the requested word into register MDR • Transfer the instruction from MDR into IR and decode it • Transfer contents of R1 and R2 to the ALU • Perform addition of two operands in the ALU and transfer answer into R3 • Transfer contents of PC to ALU • Add 1 to operand in ALU and transfer incremented address to PC 40
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 41 Interrupt • Normal execution of programs may be preempted if some device requires urgent servicing. • The normal execution of the current program must be interrupted – the device raises an interrupt signal. • Interrupt-service routine • Current system information backup and restore (PC, general-purpose registers, control information, specific information) 41
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 42 Bus Structures • There are many ways to connect different parts inside a computer together. • A group of lines that serves as a connecting path for several devices is called a bus. • Address/data/control • Bus can be used for only one transfer at a time • The main virtue of single bus structure is its low cost and its flexibility for attaching peripheral devices 42
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 43 Bus Structure • Single-bus 43 • The devices connected to a bus vary widely in their speed of operation. To synchronize their operational speed, the approach is to include buffer registers with the devices to hold the information during transfers • Buffer registers prevent a high-speed processor from being locked to a slow I/O device during a sequence of data transfers.
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 44 Speed Issue • Different devices have different transfer/operate speed. • If the speed of bus is bounded by the slowest device connected to it, the efficiency will be very low. • How to solve this? • A common approach – use buffers. 44
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 45 Performance • The most important measure of a computer is how quickly it can execute programs. • The speed with which a computer executes programs is affected by the design of its hardware and its machine language instruction. • Because programs are usually written in high level language, performance is also affected by the compiler that translates programs into machine language. • For best performance , it is necessary to design the compiler, the machine instruction set, and the hardware in a coordinated way. 45
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 46 Performance • Processor time to execute a program depends on the hardware involved in the execution of individual machine instructions. Main memory Processor Bus Cache memory The processor cache. 46
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 47 Performance • The processor and a relatively small cache memory can be fabricated on a single integrated circuit chip. • The internal speed of performing the basic steps of instruction processing on such chips is very high and is considerably faster than the speed at which instructions and data can be fetched from the main memory. 47
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 48 Processor Clock • Processor circuits are controlled by a timing signal called a Clock • The clock defines regular time intervals called clock cycles • To execute a machine instruction, the processor divides the action to be performed into a sequence of basic steps such that each step can be completed in one clock cycle • Let P=length of one clock cycle R=clock rate. Relation between P and R is given by R=1/P which is measured in cycles per second. • Cycles per second is also called hertz(Hz) 48
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 49 Basic Performance Equation • T – processor time required to execute a program that has been prepared in high-level language • N – number of actual machine language instructions needed to complete the execution (note: loop) • S – average number of basic steps needed to execute one machine instruction. Each step completes in one clock cycle • R – clock rate • Note: these are not independent to each other R S N T   How to improve T? 49
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 50 Example • Computer A has clock cycle time of 250 ps. and CPI of 2.0 for some program and Computer B has clock cycle time of 500 ps. and CPI of 1.2. Which computer is faster for this program and by how much? • Solution: • Assume each computer executes Ninstructions, so • CPU timeA = N × 2.0 × 250 = 500 × N ps • CPU timeB = N × 1.2 × 500 = 600 × N ps • A is faster by the ratio of execution times: = execution timeB /execution timeA = 600 × N /500 × N = 1.2 50
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 51 Clock Rate • Increase clock rate Improve the integrated-circuit (IC) technology to make the circuits faster Reduce the amount of processing done in one basic step (however, this may increase the number of basic steps needed) • Increases in R that are entirely caused by improvements in IC technology affect all aspects of the processor’s operation equally except the time to access the main memory. 51
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 52 Performance Measurement 52
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Machine Instructions and Programs 53
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Locations, Addresses, and Operations 54
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    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Location, Addresses, and Operation • Memory consists of many millions of storage cells, each of which can store 1 bit. • Data is usually accessed in n-bit groups. n is called word length. • The memory of computer can be schematically represented as a collection of words. second word first word n bits last word i th word • • • • • • 55
  • 56.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Location, Addresses, and Operation • 32-bit word length example (b) Four characters character character character character (a) A signed integer Sign bit: for positive numbers for negative numbers ASCII ASCII ASCII ASCII 32 bits 8 bits 8 bits 8 bits 8 bits b 31 b 30 b 1 b 0 b 31 0 = b 31 1 = • • • 56 If the word length of a computer is 32 bit a single word can store a 32 bit 2’s complement number or four ASCII characters each occupying 8 bits
  • 57.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 57 ASCII Chart https://images.app.goo.gl/8KBmaerjFC4DVmym6
  • 58.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Location, Addresses, and Operation • To retrieve information from memory, either for one word or one byte (8-bit), addresses for each location are needed. • A k-bit address memory has 2k memory locations, namely 0 – 2k-1, called memory space. • 24-bit memory: 224 = 16,777,216 = 16M (1M=220) • 32-bit memory: 232 = 4G (1G=230) • 1K(kilo)=210 • 1T(tera)=240 58
  • 59.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Location, Addresses, and Operation • It is impractical to assign distinct addresses to individual bit locations in the memory. • The most practical assignment is to have successive addresses refer to successive byte locations in the memory – byte-addressable memory. • Byte locations have addresses 0, 1, 2, … If word length is 32 bits, they successive words are located at addresses 0, 4, 8,… 59
  • 60.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Big-Endian and Little-Endian Assignments 2 k 4 - 2 k 3 - 2 k 2 - 2 k 1 - 2 k 4 - 2 k 4 - 0 1 2 3 4 5 6 7 0 0 4 2 k 1 - 2 k 2 - 2 k 3 - 2 k 4 - 3 2 1 0 7 6 5 4 Byte address Byte address (a) Big-endian assignment (b) Little-endian assignment 4 W ord address • • • • • • Big-Endian: lower byte addresses are used for the most significant bytes of the word Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word 60
  • 61.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 61 Big-Endian and Little-Endian Assignments • Endianness specifies the order in which the data is stored in the memory by processor operations in a multi byte system. • Suppose the word length is two byte then data can be stored in memory in two different ways: 1. Higher order of data byte at the higher memory and lower order of data byte at location just below the higher memory – Little-Endian ◦ E.g.: Intel x86 Processors 2. Lower order of data byte at the higher memory and higher order of data byte at location just below the higher memory – Big-Endian ◦ E.g.: Motorola 68000 Series Processors
  • 62.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 62 Little-endian scheme • Little-endian means the lower-order byte of the data is stored in memory at the lowest address, and the higher-order byte at the highest address. (The little end comes first.) • For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as shown below: Introduction to embedded system by Shibu K V.
  • 63.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 63 Big-endian scheme • Big-endian means the higher-order byte of the data is stored in memory at the lowest address, and the lower-order byte at the highest address. (The big end comes first.) • For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as shown below: Introduction to embedded system by Shibu K V.
  • 64.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Location, Addresses, and Operation • Address ordering of bytes • Word alignment • Words are said to be aligned in memory if they begin at a byte addr. that is a multiple of the num of bytes in a word. • 16-bit word: word addresses: 0, 2, 4,…. • 32-bit word: word addresses: 0, 4, 8,…. • 64-bit word: word addresses: 0, 8,16,…. 64
  • 65.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Operation  Load (or Read) • Transfer a copy of the contents of a specific memory location to the processor. • The memory contents remains unchanged • To start a load operation the processor sends the address of the desire location to the memory and requests that its contents be read. • The memory reads the data stored at that address and sends them to the processor.  Store (or Write) • The Store operation transfer a item of information from the processor to a specific memory locations, destroying the former contents of that location. • The processor sends the address of the desire location to the memory together with the data to be written into that location. 65
  • 66.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Memory Operation • Load (or Read or Fetch) Copy the content. The memory content doesn’t change. Address – Load Registers can be used • Store (or Write) Overwrite the content in memory Address and Data – Store Registers can be used 66
  • 67.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 67 • The first instruction load R1, x loads the register R1 with the content of memory location x. • The second instruction load R2, y loads the register R2 with the content of memory location y. • The instruction add R3, R1, R2 adds the content of registers R1 and R2 and stores the result in register R3. • The next instruction store R3,z stores the content of register R3 in memory location z. Load- Store Architecture (content beyond syllabus) Introduction to embedded system by Shibu K V.
  • 68.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction and Instruction Sequencing 68
  • 69.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. “Must-Perform” Operations The computer must have instruction capable of performing 4 types of operation • Data transfers between the memory and the processor registers • Arithmetic and logic operations on data • Program sequencing and control • I/O transfers 69
  • 70.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Register Transfer Notation • Identify a location by a symbolic name standing for its hardware binary address (LOC, R0,…) • Contents of a location are denoted by placing square brackets around the name of the location (R1←[LOC], R3 ←[R1]+[R2]) • Register Transfer Notation (RTN) 70
  • 71.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Assembly Language Notation • Represent machine instructions and programs. • Move LOC, R1 = R1←[LOC] • Add R1, R2, R3 = R3 ←[R1]+[R2] 71
  • 72.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. CPU Organization • Single Accumulator • Result usually goes to the Accumulator • Accumulator has to be saved to memory quite often • General Register • Registers hold operands thus reduce memory traffic • Stack • Operands and result are always in the stack 72
  • 73.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Formats • Three-Address Instructions • ADD R1, R2, R3 R3 ← R1 + R2 • Two-Address Instructions • ADD R1, R2 R2 ← R1 + R2 • One-Address Instructions • ADD A AC ← [AC] + [A] • LOAD A AC ← [A] • STORE A A ← [AC] • Zero-Address Instructions • ADD TOS ← TOS + (TOS – 1) • RISC Instructions • Lots of registers. Memory is restricted to Load & Store 73
  • 74.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Formats Example: Evaluate (A+B)  (C+D) • Three-Address 1. ADD A, B,R1 ; R1 ← M[A] + M[B] 2. ADD C, D,R2 ; R2 ← M[C] + M[D] 3. MUL R1, R2,X ; M[X] ← R1  R2 74
  • 75.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Formats Example: Evaluate (A+B)  (C+D) • Two-Address 1. MOV A,R1 ; R1 ← M[A] 2. ADD B,R1 ; R1 ← R1 + M[B] 3. MOV C,R2 ; R2 ← M[C] 4. ADD D,R2 ; R2 ← R2 + M[D] 5. MUL R2,R1 ; R1 ← R1  R2 6. MOV R1,X ; M[X] ← R1 75
  • 76.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Formats Example: Evaluate (A+B)  (C+D) • One-Address 1. LOAD A ; AC ← M[A] 2. ADD B ; AC ← AC + M[B] 3. STORE T ; M[T] ← AC 4. LOAD C ; AC ← M[C] 5. ADD D ; AC ← AC + M[D] 6. MUL T ; AC ← AC  M[T] 7. STORE X ; M[X] ← AC 76
  • 77.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Formats Example: Evaluate (A+B)  (C+D) • Zero-Address 1. PUSH A ; TOS ← A 2. PUSH B ; TOS← B 3. ADD ; TOS ← (A + B) 4. PUSH C ; TOS ← C 5. PUSH D ; TOS ← D 6. ADD ; TOS ← (C + D) 7. MUL ; TOS ← (C+D)(A+B) 8. POP X ; M[X] ← TOS 77
  • 78.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Formats Example: Evaluate (A+B)  (C+D) • RISC 1. LOAD A,R1 ; R1 ← M[A] 2. LOAD B,R2 ; R2 ← M[B] 3. LOAD C,R3 ; R3 ← M[C] 4. LOAD D,R4 ; R4 ← M[D] 5. ADD R1, R2,R1 ; R1 ← R1 + R2 6. ADD R3, R4,R3 ; R3 ← R3 + R4 7. MUL R1, R3,R1 ; R1 ← R1  R3 8. STORE R1,X ; M[X] ← R1 78
  • 79.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Using Registers • Registers are faster • Shorter instructions • The number of registers is smaller (e.g. 32 registers need 5 bits) • Potential speedup • Minimize the frequency with which data is moved back and forth between the memory and processor registers. 79
  • 80.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Instruction Execution and Straight-Line Sequencing R0,C B,R0 A,R0 Move i + 8 Begin execution here Move i Contents Address C B A the program Data for segment program 3-instruction Add i + 4 Assumptions: - One memory operand per instruction - 32-bit word length - Memory is byte addressable - Full memory address can be directly specified in a single-word instruction 80 Two-phase procedure -Instruction fetch -Instruction execute
  • 81.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Branching NUM n NUM2 NUM1 R0,SUM NUM n ,R0 NUM3,R0 NUM2,R0 NUM1,R0 Add Add Move SUM i Move Add i 4 n + i 4 n 4 - + i 8 + i 4 + • • • • • • • • • 81 A straight-line program for adding n numbers.
  • 82.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Branching N,R1 Move NUM n NUM2 NUM1 R0,SUM R1 "Next" number to R0 Using a loop to add n numbers. LOOP Decrement Move LOOP loop Program Determine address of "Next" number and add N SUM n R0 Clear Branch>0 • • • • • • Branch target Conditional branch 82
  • 83.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. Condition Codes • The processor keeps track of information about the results of various operations for use by subsequent conditional branch instructions. This is accomplished by recording the requited information in individual bits, often called condition code flags. • These flags are usually grouped together in a special processor register called the condition code register or status register. • N (negative) • Z (zero) • V (overflow) • C (carry) • Different instructions affect different flags 83
  • 84.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 84 NPTEL and other video links 1) Computer basics and number system : https://nptel.ac.in/courses/106/105/106105163/ 2) Floating point representation: https://www.youtube.com/watch?v=-A2hHFBUIsQ 3) Memory addressing and operations: https://nptel.ac.in/courses/106/105/106105163/ 4) Instruction Execution: https://www.youtube.com/watch?v=gfFgPvEDNYU 5) 2’s Complement subtraction: youtube.com/watch?v=PxrT6GUnbX0 6) Overflow condition in 2’s complement addition : https://www.youtube.com/watch?v=vl1LYH26RCM 7) Basic performance equation : https://www.youtube.com/watch?v=jafpmMOw194 8) Conditional Flags : https://www.youtube.com/watch?v=wwz_Kmpte-4 9) Instruction sequencing : https://www.youtube.com/watch?v=dPa4T_EZ7Gs
  • 85.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 85 Contents Beyond The Syllabus •Multiple Bus Structure https://www.youtube.com/watch?v=TgYAj7mlRT8 •Harvard and Von Nuemmann Architecture https://www.youtube.com/watch?v=zM9no7lHzGU •https://www.youtube.com/watch?v=wj6HoSvFszU •Conditional Flags https://www.youtube.com/watch?v=kXNPntGpNDs •Number system conversion https://youtu.be/rsxT4FfRBaM
  • 86.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 86 •Inside your computer : https://www.youtube.com/watch?v=AkFi90lZmXA •Computer System Architecture: https://www.youtube.com/watch?v=So9SR3qpWsM Innovative links
  • 87.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 87 •Six Days Online FDP on Latest Trends and Challenges in IT Industry https://www.youtube.com/watch?v=kDL6SFu_kr0 FDP Content
  • 88.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 88 Self Assessment Questions • Which registers are responsible for fetching the data from memory? • Which are the important parameters in basic performance equation? How they affect processor performance? • What is the address space generated by 24 bit address ? • How to store data in big endian and little endian scheme? Which scheme is used by Intel Processors? •When branch instruction is performed, what is the status of CPU? •How to identify overflow condition in subtraction using 2’s complement?
  • 89.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 89 Quiz questions 1. The ______ format is usually used to store data. a) BCD b) Decimal c) Hexadecimal d) Octal 2. Which unit is responsible for converting the data received from the user into computer understandable format? a) Memory Unit b) Arithmetic & Logic Unit c) Input Unit d) Output Unit 3. The only language which the computer understands is ______________ a) Assembly Language b) Binary Language c) BASIC d) C Language https://docs.google.com/forms/d/1DyovSzCmxytvV063m2xp2aUdcSLZKGs9Lj5HlvBYFmg/edit
  • 90.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 90 Quiz questions 4. The smallest unit of data in computer is ________________ a) Byte b) Nibble c) Bit d) KB 5. One nibble is equivalent to how many bits? a) 2 b) 4 c) 8 d) 1 6. The input machine which originated in the United States around 1880s is a ___________ a) Mouse b) Joystick c) Keyboard d) Bar Code Reader
  • 91.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 91 Quiz questions 7. VDU stands for __________ a) Virtual Display Unit b) Visual Display Unit c) Virtual Detection Unit d) Visual Detection Unit 8. Components that provide internal storage to the CPU are ______ a) Registers b) Program Counters c) Controllers d) Internal chips 9. Which of the following is used to hold running program instructions? a) Primary Storage b) Virtual Storage c) Internal Storage d) Minor Devices
  • 92.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 92 Quiz questions 10. The sign magnitude representation of -1 is __________ a) 0001 b) 1110 c) 1000 d) 1001 11. What does MAR stand for? a) Main Address Register b) Memory Access Register c) Main Accessible Register d) Memory Address Register 12. The 2’s complement of 15 is ____________ a) 0000 b) 0001 c) 0010 d) 0100
  • 93.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 93 Q. No. MODULE- 1 MARKS CO Code Learning Level 1 Represent 82.125 in IEEE floating point single and double precision format 8 C206.1 L3 2 Convert the following numbers into 5 bit signed numbers and perform subtraction using 2’s complement method. Also predict about overflow. 1) -5 and 8 2) -28 and 15 8 C206.1 L3 3 Write the performance equation for computer. Let us assume two computers use same instruction set architecture. Computer A has clock cycle time of 250 ps. And CPI of 2.0 for some program and Computer B has clock cycle time of 500 ps. And CPI of 1.2. Which computer is faster for this program and by how much? 7 C206.1 L3 4 Explain big endian and little endian scheme. If data 00, 01, 02, 03 be stored at memory location 1000 using big endian scheme., then show representation for the same 7 C206.1 L3 University Paper Questions www.vtu.ac.in
  • 94.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 94 Case Study 1) Study the different components of Computer and learn how to connect two computers in LAN. 2) To study ALU 74181 IC.
  • 95.
    An Autonomous Institution,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi. Recognized by UGC with 2(f) & 12(B) status. Accredited by NBA and NAAC. 95 Thank You 95

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