1. Deepa R is seeking a position as a Technical Support Engineer where she can use her analytical skills to contribute to an organization's growth. 2. She has an MTech in VLSI and Embedded Systems from CMR Institute of Technology and a BE in ECE from HKBKCE. She has experience as a Technical Support Engineer at MPHASIS. 3. Her technical skills include programming in C/C++, VHDL, Verilog, System Verilog, Ethernet MAC, AXI, AHB, UVM, TCL, and experience with tools like Xilinx ISE, Modelsim, Questasim, and Cadence Virtuoso. She is interested in verification

1. DEEPA R
# 62 A Narayanapura Dooravaninagar
Post Bangalore 560016.
Mobile: +91-9513069252
Email-id: deepar2708@gmail.com.
CARRER OBJECTIVE
To work with a leading company and to use my analytical thinking to the best of my ability
combined with perseverance, so as to contribute to an organization’s growth and goal.
and enhance my skills and experience towards professional growth.
EDUCATION SUMMARY
COURSE BRANCH UNIVERSITY/
COLLEGE/SCHOOL
PERCENTAGE
(%)
YEAR
OF
PASSING
MTECH
VLSI &
EMBEDDED
SYSTEMS
CMR INSTITUTE OF
TECHNOLOGY ,
Bangalore-37
1st
Sem 70.02%
2017
2nd
Sem 70.01%
B.E E&CE HKBKCE,Bangalore-45 65.02% 2013
2ND PUC PCMB INPUC ,Bangalore-38 59.03% 2009
1ST PUC PCMB INPUC ,Bangalore-38 58.55% 2008
SSLC STATE
SYLLABUS
SYES, Bangalore-16 70.72% 2007
PROFESSIONAL EXPERIENCE
In MPHASIS as an Technical Support Engineer for the Charles Schwab Process. (From
15TH
JUNE 2015 to 23rd
MARCH 2016).
TECHNICAL SKILLS
 Programming Language: Basics of C/C++.
 Hardware Description Language: VHDL, Verilog, System Verilog.
 Protocols: Ethernet mac, AXI, AHB.UART
 Methodology: UVM
 Scripting: TCL
 Front End Tools: Xilinx ISE 12.5, Modelsim, Questasim 10.4c, Synopsys VCS.
 Back End tool: Cadence virtuoso
 Operating Systems: Linux and windows 7.
AREA OF INTEREST
 Verification Domain ( In front and back end VLSI).
 Physical design,

2. ACADEMIC PROJECTS
Project Title Design and Functional verification of the Ethernet mac protocol.
Description The functional verification process of an Ethernet IP core, with emphasis on
the Ethernet MAC. The Ethernet IP has been adopted from OpenCores The
IP interfaces to an Ethernet Media Access Control (MAC) compatible
Physical layer interface (PHY) on one side and on the other it interfaces to
the host system through a Wishbone bus (WB). The IP has a MAC control
module, host interface and Media Independent Interface (MII). The design
and verification environment are built using Verilog HDL, an industry
standard Hardware Description Language (HDL).
Tools used QUESTASIM 10.2
Duration 6months - October 2015 to march 2016
Project Title Advanced DMA ADAPTIVE ARBITRATION Logic verification.
Description Adaptive signal value is used as an additional input to improve the
probability of the bus grant. For the starvation problems solutions by using
the arbitration technique in circular fashion is solved. which is adaptive to
any scenarios in arbitration technique. The proposed Adaptive arbiter
scheme for the DMA provides access. Based on the priority-level
notifications and the desired transfer length from the masters to ensure that
the arbitration leads to the maximum performance.
Tools used QUESTASIM 10.4c, Synopsys VCS
Language System Verilog
Duration Current project
PERSONAL PROFILE
 Name : DEEPA R
 Date of Birth : 27-AUG-1991
 Nationality : Indian
 PASSPORT NO : M3220345
 Father’s Name : RAJENDRA M
 Mother’s Name : KUMARI P
 Father’s Occupation: In SBI as Senior Head Messenger
 Languages Known
DECLARATION
I declare that the details furnished in this resume are true to best of my knowledge
Place : Bangalore -16
Date : 06/10/2016 [DEEPA.R]
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