This document discusses models for predicting the future of multi-core processors and whether they can continue to provide performance scaling according to Moore's Law. It presents the Device Scaling Model (DevM) to predict characteristics of future process nodes, the Single Core Scaling Model (CorM) to model area/performance and power/performance, and the Multi-Core Scaling Models (CmpM) including an upper-bound Amdahl's Law model (CmpMU) and a more realistic model (CmpMR). Combining these models shows that a 32x performance improvement from 2008 to 2024 is not possible due to issues like increasing "dark silicon" power inefficiencies at future nodes. The most optimistic ITRS projection

1. Dark silicon and end of multi-core
scaling
By
Chinthaka Henadeera
Seminar of Dependable systems -SS 2012

2. Presentation outline
1. Introduction
2. Motivation
3. Scaling models
3.1 Device scaling model
3.2 Single core scaling model
3.3 Multi-core scaling model
4. Model combinations
5. Evaluation of model combinations
6. Conclusions
7. References

3. Introduction
● Transistors of chips are doubled every 18
months according to the Moore's law.
● Moore's law is based on Dennard's scaling.
● Failure of Dennard's scaling has motivated
chip designers towards multi-core chips in
order to exploit the Moore's law continuously.

4. Motivation
● Hot question
“Can we gain 32 times performance from
multi-core processors in 2024 with respect to
2008 ?”

5. Scaling models
● To model the behaviour of future multicore
processors , 3 scaling models are created
and are combined.
1) Device scaling model (DevM)
2) Single core scaling model (CorM)
3) Multi-core scaling model (CmpM)

6. Overview
Figure. 1 Overview of models and methodology [1]

7. Device scaling model (DevM)
● To determine area, frequency and power of
future tech nodes.
● Uses ITRS projections and conservative
device scaling projections.

8. Device scaling model cont.
Table 1 Scaling factors for ITRS and Conservative projections

9. Single core scaling model (CorM)
● Pareto-optimal frontiers for area/performance
and power/performance are created using
over 150 processors.

10. Single core scaling model (CorM)
contd.
Figure 2(a) Power/performance frontier
at 45 nm[1]
Figure 2(b) Area/performance frontier
At 45 nm [1]

11. Multi-core scaling model (CmpM)
● There are 2 Multi-core scaling models
1) Amdahl’s Law Upper-bound model (CmpMU
)
2) Realistic model (CmpMR
)

12. Amdahl’s Law Upper-bound model
(CmpMU
)
● Amdahl's law is extended in such a way that
can describe symmetric, asymmetric,
dynamic and composed multi-core
topologies.
● CmpMU
model provides a strict upper bound
of parallel performance.

13. Amdahl’s Law Upper-bound model
contd.
Symmetric Asymmetric Dynamic Composed
CPU
multicore
Serial 1 ST Core 1 Large ST Core 1 Large ST
Core
1 Large ST
Core
Parallel N ST Core 1 Large ST Core +
N small ST Cores
N small ST
Cores
N small ST
Cores
GPU
multicore
Serial 1 MT Core
(1 Thread)
1 Large ST Core
(1 Thread)
1 Large ST
Core (1
Thread)
1 Large ST
Core(1 Thread)
Parallel N MT Core
(Multiple
threads)
1 Large ST Core
(1 thread) +
N small MT
cores(Multiple
threads)
N Small MT
Cores
(Multiple
threads)
N Small MT
Cores
(Multiple
threads)
Table 2 . CPU and GPU Topologies
ST Core: Single-tread core MT Core: Many-thread core

14. Realistic model (CmpMR
)
● Micro-architectural features, application
behaviours, physical constraints, multi-core
topologies are considered for this model.

15. Realistic model (CmpMR
) contd.
Figure 3 Equations used for CmpMR

16. Realistic model (CmpMR
) contd.
● Speed up of realistic model is calculated
using,
Figure 4

17. Realistic model (CmpMR
) contd.
● Speed up of realistic model is calculated
using,
Figure 4

18. Model combinations
● DevM x CorM
● DevM x CorM x CmpM

19. Evaluation of model combinations
DevM x CorM
Figure 5. DevM x CorM

20. Evaluation of model combinations
DevM x CorM x CorMu
Figure 6 DevM x CorM x CorMu

21. Results of combining models
DevM x CorM x CmpMR
Figure 7 DevM x CorM x CmpMR
under Symmetric topology and ITRS scaling

22. Results of combining models contd.
Table 3.

23. Conclusions
● Dark Silicon percentage increases with
scaling down of the tech node.
● ITRS projection is quite optimistic and it
shows
● 7.9x of speed up in 2024 with respect to
2008
● 32x of speed up is impossible.

24. References
[1] Hadi Esmaeilzadeh, Emily Blem, Renée St. Amant,
Karthikeyan Sankaralingam, Doug Burger. Dark Silicon and the
End of Multicore Scaling 2010

25. Questions
?

26. Thank you