This master's thesis presents a consistent modeling technique for creating accurate transaction level models. It describes refining an existing C model of the SPINNI system into a transaction level model by structuring it based on the original VHDL design. Timing information is integrated by adding time-based and event-based delays calibrated to the VHDL model. Functional regression is automated to validate the transaction level models against the C and VHDL versions. Simulation time and CPU time comparisons demonstrate the transaction level models achieve an order of magnitude speedup over VHDL while maintaining timing accuracy.

1. Consistent Modeling Technique for Accurate
Transaction Level Models
(Master Thesis)
Hui Chen
Professor : Prof. Dr.-Ing. Ulf Schlichtmann
Advisors Prof. Dr Ing
Ad isors : Prof Dr.-Ing. Wolfgang Ecker
Ecker,
Dipl.-Ing. Michael Velten
April 22, 2008
COM BTS MT SD
Institute for EDA

2. Motivation
Complex SoC design, but limited time to market
Start software development and validation before RTL is available
Raise design to higher abstraction levels: Transaction Level (TL)
Early availability of TL Models due to high degree of abstraction
Existent RTL legacy in new SoCs => Need to be modeled at TL too
Not only functional but also timing accurate TL models:
To ensure the order of interrupts, to analyze the system performance, …
Obtaining TL models
....
switch(base_addr) {
case 2: pbus_read(...); break;
case 1: ...
... } TL TL TL
...
Functional Model
TL
Component
TL TL
RTL
A Complete TL SoC Design
Component
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 2

3. Task Description
Free IP "Plasma"
F "Pl "
enhancement / Plasma VHDL Model Plasma C Model
bug fixes alignment
restructure
SPINNI VHDL Model SPINNI C Model refinement
....
switch(base_addr) {
it h(b dd )
case 2: pbus_read(...); break;
case 1: ...
... }
...
functional comparison
f ti l i
SPINNI TL Model
timing
comparison
SPINNI Timed TL Model
Presentation Part
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 3

4. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 4

5. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 5

6. Principles of TL Modeling
Initiator Target
initiator_port target_port
implements a
remote function call
function
Transactions : communication between modules via
function calls
Synchronization : no toggling clock, time-based or
event-based
Modules : basic building blocks
Ports : bind modules and channels
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 6

7. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 7

8. SPINNI VHDL & C Models
SPINNI: Restructure Plasma
Get a clear architecture
Plasma Model SPINNI Model
restructure
Make the modules traceable and comparable
Make the model extensible
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 8

9. SPINNI VHDL & C Models
SPINNI VHDL Model
irq_sig
CPU
gpio_irq
timer_irq
Main_Bus ICU 4 uart_irq
2
GPIO 2
Timer
Periph_Bus
UART
RAM XRAM
TBE1 TBE2
Fig. 2.1: Block Diagram of the SPINNI VHDL Model
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 9

10. SPINNI VHDL & C Models
SPINNI C Model
irq_sig
CPU
cpu_run
gpio_irq
timer_irq
Main_Bus ICU 4 uart_irq
2
GPIO 2
Timer
Ti
Periph_Bus
main_bus_write UART
main_bus_read RAM XRAM
TBE1 TBE2
ram_write xram_write periph_bus_write
ram_read xram_read periph_bus_read
uart_write gpio_write
uart_read
t d gpio_read
i d
Fig. 2.2: Hierarchical Function Calls
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 10

11. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 11

12. Refinement from C to TL
Structure Based Refinement
SPINNI C Model
Module Access Type
uart_read
uart_write
uart write
ram_read
... ...
Module
SPINNI TL UART Module Access
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 12

13. Refinement from C to TL
Combining Created TL Modules
irq_sig
CPU
gpio_irq
ICU timer_irq
Main_Bus 4 uart_irq
2
GPIO 2
Timer
Periph_Bus
RAM XRAM
UART
: sc_port : sc_export
TBE1 TBE2
Fig. 3.1: Block Diagram of the SPINNI TL Model
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 13

14. Refinement from C to TL
Implementation of C Functions in Module Interfaces
irq_sig
CPU
periph_bus_read
main_bus_read
gpio_irq
ICU timer_irq
Main_Bus 4 uart_irq
ead
2
gpio_re
GPIO 2
ram_read xram_read
Timer
Periph_Bus
uart_read
RAM XRAM
UART
: sc_port
sc port : sc_export
sc export
TBE1 TBE2
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 14

15. Refinement from C to TL
SPINNI TL Model
Reflects the functionality of the SPINNI VHDL model
Enables SW development, co-simulation of HW and SW
No timing information
no prediction for the overall performance of the system
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 15

16. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 16

17. Timing Accuracy
Measure & add timing information
VHDL RTL Model TL Model
Timing
Information
time
time
Basic ways to add timing
y g
¬ Time-based: wait(time)
¬ Event-based: event_name.notify(time)
¬ …
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 17

18. Timing Accuracy
Selected Problem Cases
1. How to align timing after reset ?
2. How to align instruction processing timing ?
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 18

19. Timing Accuracy
Align Timing after Reset
n cycles
l
reset
register1 0
i t 1 4
(a) In the SPINNI VHDL Model
void initialize() { trigger
register1 = 0;
// notify event void module_run() {
// after n cycles register1 = 4;
} }
register1 0 4
(b) In the SPINNI TL Model
* assuming the reset lasts n clock cycles in the SPINNI VHDL model
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 19

20. Timing Accuracy
Align Instruction Processing Timing
Clock Cycle # 0 1 2 3 4 5
Stage 1: Instruction Fetch
Stage 2: Execution
(a) Two Pipeline Stages in the SPINNI VHDL Model
wait (time)
(b) No Pipeline Stage in the SPINNI TL Model
Note: “time” in “wait (time)” equals to 1 clock period of the SPINNI VHDL Model
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 20

21. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 21

22. Validation of Concept
Regression Automation for Functional Comparison
50 test cases k-th Test Case
VHDL Model C Model TL Models
New VHDL E
N Execution
ti New C Execution New TL E
N Execution
ti
Instruction Memory Instruction Memory Instruction Memory
Trace Dumps Trace Dumps Trace Dumps
Golden Reference
Instruction Memory
Trace
T Dumps
D
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 22

23. Validation of Concept
Selected Test Simulation Time VHDL (ns) Simulation Time TL (ns)
Algorithmic Test 42942800 42942800
I/O Test 5441500 5441500
IRQ Test 7331400 7331400
Fig. 5.1: Simulation Time Comparison between VHDL & Timed TL Models
50 User CPU Time VHDL (s)
45 User CPU Time TL (s)
40
35 Selected User CPU User CPU Factor
30 Test Time VHDL Time TL
(sec.) (sec.)
25
20 g
Algorithmic 0.87
40.87 2.87
.87 14
15 Test
10 I/O Test 14.40 1.25 12
5 IRQ Test 18.21 1.51 12
0
Test case 1 Test case 2 Test case 3
Fig. 5.2: User CPU Time Comparison between VHDL & Timed TL Models
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 23

24. Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 24

25. Conclusion & Outlook
Conclusion
SPINNI system with a clear architecture
Shown how to refine C to TL model
Ways for adding timing information to the TL model
Cases to make the timing accurate using RTL model
Method for functional comparison, results of timing comparison
comparison
Outlook
Adopt the forthcoming TLM standard v2.0 for further improvement of
performance
Develop a methodology for fully automatic timing integration
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 25

26. Thank You!
Any Question?
Contact: Hui Chen hui.chen@ieee.org
April 22, 2008 Consistent Modeling Technique for Accurate Transaction Level Models Page 26