1. The document examines the effect of laser spike annealing dwell time on wafer stress and photolithography overlay errors. It finds that reducing dwell time decreases wafer deformation, which helps reduce overlay errors. 2. Testing on boron-implanted wafers showed that sheet resistance, an indicator of dopant activation, has a weak dependence on dwell time and is primarily influenced by temperature. 3. Experiments on patterned SiGe wafers found that lowering dwell time increases the temperature threshold for slip or stress-induced defects. This is because a lower dwell time increases the strain rate during annealing due to the wafer's viscoelastic properties.

1. Impact of Laser Spike Annealing Dwell Time on Wafer
Stress and Photolithography Overlay Errors
Shrinivas Shetty1
, Amitabh Jain2
, David M.Owen1
, Jeffrey Mileham1
, Jeff Hebb1
, and Yun Wang1
1
Ultratech Inc., 3050 Zanker Rd., San Jose, California, 95134, USA
2
External Development and Manufacturing, Texas Instruments Inc., 13121 TI Boulevard, MS 365, Dallas, TX 75243, USA
E-mail: sshetty@ultratech.com
The use of strained SiGe is essential to improvement in device performance. However, the
structure is susceptible to strain relaxation and wafer deformation during thermal annealing. The
accumulation of stress in the wafer needs to be controlled to minimize photolithographic overlay
errors. Laser spike annealing offers negligible pattern effects, closed-loop temperature control, and
localized heating, which help control stress intensity and variation. This paper describes the effect
of dwell time on deformation and its contribution to overlay error. By the use of a stress
measurement technology, the Coherent Gradient Sensing (CGS) interferometer, a detailed
characterization of deformation induced during micro-second laser annealing can be correlated to
the overlay error.
1. Introduction
Sub-melt, sub-millisecond laser spike annealing (LSA)
allows for device fabrication with abrupt, ultra-shallow, and
highly-activated low-resistivity junctions. As a result, short
channel effects are minimized leading to significant gains in
device performance [1-5]. Figure 1 shows an example of
how device performance can be improved by integrating
LSA into the process flow for source/drain activation. In this
particular 65 nm device technology, the nMOSFET drive
current (for a specified sub-threshold leakage) improves up
to approximately 8% with increasing LSA temperature, as
compared to the RTA spike anneal baseline [6].
0.0%
2.0%
4.0%
6.0%
8.0%
10.0%
1150 1200 1250 1300
LSA Process Temperature (°C)
DeviceGain(Percent)
Figure 1 – nMOSFET drive current gain over the RTA baseline vs.
LSA process temperature.
An important consideration in device manufacturing is
contact-to-gate photolithographic overlay error, whose
requirements become more stringent as devices are
increasingly scaled. Contrary to improvements in device
performance with increased annealing temperature, there is
potential for increased overlay error as the temperature is
increased due to plastic deformation. The LSA process
exhibits low process-induced stress and deformation. One
potential source of stress is temperature non-uniformity on
patterned wafers. On a local scale, LSA practically
eliminates this non-uniformity by utilizing a long
wavelength laser (10.6 µm) incident at the Brewster angle,
which allows for negligible local temperature variation on
patterned wafers [7]. An advantageous feature of an ultra-
high temperature sub-millisecond time-scale annealing
process is that only a small portion of the wafer near the
surface is at an elevated temperature allowing the rest of the
wafer to act as a sink for thermal and mechanical energy.
This results in rapid cool down of the annealed region,
which limits diffusion, thus allowing shallow junction
formation. However, this means the existence of high
thermal gradients, which can drive dislocation movement,
and slip, which leads to wafer bow. This is because
mechanical energy that is not dissipated elastically, gets
stored plastically in the form of dislocations and other
defects [8]. The bow can make registration difficult when
attempting photolithographic alignment at the contact level
and leads to overlay errors.
An advantage of LSA for controlling such wafer stress and
deformation is its ability to reduce the annealing time. The
annealing time may be quantified using the term dwell time,
which is defined as the amount of time a point on the silicon
wafer spends under the “full width half maximum” of the
CO2 beam as the wafer is being scanned. Control of the
dwell time allows one to take advantage of the viscoelastic
property of silicon. Due to its viscoelasticity, silicon will
resist dislocation generation and movement when the strain
rate is high. This paper investigates the effect of dwell time
on sheet resistance and overlay error. The annealing-induced
stress is measured directly using the Coherent Gradient
Sensing (CGS) interferometer and the overlay error is
related to the distribution of the stress as measured by this
technique. We show that by reducing the dwell time, one can
reduce overlay errors during photolithographic alignment.

2. 2. Overview of the LSA Technology and CGS Technique
LSA-100A System
A schematic of the LSA system including the pyrometer and
feedback loop is shown in Figure 2. The CO2 laser beam is
conditioned through a system of reflective optics and
brought to the wafer plane as a line beam where it locally
heats the wafer. The wafer sits on a heated chuck mounted
on an X-Y stage, and the stage is programmed to scan the
wafer under the CO2 line beam. The temperature of the
locally heated region is determined by measuring the
intensity (I) of the emitted radiation and converting that
intensity into peak wafer temperature (Tw) using a
proprietary conversion algorithm. This temperature is fed
into the control loop, and a small correction is made to the
next cycle of the laser power to maintain a uniform peak
temperature. The pyrometer's design suppresses the effect of
front-side emissivity variations caused by thin-film
interference effects. The control loop frequency of 10 kHz is
~10 times greater than the silicon's thermal response time
ensuring tight temperature control to within a few degrees
[9].
CO2
Laser
10
kHz
Reflective
Optics
X-Y
stage
I
Temperature
Conversion Algorithm
ΔP
Tw
Collection
Optics
Temperature
Control Algorithm
Ttarget
Chuck
I
Emission
Detector
Figure 2 – Schematic of the LSA temperature measurement and
control system.
CGS-300 System
The CGS-300 is a stress metrology system that has unique
features compared to traditional stress metrology and wafer
warpage measurements [10, 11]. The CGS system generates
stress maps of high spatial resolution (>700,000 points on a
300mm wafer) and the repeatability of CGS when measuring
process-induced wafer bow is less than 1000Å, 1-sigma. The
detailed data available from CGS enables characterization of
within die-stress variations as well as providing detailed
information at the wafer edge with over 100,000 data points
within 15mm of the wafer edge.
3. Dwell Time Impact on Processing and Deformation
As discussed above, the LSA process has the advantage of
negligible pattern effect, closed-loop temperature control,
and local heating – all of which contribute to low stress non-
uniformity during processing. Another critical variable is the
dwell time, which can be controlled on the LSA system by
simply changing the stage velocity in the scan direction.
The power density required to meet a given temperature
needs to be increased as the dwell time is reduced. Figure 3
shows the relationship between the power density required
to melt silicon and dwell time. The dependence arises
because the heat diffusion length scales with the square root
of dwell time.
0.3
0.4
0.5
0.6
0.7
0.8
0 200 400 600 800 1000 1200
Dwell Time (µs)
PowerDensity(kW/mm
2
)
Figure 3 – Power density required to melt Si vs. dwell time. The
power density is calculated based on the beam size (full width at
half maximum).
One of the main considerations in LSA processing is the
activation of the dopants. The level of activation can be
measured indirectly by the sheet resistance. A set of
experiments were run on boron-implanted wafers to
investigate the role of dwell time on sheet resistance. Figure
4 shows the sheet resistance measured using four different
dwell times versus temperature. Over a temperature range of
~250°C it is clear from Figure 4 that sheet resistance has a
weak dependence on dwell time indicating that the
temperature is the dominant factor affecting the dopant
activation.
0
100
200
300
400
1100 1200 1300 1400
Temperature (°C)
SheetResistance(Ω/sq.)
400µs
600µs
800µs
1000µs
Figure 4 – Sheet resistance vs. temperature for boron implants at
various values of dwell time.
Silicon-Germanium (SiGe) is typically used to strain-
engineer semiconductor devices for increased performance.
However, interfacial dislocations and slip can occur during
annealing, and this problem becomes exacerbated as the
amount of Ge concentration increases. The yield criterion for
T = TSi melt

3. slip is both temperature and strain rate dependent, each of
which are controllable in the LSA system. Since it is
desirable to keep peak temperature as high as possible for
increased activation, it is necessary to explore the impact of
dwell time on slip.
Patterned SiGe wafers with 20 at.% Ge were implanted and
annealed at various values of dwell time and temperature to
investigate the influence of dwell time on the slip threshold
temperature. After processing, evidence for slip was
investigated by visual inspection using a Nomarski phase
contrast microscope. The threshold for slip is the
temperature at which multiple slip lines are first seen under
the microscope. A large area of 24 mm x 90 mm was used
for each experimental condition in order not to miss the
onset of slip. The results shown in Figure 5 provide evidence
that lowering the dwell time helps prevent the occurrence of
slip, which is an indication of stress and deformation.
1200
1225
1250
1275
1300
1325
200 400 600 800 1000
Dwell Time (µs)
SlipThreshold(°C)
Figure 5 – Temperature at which slip appears as a function of dwell
time.
Physically, the concept of viscoelasticity can be used as a
model of the strain rate dependence of the slip threshold.
Viscoelastic behavior can be thought of as a spring and
dashpot in series. In the LSA system, lowering the dwell
time will increase the heating rate (dT/dt), thus increasing
the strain rate. At high strain rates achieved by lowering the
dwell time, the yield criterion increases resulting
deformation that is increasingly elastic. These elastic
deformations result in a reduction of the formation of
dislocations and interfacial defects.
On the scale of a device structure, strained-SiGe relaxation
can be modeled through energy considerations [12, 13]. The
onset of dislocation nucleation will occur when the
incremental change in elastic energy due to a dislocation is
more favorable (lower total energy) than an incremental
increase in the epitaxial mismatch strain within the structure.
In the context of LSA, reducing the dwell time reduces the
total energy the structure has to accommodate and
temporarily store elastically. In other words, there is less
energy available for dislocation nucleation and propagation.
Thus, lowered dwell time leads to the ability of LSA to
anneal to high temperatures and in turn produce device
performance improvements.
4. Dwell Time Impact on Device Overlay
Full flow 65nm device wafers with SiGe (20 at.% Ge) were
implanted and annealed using LSA and the overlay
registration error was measured. Figure 6 shows examples of
the mis-alignment residuals for wafers processed at 400µs
and 800µs. Comparison of the offset vectors in the two
overlay maps reveals a significant improvement at shorter
dwell time.
Figure 6 – Overlay registration error for 400µs and 800µs showing
improvement at the shorter dwell time. (The local registration error
is indicated by the vectors in the diagrams).
Figure 7 provides the summary overlay data for wafers with
no processing, 400µs dwell time, and 800µs dwell time.
0
0.02
0.04
Dwell Time
OverlayError(µm)
RMS X Error
RMS Y Error
No LSA
400µs
800µs
Figure 7 – Photolithographic overlay data for a Si-Ge flow.
The data are root mean square registration errors calculated
from the alignment offsets at each aim mark on the wafer.
The errors are in the vertical direction and this is related to
the scanning direction. Overlay errors increase in frequency
and magnitude as wafer bow increases due to increased
stress non-uniformity. The stress uniformity can be
significantly improved by employing a shorter dwell time
during LSA processing.
The CGS stress data can be used to correlate and predict
overlay error. Mechanical equilibrium can be used to analyze
the forces acting any small volume of the structure at any
point on the wafer [14]. The result is that the stress gradients
lead to shear stresses (σxz and σyz) along the interface
between the device structure and the underlying substrate or
structure. Specifically, the interfacial shear stresses in the x-
400µs 800µs

4. direction (σxz) and y-direction (σyz) are proportional to the
in-plane stress gradients,
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
∂
∂
+
∂
∂
∝
yx
xyxx
xz
σσ
σ (1a)
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
∂
∂
+
∂
∂
∝
yx
yyxy
yz
σσ
σ (1b)
The interfacial shear stresses may cause relative slip or shear
of the two layers. The term ‘mis-alignment potential’ has
been used to describe the two gradient quantities in the
above equations and can be computed from the CGS stress
maps. It should be noted that the high-point density CGS
maps uniquely enable this application of stress measurement
to overlay since lower density maps will have insufficient
data points to accurately calculate the gradients.
The x-direction and y-direction mis-alignment potentials
(equations 1a and 1b, respectively) can be used to construct
vector maps to visualize the data. Figure 8 shows examples
of the mis-alignment potential vector maps for an anneal
process at 1270°C and 200µs (Figure 8a) and 1270°C and
400µs (Figure 8b) from patterned (20 at.% Ge) wafers. The
shorter dwell time process exhibited much more uniform
stress than the longer dwell time process and this is reflected
in the vector magnitudes.
Figure 8 – Examples of CGS mis-alignment potential vector maps
calculated from stress gradients: a) shorter dwell time (200µs at
1270°C), b) longer dwell time (400µs at 1270°C).
The vector maps in Figure 8 provide a qualitative example
of the correlation between stress gradients and overlay,
however quantitative correlations between the stress
gradients and traditional overlay residuals have also been
established. Figure 9 shows the correlation between the
wafer average mis-alignment potentials due to annealing
versus the wafer average mis-alignment residuals measured
after laser annealing, during post-lithography inspection at
the contact patterning stage. The ‘x’ and ‘y’ components are
plotted separately for each of the four wafers. The four
wafers were processed by LSA at two different dwell times
(200μs and 400μs) and at two different temperatures
(1235°C and 1270°C). The wafer processed at 1270°C for
each dwell time exhibits the higher mis-alignment potential
in each case. Figure 9 shows that the data fall on a straight
line and the x and y data mis-alignment potential data
correlate independently to the overlay residuals. In addition,
the straight-line fit intersects the overlay residuals axis at a
normalized value of ~0.4. The intercept indicates the
contribution of all the other processes to the overlay error.
The intercept correlates well with the error from a wafer not
processed through laser annealing as shown by the circle at
zero misalignment potential on the figure.
0
2
4
6
8
10
12
0.4 0.8 1.2 1.6 2 2.4 2.8
Overlay Residuals (Normalized)
CGSMis-alignmentPotential
(Normalized)
No LSA
x-residual, 200µs, 1270°C
x-residual, 200µs, 1235°C
y-residual, 200µs, 1270°C
y-residual, 200µs, 1235°C
x-residual, 400µs, 1270°C
x-residual, 400µs, 1235°C
y-residual, 400µs, 1270°C
y-residual, 400µs, 1235°C
Figure 9 – Correlation between overlay residuals and the CGS mis-
alignment potential.
5. Summary
Laser spike anneal offers advantage in terms of reducing the
stress and deformation during high-activation by sub-melt
annealing of devices. This is especially critical for device
wafers using SiGe, which makes the wafer more susceptible
to plastic deformation. In the particular example showed in
this work, reducing the LSA dwell time by a factor of two
reduced the average overlay error without detrimental effects
to the activation. This reduction in overlay errors allowed
the annealing temperature to be increased, which improves
device performance due to increased activation. The use of
CGS allows one to determine the mis-alignment potential by
correlating wafer stress gradients to overlay error.
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Acknowledgments
We wish to thank Dr. Jim Chambers for a critical reading of the
manuscript.
(a) (b)