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Cortex M Bootup & CMSIS - Part 1 / 3
Raahul Anand Raghavan, Lead Systems Architect,
Glyton Solutions
!1
Agenda
• Before We Proceed!
• Introduction to CMSIS
• CMSIS Modules
• Bootup Fundamentals
• ARM® Cortex M System Level Mem...
Before We Proceed!
• This is a 3 part presentation which would practically
introduce ARM® Cortex M boot up / system initia...
Introduction to CMSIS (1 / 2)
!4
Cortex M processor
Firmware
Middleware
Application Code
Firmware Before CMSIS
No common s...
Introduction to CMSIS (2 / 2)
!5
Cortex M processor
Middleware
Application Code
Firmware After CMSIS
Modular,Functionally ...
CMSIS Modules
!6
CMSIS-Core
CMSIS-SVD
CMSIS-DAP
CMSIS-RTOS API
CMSIS-Driver API
CMSIS-DSP
HAL(Systick,NVIC,SCB,MPU,FPU),sy...
Bootup Fundamentals
!7
• What is Boot-up (or) system initialization ?
• Setting up the required environment on chip and as...
Cortex M Core - System Memory Map (1 / 3)
!8
Code
(512MB)
0x00000000
0x1FFFFFFF
SRAM
(512MB)
0x20000000
0x3FFFFFFF
Periphe...
Cortex M Core - System Memory Map (2 / 3)
!9
ROM Table
(4KB)
0xE00FFFFF
Reserved
ETM
(4 KB)
TPIU
(4 KB)
Reserved
System Co...
Cortex M Core - System Memory Map (3 / 3)
!10
CPACR and FP
CPUID
FSRs & FARs
SHCSR
SHPR3
SHPR2
SHPR1
CCR
SCR
AIRCR
VTOR
IC...
Accessing Memory Mapped Control Registers
!11
• CMSIS Core Register Abstraction headers files
• Ex: core_cmx.h (X could be ...
Processor Modes, Privilege & Stacks
!12
• Only two modes
• Handler Mode — Used to handle exceptions.
Main stack is used
• ...
Whats in Part 2 ?
!13
• Typical Cortex M Boot up sequence
• Setting up EFM®32 starter kit with Silicon Labs SDK
• Set Brea...
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ARM® Cortex M Boot & CMSIS Part 1-3

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ARM® Cortex M Boot & CMSIS Part 1-3

  1. 1. Cortex M Bootup & CMSIS - Part 1 / 3 Raahul Anand Raghavan, Lead Systems Architect, Glyton Solutions !1
  2. 2. Agenda • Before We Proceed! • Introduction to CMSIS • CMSIS Modules • Bootup Fundamentals • ARM® Cortex M System Level Memory Map • Processor Modes, Privilege level and Stacks • Whats in Part 2 ? !2
  3. 3. Before We Proceed! • This is a 3 part presentation which would practically introduce ARM® Cortex M boot up / system initialization & CMSIS interface • Involves Cortex M0 based EVM and a suitable IDE • Official Documentation from ARM®, Silicon Labs will override information provided here. Treat official TRM’s as complete guides on Subject Matter • ARM® Cortex® M trademark - ARM Ltd • EFM®32, Silicon Labs SDK etc are registered trademarks !3
  4. 4. Introduction to CMSIS (1 / 2) !4 Cortex M processor Firmware Middleware Application Code Firmware Before CMSIS No common specification across silicon vendors using ARM® Cortex M IP Firmware interface specification is silicon vendor specific Porting RTOS, peripheral code complicated Lengthy learning curve & Negative Impact on Time to Market
  5. 5. Introduction to CMSIS (2 / 2) !5 Cortex M processor Middleware Application Code Firmware After CMSIS Modular,Functionally mapped.Standardized Interface Specification for various modules defined by ARM®. Port RTOS, peripheral device driver code with more ease Less learning curve & Reduced Time to Market CMSIS-Core CMSIS-SVD CMSIS-DAP CMSIS-DSP CMSIS- RTOS API CMSIS- Driver API Debugger IDE
  6. 6. CMSIS Modules !6 CMSIS-Core CMSIS-SVD CMSIS-DAP CMSIS-RTOS API CMSIS-Driver API CMSIS-DSP HAL(Systick,NVIC,SCB,MPU,FPU),system initialization,system exception names,CPU specific intrinsic functions etc Provides programmers view for memory mapped peripherals. Maintained by Silicon Vendors Standardized firmware for a debugger connecting to on chip coresight debug access port Standardized API’s RTOS interface RTOS independent API’s connecting middleware stack to MCU peripherals Collection of DSP Libraries CMSIS-PACK Software package including all necessary headers,source files, libraries,examples, flash programmers for a specific eval module
  7. 7. Bootup Fundamentals !7 • What is Boot-up (or) system initialization ? • Setting up the required environment on chip and associated peripherals, leading up to application code execution • Initialize • Core (Clock,NVIC, System timers, Exception Handlers etc…) • Peripherals • Copy code from NV (On Chip or On Board NAND / NOR / eMMC) to RAM or SRAM • Setup C Runtime environment • …….. • How ? • By programming various memory mapped registers which in turn control MCU using CMSIS core interfaces • What system level information do we need to know ? • System Memory Map (System Control Space,Systick timer, NVIC etc) • System Instructions & CMSIS Core Interfaces • Exceptions handlers • ……..
  8. 8. Cortex M Core - System Memory Map (1 / 3) !8 Code (512MB) 0x00000000 0x1FFFFFFF SRAM (512MB) 0x20000000 0x3FFFFFFF Peripheral (512MB) 0x40000000 0x5FFFFFFF RAM (512MB) 0x60000000 0x7FFFFFFF RAM (512MB) 0x80000000 0x9FFFFFFF Device (512MB) 0xA0000000 0xBFFFFFFF Device (512MB) 0xC0000000 0xDFFFFFFF System (512MB) 0xE0000000 0xFFFFFFFF Vendor_Sys 0xE0100000 0xFFFFFFFF PPB (1 MB) 0xE0000000 0xE00FFFFF ROM Table (4KB) 0xE00FFFFF Reserved ETM (4 KB) TPIU (4 KB) Reserved System Control Space (4 KB) Reserved FPB (4 KB) DWT (4 KB) ITM (4 KB) 0xE0000000
  9. 9. Cortex M Core - System Memory Map (2 / 3) !9 ROM Table (4KB) 0xE00FFFFF Reserved ETM (4 KB) TPIU (4 KB) Reserved System Control Space (4 KB) Reserved FPB (4 KB) DWT (4 KB) ITM (4 KB) 0xE0000000 µC-specific ID Implementation
 Defined SW Triggered Interrupt Debug MPU System Control Block NVIC SysTick Auxiliary Control 0xE000E000 0xE000F000 CPACR and FP CPUID FSRs & FARs SHCSR SHPR3 SHPR2 SHPR1 CCR SCR AIRCR VTOR ICSR CPUID
  10. 10. Cortex M Core - System Memory Map (3 / 3) !10 CPACR and FP CPUID FSRs & FARs SHCSR SHPR3 SHPR2 SHPR1 CCR SCR AIRCR VTOR ICSR CPUID Coprocessor Access Control and FP registers Reserved for other CPUID registers Fault status and address registers System Handler Control and State Register System Handler Priority Register 3 System Handler Priority Register 2 System Handler Priority Register 1 Configuration and Control Register System Control Register Application Interrupt and Reset Control Register Vector Table Offset Register Interrupt Control and State Register CPUID Base Register
  11. 11. Accessing Memory Mapped Control Registers !11 • CMSIS Core Register Abstraction headers files • Ex: core_cmx.h (X could be 0,3,4 etc based on which Cortex M Core is used) • CMSIS core Intrinsic function interface for accessing and configuring System Control Space • More on this in Part 2 when we take a look at a Cortex M0 based EVM boot up
  12. 12. Processor Modes, Privilege & Stacks !12 • Only two modes • Handler Mode — Used to handle exceptions. Main stack is used • Thread Mode — Used to execute application code. Main (or) Process Stack.Refer to the table below ! • Privilege Levels • Privileged — Access to all processor resources and instructions • Unprivileged — Restricted access to core register read and write instructions (MSR,MRS) Mode Privilege Stack Pointer Usage Scenario Handler Privileged Main Exception Handling. Also upon reset Thread Privileged Main Privileged Process execution using main/common stack Process Privileged process execution using individual process specific stack Thread Unprivileged Main Unprivileged process execution using main/common stack Process Privileged process execution using individual process specific stack
  13. 13. Whats in Part 2 ? !13 • Typical Cortex M Boot up sequence • Setting up EFM®32 starter kit with Silicon Labs SDK • Set Break points & Investigate various stages during boot up sequence • Map CMSIS Core API’s with boot up stages identified above • Follow up in Part 3…

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