Self-Tuning Wireless Network Power ManagementSumin Byeon
Explores strategies to design and implement an intelligent power management module that adapts to the usage pattern and the characteristics of the network interface card.
Anand, Manish, Edmund B. Nightingale, and Jason Flinn. "Self-Tuning Wireless Network Power Management." Wireless Networks 11.4 (2005): 451-69. Print.
Taming Latency: Case Studies in MapReduce Data AnalyticsEMC
This session discusses how to achieve low latency in MapReduce data analysis, with various industrial and academic case studies. These illustrate various improvements on MapReduce for squeezing out latency from whole data processing stack, covering batch-mode MapReduce system, as well as stream processing systems. This session also introduces our BoltMR project efforts on this topic and discloses some interesting benchmark results.
Objective 1: Understand why low-latency matters for many MapReduce-based big data analytics scenarios.
After this session you will be able to:
Objective 2: Learn the root causes of MapReduce latency, the obstacles to lowering the latency and the various (im)mature solutions.
Objective 3: Understand the extent of MapReduce low-latency that is needed for their own applications and which optimization techniques are potentially applicable.
Approximation techniques used for general purpose algorithmsSabidur Rahman
Survey on approximation techniques used for general purpose algorithms, data parallel applications ans solid-state memories. It is interesting to see how approximation algorithms can contribute to solve real-life problems with better efficiency and lower cost!
Questions? krahman@ucdavis.edu.
Self-Tuning Wireless Network Power ManagementSumin Byeon
Explores strategies to design and implement an intelligent power management module that adapts to the usage pattern and the characteristics of the network interface card.
Anand, Manish, Edmund B. Nightingale, and Jason Flinn. "Self-Tuning Wireless Network Power Management." Wireless Networks 11.4 (2005): 451-69. Print.
Taming Latency: Case Studies in MapReduce Data AnalyticsEMC
This session discusses how to achieve low latency in MapReduce data analysis, with various industrial and academic case studies. These illustrate various improvements on MapReduce for squeezing out latency from whole data processing stack, covering batch-mode MapReduce system, as well as stream processing systems. This session also introduces our BoltMR project efforts on this topic and discloses some interesting benchmark results.
Objective 1: Understand why low-latency matters for many MapReduce-based big data analytics scenarios.
After this session you will be able to:
Objective 2: Learn the root causes of MapReduce latency, the obstacles to lowering the latency and the various (im)mature solutions.
Objective 3: Understand the extent of MapReduce low-latency that is needed for their own applications and which optimization techniques are potentially applicable.
Approximation techniques used for general purpose algorithmsSabidur Rahman
Survey on approximation techniques used for general purpose algorithms, data parallel applications ans solid-state memories. It is interesting to see how approximation algorithms can contribute to solve real-life problems with better efficiency and lower cost!
Questions? krahman@ucdavis.edu.
With the laws of physics providing a nice brick wall that chip builders are heading towards for processor clock speed, we are heading into the territory where simply buying a new machine won't necessarily make your batch go faster. So if you can't go short, go wide! This session looks at some of the performance issues and techniques of splitting your batch jobs into parallel streams to do more at once.
MAC: A NOVEL SYSTEMATICALLY MULTILEVEL CACHE REPLACEMENT POLICY FOR PCM MEMORYcaijjournal
The rapid development of multi-core system and increase of data-intensive application in recent years call
for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size
of storage cell. Now further scaling of DRAM faces great challenge, and the frequent refresh operations of
DRAM can bring a lot of energy consumption. As an emerging technology, Phase Change Memory (PCM)
is promising to be used as main memory. It draws wide attention due to the advantages of low power
consumption, high density and nonvolatility, while it incurs finite endurance and relatively long write
latency. To handle the problem of write, optimizing the cache replacement policy to protect dirty cache
block is an efficient way. In this paper, we construct a systematically multilevel structure, and based on it
propose a novel cache replacement policy called MAC. MAC can effectively reduce write traffic to PCM
memory with low hardware overhead. We conduct simulation experiments on GEM5 to evaluate the
performances of MAC and other related works. The results show that MAC performs best in reducing the
amount of writes (averagely 25.12%) without increasing the program execution time.
Paper chosen for DesignCon 2015. Critical Memory Performance Metrics for DDR4. Is DDR4 the end of the DDR line of memory technologies? If so then stretching DDR4 to give that much more performance is critical. Discussed in this paper is how to measure the intricate performance metrics of your DDR4 system and why they matter. Understanding these critical parameters can lead to better system design, memory controller architecture and software design. Metrics such as Power Management, Page Hits, Bank Group and Bank Utilization, Multiple Open Bank Analysis, Data Bus Utilization and overhead on a DDR4 memory bus will be demonstrated and discussed.
Hardback solution to accelerate multimedia computation through mgp in cmpeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
ENERGY-AWARE DISK STORAGE MANAGEMENT: ONLINE APPROACH WITH APPLICATION IN DBMSijdms
Energy consumption has become a first-class optimization goal in design and implementation of dataintensive
computing systems. This is particularly true in the design of database management systems
(DBMS), which was found to be the major consumer of energy in the software stack of modern data
centers. Among all database components, the storage system is one of the most power-hungry elements. In
previous work, dynamic power management (DPM) techniques that make real-time decisions to transition
the disks to low-power modes are normally used to save energy in storage systems. In this paper, we tackle
the limitations of DPM proposals in previous contributions. We introduced a DPM optimization model
integrated with model predictive control (MPC) strategy to minimize power consumption of the disk-based
storage system while satisfying given performance requirements. It dynamically determines the state of
disks and plans for inter-disk data fragment migration to achieve desirable balance between power
consumption and query response time. Via analyzing our optimization model to identify structural
properties of optimal solutions, we propose a fast-solution heuristic DPM algorithm that can be integrated
in large-scale disk storage systems for efficient state configuration and data migration. We evaluate our
proposed ideas by running simulations using extensive set of synthetic workloads based on popular TPC
benchmarks. Our results show that our solution significantly outperforms the best existing algorithm in
both energy savings and response time.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded...IJECEIAES
Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3% - 7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP.
With the laws of physics providing a nice brick wall that chip builders are heading towards for processor clock speed, we are heading into the territory where simply buying a new machine won't necessarily make your batch go faster. So if you can't go short, go wide! This session looks at some of the performance issues and techniques of splitting your batch jobs into parallel streams to do more at once.
MAC: A NOVEL SYSTEMATICALLY MULTILEVEL CACHE REPLACEMENT POLICY FOR PCM MEMORYcaijjournal
The rapid development of multi-core system and increase of data-intensive application in recent years call
for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size
of storage cell. Now further scaling of DRAM faces great challenge, and the frequent refresh operations of
DRAM can bring a lot of energy consumption. As an emerging technology, Phase Change Memory (PCM)
is promising to be used as main memory. It draws wide attention due to the advantages of low power
consumption, high density and nonvolatility, while it incurs finite endurance and relatively long write
latency. To handle the problem of write, optimizing the cache replacement policy to protect dirty cache
block is an efficient way. In this paper, we construct a systematically multilevel structure, and based on it
propose a novel cache replacement policy called MAC. MAC can effectively reduce write traffic to PCM
memory with low hardware overhead. We conduct simulation experiments on GEM5 to evaluate the
performances of MAC and other related works. The results show that MAC performs best in reducing the
amount of writes (averagely 25.12%) without increasing the program execution time.
Paper chosen for DesignCon 2015. Critical Memory Performance Metrics for DDR4. Is DDR4 the end of the DDR line of memory technologies? If so then stretching DDR4 to give that much more performance is critical. Discussed in this paper is how to measure the intricate performance metrics of your DDR4 system and why they matter. Understanding these critical parameters can lead to better system design, memory controller architecture and software design. Metrics such as Power Management, Page Hits, Bank Group and Bank Utilization, Multiple Open Bank Analysis, Data Bus Utilization and overhead on a DDR4 memory bus will be demonstrated and discussed.
Hardback solution to accelerate multimedia computation through mgp in cmpeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
ENERGY-AWARE DISK STORAGE MANAGEMENT: ONLINE APPROACH WITH APPLICATION IN DBMSijdms
Energy consumption has become a first-class optimization goal in design and implementation of dataintensive
computing systems. This is particularly true in the design of database management systems
(DBMS), which was found to be the major consumer of energy in the software stack of modern data
centers. Among all database components, the storage system is one of the most power-hungry elements. In
previous work, dynamic power management (DPM) techniques that make real-time decisions to transition
the disks to low-power modes are normally used to save energy in storage systems. In this paper, we tackle
the limitations of DPM proposals in previous contributions. We introduced a DPM optimization model
integrated with model predictive control (MPC) strategy to minimize power consumption of the disk-based
storage system while satisfying given performance requirements. It dynamically determines the state of
disks and plans for inter-disk data fragment migration to achieve desirable balance between power
consumption and query response time. Via analyzing our optimization model to identify structural
properties of optimal solutions, we propose a fast-solution heuristic DPM algorithm that can be integrated
in large-scale disk storage systems for efficient state configuration and data migration. We evaluate our
proposed ideas by running simulations using extensive set of synthetic workloads based on popular TPC
benchmarks. Our results show that our solution significantly outperforms the best existing algorithm in
both energy savings and response time.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Dynamic Frequency Scaling Regarding Memory for Energy Efficiency of Embedded...IJECEIAES
Memory significantly affects the power consumption of embedded systems as well as performance. CPU frequency scaling for power management could fail in optimizing the energy efficiency without considering the memory access. In this paper, we analyze the power consumption and energy efficiency of an embedded system that supports dynamic scaling of frequency for both CPU and memory access. The power consumption of the CPU and the memory is modeled to show that the memory access rate affects the energy efficiency and the CPU frequency selection. Based on the power model, a method for frequency selection is presented to optimize the power efficiency which is measured using Energy-Delay Product (EDP). The proposed method is implemented and tested on a commercial smartphone to achieve about 3.3% - 7.6% enhancement comparing with the power management policy provided by the manufacturer in terms of EDP.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Memory system, and not processor speed, is often the bottleneck for many applications.
Memory system performance is largely captured by two parameters, latency and bandwidth.
Latency is the time from the issue of a memory request to the time the data is available at the processor.
Bandwidth is the rate at which data can be pumped to the processor by the memory system.
Dr. Sean Tan, Head of Data Science, Changi Airport Group
Discover how Changi Airport Group (CAG) leverages graph technologies and generative AI to revolutionize their search capabilities. This session delves into the unique search needs of CAG’s diverse passengers and customers, showcasing how graph data structures enhance the accuracy and relevance of AI-generated search results, mitigating the risk of “hallucinations” and improving the overall customer journey.
Unlocking Productivity: Leveraging the Potential of Copilot in Microsoft 365, a presentation by Christoforos Vlachos, Senior Solutions Manager – Modern Workplace, Uni Systems
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We’ll kick things off by showcasing the most commonly used event-based triggers, introducing you to various automation workflows like manual triggers, schedules, directory watchers, and more. Plus, see how these elements play out in real scenarios.
Whether you’re tweaking your current setup or building from the ground up, this session will arm you with the tools and insights needed to transform your FME usage into a powerhouse of productivity. Join us to discover effective strategies that simplify complex processes, enhancing your productivity and transforming your data management practices with FME. Let’s turn complexity into clarity and make your workspaces work wonders!
Enchancing adoption of Open Source Libraries. A case study on Albumentations.AIVladimir Iglovikov, Ph.D.
Presented by Vladimir Iglovikov:
- https://www.linkedin.com/in/iglovikov/
- https://x.com/viglovikov
- https://www.instagram.com/ternaus/
This presentation delves into the journey of Albumentations.ai, a highly successful open-source library for data augmentation.
Created out of a necessity for superior performance in Kaggle competitions, Albumentations has grown to become a widely used tool among data scientists and machine learning practitioners.
This case study covers various aspects, including:
People: The contributors and community that have supported Albumentations.
Metrics: The success indicators such as downloads, daily active users, GitHub stars, and financial contributions.
Challenges: The hurdles in monetizing open-source projects and measuring user engagement.
Development Practices: Best practices for creating, maintaining, and scaling open-source libraries, including code hygiene, CI/CD, and fast iteration.
Community Building: Strategies for making adoption easy, iterating quickly, and fostering a vibrant, engaged community.
Marketing: Both online and offline marketing tactics, focusing on real, impactful interactions and collaborations.
Mental Health: Maintaining balance and not feeling pressured by user demands.
Key insights include the importance of automation, making the adoption process seamless, and leveraging offline interactions for marketing. The presentation also emphasizes the need for continuous small improvements and building a friendly, inclusive community that contributes to the project's growth.
Vladimir Iglovikov brings his extensive experience as a Kaggle Grandmaster, ex-Staff ML Engineer at Lyft, sharing valuable lessons and practical advice for anyone looking to enhance the adoption of their open-source projects.
Explore more about Albumentations and join the community at:
GitHub: https://github.com/albumentations-team/albumentations
Website: https://albumentations.ai/
LinkedIn: https://www.linkedin.com/company/100504475
Twitter: https://x.com/albumentations
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Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
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Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
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GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...Neo4j
Leonard Jayamohan, Partner & Generative AI Lead, Deloitte
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Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
Discover how Standard Chartered Bank harnessed the power of Neo4j to transform complex data access challenges into a dynamic, scalable graph database solution. This keynote will cover their journey from initial adoption to deploying a fully automated, enterprise-grade causal cluster, highlighting key strategies for modelling organisational changes and ensuring robust disaster recovery. Learn how these innovations have not only enhanced Standard Chartered Bank’s data infrastructure but also positioned them as pioneers in the banking sector’s adoption of graph technology.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
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UiPath Test Automation using UiPath Test Suite series, part 5
A survey on exploring memory optimizations in smartphones
1. A SURVEY ON EXPLORING
MEMORY OPTIMIZATIONS IN
SMARTPHONES
-KARTHIKEYAN RAMKUMAR
2. ABSTRACT
•
Many memory optimizations have been explored for computer systems and in this survey we explore
their applicability to smartphone hardware.
•
Memory technologies such as Mobile RAM (M-RAM), Power Aware Virtual Memory
(PAVM), Dynamic RAM (DRAM) and On-demand mechanisms such as Immediate Power Down
(IPD) mechanism and Immediate Self Refresh (ISR) mechanism are described in this survey.
•
Newly emerging technologies such as Phase Change Memory (PCM) and a hybrid approach consisting
of both Phase Change Memory and Mobile RAM are also surveyed.
3. INTRODUCTION
•
Additional features and improved user experience, provided by fast processors, copious
memory, resource demanding software, and power-hungry hardware makes energy a precious resource.
With hardware continuously improving in performance and price, vendors are able to build systems
with higher-performance and higher power components trying to meet users’ ever increasing demands
and compete for customers.
•
However, this results in systems that are over-provisioned with components that provide more
capacity, more throughput, and more processing power than needed for the typical workload, and as a
result, it is becoming more difficult to maintain long battery life in these devices.
•
While a smartphone contains many energy hungry components, such as CPU, display, and multiple
radios, energy consumed by memory subsystem has been given limited consideration.
•
Therefore, we explore the efficiency of the existing energy management mechanisms on smartphones.
4. MEMORY TECHNOLOGIES
The memory technologies discussed in this paper include Dynamic RAM (DRAM) which is the most
widely used memory technology in mobile devices and is otherwise referred to as Mobile RAM (MRAM). A recent contender for main memory technology is Phase Change Memory (PCM) which is a type
of non-volatile random-access memory that eliminates idle power due to its non-volatile nature but offers
lower performance than M-RAM. Another memory technology that is described is the Power Aware
Virtual Memory (PAVM), which reduces the energy consumed by the memory in response to workloads
becoming increasingly data-centric. This section describes the various memory technologies and how
they are optimized in smartphones to give a better performance.
5. 1. DYNAMIC RAM (DRAM)
•
Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of
data in a separate capacitor within an integrated circuit.
•
As applications are becoming increasingly data-centric, we expect main memory to remain as a
significant energy consumer because achieving good overall system performance will be more likely to
depend on having higher-performance and larger-capacity DRAM.
•
We use the terminology of the Double-Data Rate (DDR) memory simply because DDR is becoming the
most common type of memory used in today's PC and server systems. This approach is not limited to
only DDR but this technique can also be applied to other memory types, e.g., SDR and RDRAM.
6. 1.1 MEMORY TRAFFIC RESHAPING
•
To reshape the memory traffic for our benefit, we must make memory access less random and more
controllable.
•
We use a 4-rank system wherein memory requests are likely to be randomly distributed among the 4
ranks and this creates a large number of small and medium sized idle periods.
•
To elongate idle periods, the concepts of hot and cold ranks are introduced.
•
Since more opportunities are created on cold ranks since Self Refresh can be more utilized, more
valuable opportunities are created in it.
7. 1.1 MEMORY TRAFFIC RESHAPING
In the experiments conducted, the average
interarrival time was elongated by almost 2
orders of magnitude on cold ranks.
An example showing that if memory traffic
is left unshaped, power management cannot
take full advantage of deeper power-saving
states since most idle periods are too short.
8. 1.2 EFFECT OF RESHAPING ON MEMORY TRAFFIC
•
To study the effect of memory traffic reshaping in more detail, we compare the results of migrating
1%, 5%, and 10% of pages.
•
Migrating only 1 % of pages gives only limited benefits in power reduction. On the other
hand, migrating 10% of pages does not give any additional energy benefit beyond that of migrating
5%. In addition, it also suffers from more performance penalty due to having to migrate more pages.
•
Therefore, migrating 5% of pages gives the best result for the workloads we ran.
9. 1.2 EFFECT OF RESHAPING ON MEMORY TRAFFIC
•
•
To solve the problem at its root, it calls for an.
alternative main memory design, where we
should use high-performance, highly parallel
memory on hot ranks and low-performance lowpower memory on cold ranks.
•
Effects of actively reshaping memory
traffic by migrating 1%, 5%, and 10% of
pages for the low memory intensive
workload (above) and high memoryintensive workload (below).
As we can see from the Figure, migrating 1% as
opposed to 5% of pages does not give much
benefit in reducing performance penalty.
Results shows that a 35.63-38.87% additional
energy can be saved by complementing existing
power management techniques with this
technique.
10. 2. PHASE CHANGE MEMORY (PCM)
•
Phase change memory is a type of non-volatile random access memory and provides a non-volatile
storage mechanism agreeable to process scaling.
•
However, for a DRAM alternative, we must architect PCM for feasibility in main memory within
general-purpose systems.
•
Drawn from a rigorous survey of PCM device and circuit prototypes published within the last five
years and comparing against modern DRAM memory subsystems, we examine the following: Buffer
Organization and Partial Writes.
11. 2.1 BUFFER ORGANIZATION
•
We examine PCM buffer organizations that satisfy DRAM imposed area constraints.
•
PCM buffer reorganizations reduce application execution time from 1.6x to 1.2x and memory energy
from 2.2x to 1.0x, relative to DRAM-based systems.
Evaluation:
On optimizing average delay and energy across the workloads, we find four 512B-wide buffers most
effective. Executing on effectively buffered PCM, more than half the benchmarks achieve within 5
percent of their DRAM performance. Although each PCM array write requires 43.1x more energy than a
DRAM array write, these energy costs are mitigated by narrow buffer widths and additional rows, which
reduce the granularity of buffer evictions and expose opportunities for write coalescing, respectively.
12. 2.2 PARTIAL WRITES
•
Partial writes, which track data modifications and write only modified cache lines or words to the PCM
array are utilized. Using an endurance model to estimate lifetime, we expect write coalescing and
partial writes to deliver a memory module average lifetime of 5.6 years.
•
Scaling improves PCM endurance, extending lifetimes by four orders of magnitude at 32nm.
Evaluation:
•
In a baseline architecture with a single 2048B-wide buffer, average module lifetime is approximately
525 hours.
•
For our memory intensive workloads, we observe 32.8 percent memory bus utilization. Scaling by
application-specific write intensity, we find 6.9 percent of memory bus cycles are utilized by writes.
•
On average, the four 512B-wide buffers coalesce 38.9 percent of writes emerging from the memory
bus, which is 47.0 percent utilized. Writes alone utilize 11.0 percent of the bus. Buffers use partial
writes so that only a fraction of the buffer’s bits is written to the array.
•
13. PHASE CHANGE MEMORY (PCM)
•
Collectively, these results indicate PCM is a viable DRAM alternative, with architectural solutions
providing competitive performance, comparable energy, and feasible lifetimes.
•
On utilizing PCM as a viable alternative to M-RAM, we need to note that it consumes more energy to
perform I/O operations, particularly write operations, since the cell state has to be changed.
•
However, PCM consumes significantly less idle power than M-RAM, especially in the low-power state
where the power consumption is reduced to 0. Therefore, we should leverage the tradeoffs between
performance and energy efficiency to apply PCM technology in mobile devices.
14. 3. CHARACTERIZING MOBILE SOFTWARE
The applications selected for this survey are shown in the table
This table lists 12 popular Android applications selected from the Android market along with their trace
statistics. We is e a T-Mobile G1 smartphone is used to collect the application traces. Each trace consists of
task intervals with the task execution length and the number of memory I/Os
15. 3. CHARACTERIZING MOBILE SOFTWARE
•
Compared to the CPU speed, human interactions are extremely slow, such that a mobile system is idle and waiting
for user input for the majority of time.
•
Prior study has shown that human perception threshold is between 50ms and 100ms and any event shorter than the
perception threshold appears instantaneous to the user.
•
Completing task execution earlier than the perception threshold is meaningless since the user will not notice this
amount of time and cannot initiate new tasks any sooner. This observation is the key to enabling energy
optimizations without impacting observed application performance
•
The majority of tasks are very short as more than 90% of all tasks complete within 10ms. Moreover, 95% of all
tasks are shorter than 50ms, indicating that these tasks can be extended to the 50ms perception threshold deadline
without any performance penalty. Similarly, for the remaining 5% of long tasks, any additional extension less than
50ms will not be noticed by the user, avoiding performance degradation.
16. 4. MECHANISM COMPARISON
•
M-RAM needs to refresh the storage cells regularly for data retention, therefore consuming nonnegligible power even in the low-power state. PCM is able to completely eliminate idle power due to
non-volatile nature. We will evaluate the effectiveness of various energy management mechanisms on
M-RAM and PCM under the same execution environment.
•
For this survey, a simulator that models the system configuration of a T-Mobile G1 smartphone is used
System Configuration of a T-Mobile G1
•
The memory subsystem consists of a memory controller and three 64MB ranks (192MB totally), for
either M-RAM or PCM. The simulator feeds with the traces, determines the memory power state, and
conducts task execution under the current CPU and memory state. The memory controller conducts
memory I/O operations, and executes power state transitions for each rank based on the energy
management mechanism
17. 4.1 POWER AWARE VIRTUAL MEMORY (PAVM)
•
In mobile applications when the smartphone is waiting for user input, idle periods are common and
therefore powering down the memory devices during this period can help in reducing the energy
consumption.
•
Power-Aware Virtual Memory (PAVM) is a simple and efficient way to provide energy management. It
keeps the memory devices occupied by the currently running process in the active state while keeping
all other memory devices in a low-power state to save energy. Memory devices used by the newly
scheduled process are powered up during the context switch time to minimize the delays exposed to the
user due to power state transitions.
Memory energy consumption
with a standard system (ON) and
the PAVM mechanism. The left
two bars for each application
show the energy of M-RAM and
PCM in standard system, while
the right two bars show the
energy for the PAVM mechanism.
18. 5. ON-DEMAND MECHANISMS
•
Despite PAVM’s benefits to the standard system, it fails to address the energy efficiency of the active
rank accessed during the process execution.
•
Immediate Power Down (IPD) mechanism and Immediate Self Refresh (ISR) mechanism have been
proposed for RAM to provide on-demand power state transitions and improve energy efficiency of
active ranks.
•
As soon as an I/O request arrives at the memory controller, the rank to be accessed is transitioned to the
PRE state, and transitioned back to a low-power immediately after the I/O completes. Each energy bar
is normalized to M-RAM with the PAVM mechanism.
19. 5. ON-DEMAND MECHANISMS
Memory energy consumption for
on-demand mechanisms
normalized to the PAVM
mechanism on M-RAM
•
The first bar shows the energy consumption of PCM with the PAVM mechanism and the other bars show the energy
of on-demand mechanisms.
•
The two on-demand mechanisms outperform the PAVM mechanism on PCM and as a result, PCM’s inferior I/O
efficiency can’t offset its energy savings from idle periods, except for lightly loaded applications Amazon, Music
and Twidroid.
•
The PCM OFF mechanism completely eliminates the active idle energy, resulting in 44% energy reduction over the
PAVM mechanism on PCM. Compared to the IPD and ISR mechanisms on M-RAM, the PCM OFF mechanism
offers 18% and 22% energy savings respectively.
20. 5. ON-DEMAND MECHANISMS
The distribution of extended tasks
that expose delays for on-demand
mechanisms
• We can observe that the IPD mechanism achieves the best performance with negligible delays exposed.
The ISR and PCM OFF mechanisms, on the other hand, incur more evident degradation due to the
141.5ns long transition latency
• energy is the only concern, the novel PCM technology with on-demand mechanism surpasses the
traditional MRAM. However, taking into account the performance as well, M-RAM still has the chance
to beat PCM,
• We therefore need an approach to balance energy and performance more efficiently than any standalone
memory technology.
21. 6. HYBRID MEMORY ARCHITECTURE
•
From the previous analysis, we can see that PCM is superior to M-RAM for its lower idle power
consumption, while M-RAM excels PCM for faster I/O speed and lower I/O energy. Therefore, a
hybrid memory consisting of M-RAM and PCM can improve both the energy efficiency and
performance.
•
When an application is invoked and its image does not reside in M-RAM, it is loaded into M-RAM
either from secondary storage or PCM, and the corresponding process identifier is put at the head of the
LRU list.
•
When an application is closed, its memory image will stay in M-RAM until it is swapped out.
•
The hybrid approach preserves more than 99% of IPD’s performance and achieves the best energy
efficiency among all mechanisms while maintaining almost full memory performance.
22. CONCLUSIONS
•
The PAVM mechanism saves more than 90% energy as compared to the standard system with no
energy management.
•
Additional energy savings are provided by the on-demand mechanisms which offer around 40% more
savings compared to the PAVM mechanism, for both M-RAM and PCM.
•
The energy efficiency can be improved further by a hybrid approach consisting of mixed memory
technologies and mechanisms and this approach provides an energy savings of 98% with negligible
performance overheads as compared to the standard system.
Editor's Notes
As smartphones are becoming widely used and an indispensable part of our lives, limiting their energy consumption is critical. With battery technology improving at a much slower pace than hardware technology thereby making the gap between energy supply and demand increasingly larger, energy efficiency has become one of the most important factors in designing smartphones.