BY VIEWING THIS SLIDES YOU ABLE TO KNOW -WHAT IS EMBEDDED SYSTEM? -WHAT ARE PROS AND CONS OF EMBEDDED SYSTEM? -WHERE IT IS USED? -WHAT IS FGPA,MICROPROCESSOR,CRYPTOGRAPHY,JTAG,SPI, SERIAL AND PARALLEL COMMUNICATION? AND MUCH MORE.

1. EMBEDDED SYSTEM BASICS
POWERED BY
RANA ALI

2. Interface Analog voltage
• Interfacing ACS 712 current sensor
• Measuring current and give voltage output

3. ACS712 relation between Current on
Output voltage

4. Driving ACS 712 formula
Input current Output voltage ADC value
-30 A 0 V 0
0 A 2.5 V 512
+30 A 5 V 1023
Y = MX + B
And
M = (y2-y1) / (x2 – x1)
M = ( 1023 – 0 ) / (30 – (-30))
M = 1023 / 60
M = 17.05
Y = MX + B
Y = 17.05X + 512
X = (Y – 512) / 17.05

5. FPGA block diagram

6. Logic Block

7. Logic flow in FPGA

8. FPGA ASIC difference

9. FPGA Application

10. Difference between Microprocessor
and FPGA

11. cryptography

12. How cryptography work

13. Network application

14. FPGA SoC

15. FPGA SoC
Assignment: Write difference between the
following
• Hardcore FPGA
• Softcore FPGA

16. Protocol
• UART
• JTAG
• I2C
• SPI
• CAN

17. Serial vs Parallel Communication

18. Serial vs Parallel Communication

19. UART

20. UART vs USART

21. UART Working

22. Serial Communication in Arduino UNO
and Mega

23. Data Transmission Type
• (a) Simplex
• (b) Half Duplex
• (c) Full Duplex

24. RS232 UART

25. UART GSM Interface

26. UART GPS Interface

27. JTAG
• JTAG is a Testing protocol
• It use to design and test board after
manufacturing
• It is on-chip instrument for digital Simulation
Joint Test Action Group

28. JTAG Pins
Daisy-chained JTAG (IEEE 1149.1)
The connector pins are
• TDI (Test Data In)
• TDO (Test Data Out)
• TCK (Test Clock)
• TMS (Test Mode Select)
• TRST (Test Reset) optional.
• Test reset signal is not shown in the image.

29. JTAG
Daisy-chained JTAG

30. JTAG Application

31. JTAG AVR

32. JTAG FPGA

33. JTAG Mobile Phone

34. I2C Protocol
• I²C (Inter-Integrated Circuit) design by Phllips
• It is typically used for attaching lower-speed
peripheral ICs to processors
and microcontrollers in short-distance, intra-
board communication
• Some other vendor use same protocol by name
TWI (Two Wire Interface) or TWSI (Two-Wire
Serial Interface)

35. I2C Protocol
• I²C uses only two bidirectional open-
drain lines, Serial Data Line (SDA) and Serial
Clock Line (SCL), pulled up with resistors.
Typical voltages used are +5 V or +3.3 V
• It has adress space of 7-bit mean it interface
128 devices
• I²C bus speeds are the 100 kbit/s

36. I2C Interface

37. I2C Working

38. I2C in Arduino

39. I2C devices

40. SPI
(Serial Peripheral Interface)
• The Serial Peripheral Interface bus (SPI) is a
synchronous serial communication interface
specification used for short distance
communication.
• SPI devices communicate in full duplex mode.
• The interface was developed by Motorola.
• Typical applications include Secure Digital cards
and LCD.

41. SPI working
The SPI bus specifies five logic signals:
SCLK: Serial Clock (output from master)
MOSI: Master Output Slave Input, or
Master Out Slave In
(data output from master).
MISO: Master Input Slave Output, or
Master In Slave Out
(data output from slave).
SS: Slave Select
(often active low, output from master).

43. SPI Animation

44. Independent slave configuration
• In the independent
slave configuration,
there is an
independent chip
select line for each
slave

45. Daisy chain configuration
• Only 4 wires are
user to interface
many device
• Sometime use in
place of JTAG

46. SPI Application
• Sensors: temperature, pressure, ADC, touch
screens, video game controllers
• Control devices: audio codecs, digital
potentiometers, DAC
• Camera lenses: Canon EF lens mount
• Communications: Ethernet
• Memory: flash and EEPROM
• Real-time clocks
• LCD, sometimes even for managing image data
• Any MMC or SD card (including SDIO variant[5])

47. SPI Example
• SCP1000 Barometric Pressure sensor

48. SPI Arduino

49. CAN Bus
• Controller Area Network (CAN bus)
• It is a vehicle bus standard designed to allow
microcontrollers and devices to communicate
with each other in applications without a host
computer

50. CAN
• The modern automobile may have as many as 70
Electronic Control Units (ECU)
• Typically the biggest processor is the Engine Control
Unit.
• Some of these form independent subsystems, but
communications among others are essential.
Transmission electric power steering
airbags audio systems
antilock power windows
Braking/ABS doors
cruise control mirror adjustment
battery and recharging systems for hybrid/electric cars

51. CAN Bus

52. Before CAN Bus: Multi-wire Bus
•Electronic/engine Control Module (ECM)
• Body Control Module (BCM)

53. CAN Bus

54. CAN Device

55. CAN Bus Architecture

56. CAN Bus Application

57. CAN Bus Application

58. Comparing UART, I2C and SPI
• Data Transmission Type
Simplex, Half Duplex and Full Duplex
• Synchronous or Asynchronous
• Master/Slave or Independent
• Applications

59. Verilog Design Methodologies
Top-down Design Methodology
Bottom-up Design Methodology

60. Verilog Modules
A module is the basic building block in Verilog
Module Syntax
module <module_name> (<module_terminal_list>);
...
<module internals>
...
...
endmodule

61. Bottom-up Design Methodology
Example
d Clk Q
0 0 Q0
0 1 0
1 0 Q0
1 1 1

62. Bottom-up Design Methodology
Example

63. Bottom-up Design Methodology
Example

64. Verilog Simulation
Simulink programming
a = 0;
b = 0;
#100; //delay of 100 unit time
a = 0;
b = 1;
#100; //delay of 100 unit time
a = 1;
b = 0;
#100; //delay of 100 unit time
a = 1;
b = 1;
#100; //delay of 100 unit time

65. Verilog FPGA
Verilog is both a behavioral and a structural
Model(Switch level, Gate level and Dataflow ).
Internals of each module can be defined at four
levels of abstraction, depending on the needs of
the design
• Behavioral or algorithmic level
• Dataflow level
• Gate level
• Switch level

66. Switch level Modeling
Design using nmos and pmos logics
• pmos (out,data,control);
• cmos (w, datain, ncontrol, pcontrol);
• nmos (w, datain, ncontrol);
• pmos (w, datain, pcontrol);

67. Gate level Modeling
• Gates provide a much closer one to one mapping
between the actual circuit and the network
model
• Use in Small circuit design
• The and/or gates available in Verilog are shown
below.
and or xor nand nor xnor
• and a1(OUT, IN1, IN2);
• nand na1(OUT, IN1, IN2);
• or or1(OUT, IN1, IN2);
• nor nor1(OUT, IN1, IN2);

68. Dataflow Modeling
• assign out = in1 & in2;
• assign #10 out = in1 & in2;
// Delay in a continuous assign

69. Behavioral Modeling
• Design at this level resembles C programming more
than it resembles digital circuit design.
module clock_gen (output reg clock);
Initial //Initialize clock at time zero
clock = 1'b0;
always
#10 clock = ~clock; //Toggle clock every half-cycle
//time period = 20
initial
#1000 $finish; //Finish at 1000 unit clock
endmodule

71. Behavioral Modeling
• initial : initial blocks execute only once at time
zero (start execution at time zero).
• always : always blocks loop to execute over and
over again; in other words, as the name suggests,
it executes always.
module initial_example();
reg clk,reset,enable,data;
initial
begin
clk = 0;
reset = 0;
enable = 0;
data = 0;
end
endmodule
module always_example();
reg clk,reset,enable,q_in,data;
always @ (posedge clk)
if (reset)
begin
data <= 0;
end
else if (enable)
begin
data <= q_in;
end
endmodule

72. Blocking vs. Non-blocking
Assignments

73. Blocking vs. Non-blocking
Assignments

74. Blocking vs. Non-blocking
Assignments Example

75. Blocking vs. Non-blocking
Assignments Example