1. Introduction The exponential growth of semiconductor technology has led to highly complex integrated circuits (ICs) with billions of transistors. While the ability to fabricate such advanced chips is a testament to modern technology, ensuring their correct operation after manufacturing is an equally critical challenge. Manufacturing test principles are applied to detect faults that may occur during the fabrication process, ensuring that only properly functioning chips are delivered to customers. These tests are essential for quality assurance, yield improvement, and customer satisfaction. The primary goal of manufacturing testing is to identify defective chips before they are shipped, ideally with minimal cost and testing time. This paper presents a comprehensive overview of the principles and practices involved in manufacturing testing, including fault models, test strategies, design for testability (DFT), test pattern generation, and emerging trends. 2. Importance of Manufacturing Testing Manufacturing testing plays a vital role in the semiconductor industry due to the following reasons: High Cost of Failure: A single faulty chip can cause failure in critical systems such as medical devices, avionics, or automotive control systems. Complexity of ICs: As device complexity increases, the probability of defects in each chip also rises. High Production Volumes: Millions of chips are fabricated in a single batch, making automated and reliable testing essential. Yield Improvement: Manufacturing testing helps identify recurring fault patterns that can be traced back to process issues. 3. Types of Manufacturing Tests Manufacturing tests are typically classified into various categories depending on the phase of testing and the type of fault targeted. 3.1 Wafer-Level Testing Performed while chips are still on the wafer. Probes are used to make contact with bonding pads. Only basic functional or parametric tests are done. 3.2 Package-Level Testing Conducted after the wafer is diced and chips are packaged. Allows more comprehensive testing due to full electrical access. 3.3 System-Level Testing Performed after the chip is integrated into a board or system. Verifies system-level functionality and performance. 4. Fault Models in Manufacturing Testing Fault models provide a simplified representation of physical defects that may occur in a circuit. They help in generating test patterns and analyzing fault coverage. 4.1 Stuck-at Fault Model Assumes a line is permanently stuck at logic ‘0’ or ‘1’. Simple and widely used for combinational and sequential circuits. 4.2 Bridging Fault Model Assumes that two signal lines are unintentionally connected. Can result in logic conflicts depending on the states of the signals. 4.3 Open Circuit Fault Model A connection is broken, resulting in a floating signal. Difficult to detect, as behavior depends on circuit loading and capacitance. 4.4 Delay Fault Model Faults that affect the timing rather than

1. 06/20/2025
SNS COLLEGE OF TECHNOLOGY
Coimbatore-35
An Autonomous Institution
Accredited by NBA – AICTE and Accredited by NAAC – UGC with ‘A+’ Grade
Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
19ECB302–VLSI DESIGN
III YEAR/ V SEMESTER
UNIT 4 –VLSI TESTING
TOPIC 3: MANUFACTURING TEST PRINCIPLES
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

2. OUTLINE
• Testing
–Logic Verification
–Silicon Debug
–Manufacturing Test
• Fault Models
• Activity
• Observability and Controllability
• Summary
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MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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TESTING-NEEDS
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•Testing is one of the most expensive parts of chips
• Logic verification accounts for > 50% of design effort for
many chips
• Debug time after fabrication has enormous opportunity
cost
• Shipping defective parts can sink a company
Example: Intel FDIV bug
• Logic error not caught until > 1M units shipped
• Recall cost $450M (!!!)
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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LOGIC VERIFICATION
•Does the chip simulate correctly?
• Usually done at HDL level
• Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
•Ex: 32-bit adder
• Test all combinations of corner cases as inputs:
• 0, 1, 2, 231
-1, -1, -231
, a few random numbers
•Good tests require ingenuity
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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Silicon Debug
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•Test the first chips back from fabrication
• If you are lucky, they work the first time
• If not…?????????
•Logic bugs vs. electrical failures
• Most chip failures are logic bugs from inadequate simulation
• Some are electrical failures
• Crosstalk
• Dynamic nodes: leakage, charge sharing
• Ratio failures
• A few are tool or methodology failures (e.g. DRC)
•Fix the bugs and fabricate a corrected chip
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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MANUFACTURING TEST
A speck of dust on a wafer is sufficient to kill chip
Yield of any chip is < 100%
Must test chips after manufacturing before delivery
to customers to only ship good parts
Manufacturing testers are
very expensive
Minimize time on tester
Careful selection of
test vectors
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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TESTING YOUR CHIP
If you don’t have a multimillion dollar tester:
Build a breadboard with LED’s and switches
Hook up a logic analyzer and pattern generator Or use a low-cost functional chip tester
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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TESTOSTERICS
Ex: Testoster ICs functional chip tester
Designed by clinic teams and David Diaz at HMC
Reads your IRSIM test vectors, applies them to your chip, and reports assertion
failures
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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STUCK-AT FAULTS
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How does a chip fail?
Usually failures are shorts between two
conductors or opens in a conductor
This can cause very complicated behavior
A simpler model: Stuck-At
Assume all failures cause nodes to be “stuck-at”
0 or 1, i.e. shorted to GND or VDD
Not quite true, but works well in practice
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

10. 06/20/2025
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STUCK-AT FAULTS-EXAMPLES
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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ACTIVITY
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SHAPE JOINING
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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OBSERVABILITY &
CONTROLLABILITY
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Observability: ease of observing a node by watching external output pins of
the chip
Controllability: ease of forcing a node to 0 or 1 by driving input pins of the
chip
Combinational logic
-observe and control
-Finite state machines –difficult (requiring many cycles
to enter desired state)
if state transition diagram is not known to the test engineer
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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TEST PATTERN GENERATION
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• Manufacturing test ideally would check every node in the
circuit to prove it is not stuck.
• Apply the smallest sequence of test vectors necessary to
prove each node is not stuck.
• Good observability and controllability reduces number of
test vectors required for manufacturing test.
– Reduces the cost of testing
– Motivates design-for-test
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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TEST EXAMPLE
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SA1 SA0
• A3 {0110} {1110}
• A2 {1010} {1110}
• A1 {0100} {0110}
• A0 {0110} {0111}
• n1 {1110} {0110}
• n2 {0110} {0100}
• n3 {0101} {0110}
• Y {0110} {1110}
• Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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FABRICATION
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Think about testing from the beginning
Simulate as you go
Plan for test after fabrication
“If you don’t test it, it won’t work!
(Guaranteed)”
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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ASSESSMENT
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1. How can you test the Loaded materials weight in lorry
Say with examples
2. Struck at fault 0 vs 1
3. List out the Testing Needs?
4. Any other Examples of Testing
5. Differentiate Observability & controllability
MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT

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SUMMARY & THANK YOU
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MANUFACTURING TEST PRINCIPLESS//19ECB302-VLSI DESIGN/J.Prabakaran/Assistant Professor/ECE/SNSCT