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ECWAY TECHNOLOGIES 
ECWAY TECHNOLOGIES 
2014-15 IEEE Software | Embedded | Mechanical Projects Development 
IEEE PROJECTS & SOFTWARE DEVELOPMENTS 
OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE 
BANGALORE / HYDRABAD 
CELL: 9894917187 | 875487 1111/2222/3333 | 8754872111 / 3111 / 4111 / 5111 / 6111 
Visit: www.ecwayprojects.com Mail to: ecwaytechnologies@gmail.com 
IEEE 2014 VLSI TITLES 
BE, B.TECH PROJECTS INSTITUTE COST ONLY 
[ME, MTECH DEVELOPING EXTRA CHARGES] 
2014 VLSI PROJECT TITLES DOMAIN 
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained 
Random Verification 
VLSI 
A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High 
Throughput VLSI Implementation 
VLSI 
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA 
Resistant Circuits 
VLSI 
A Multicast Tree Router for Multichip Neuromorphic Systems VLSI 
Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for 
VLSI 
Memory-Dominated Wireless Communication Systems 
An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder 
Implementation 
VLSI 
An Event-Based Neural Network Architecture With an Asynchronous Programmable 
Synaptic Memory 
VLSI 
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply 
Operator 
VLSI 
Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design VLSI 
Constructing Sub-Arrays with Short Interconnects from Degradable VLSI Arrays VLSI 
OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE /BANGALORE / HYDRABAD 
CELL: +91 98949 17187 | +91 875487 1111 / 2222 / 3333 | +91 875487 2111 / 3111 / 4111 / 5111 / 6111
ECWAY TECHNOLOGIES 
2014-15 IEEE Software | Embedded | Mechanical Projects Development 
Design and Analysis of Approximate Compressors for Multiplication VLSI 
Design of an NoC Interface Macrocell with Hardware Support of Advanced Networking 
VLSI 
Functionalities 
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under 
Process Variations 
VLSI 
Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set 
Computing (RISC) Microprocessor 
VLSI 
Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems VLSI 
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation 
VLSI 
Function 
Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity VLSI 
Finite Alphabet Iterative Decoders for LDPC Codes Optimization, Architecture and 
VLSI 
Analysis 
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM 
VLSI Architecture 
VLSI 
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State 
Drives 
VLSI 
Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 
14 Additions 
VLSI 
Iterative Linear Interpolation Based on Fuzzy Gradient Model for Low-Cost VLSI 
Implementation 
VLSI 
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through VLSI 
Multifunction Residue Architectures for Cryptography VLSI 
Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches VLSI 
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions VLSI 
Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial 
VLSI 
Interpolation Methods 
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for 
Efficient Digital Signal Processing 
VLSI 
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority VLSI 
Recursive Approach to the Design of a Parallel Self-Timed Adder VLSI 
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error- 
VLSI 
Floor 
Regaining Trust in VLSI Design Design-for-Trust Techniques VLSI 
OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE /BANGALORE / HYDRABAD 
CELL: +91 98949 17187 | +91 875487 1111 / 2222 / 3333 | +91 875487 2111 / 3111 / 4111 / 5111 / 6111
ECWAY TECHNOLOGIES 
2014-15 IEEE Software | Embedded | Mechanical Projects Development 
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block VLSI 
Reverse Converter Design via Parallel-Prefix Adders Novel Components, 
VLSI 
Methodology,and Implementations 
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs VLSI 
Switching Noise Improvement of a Limit-Cycle Amplifier Using a Negative Hysteresis 
VLSI 
Relay 
Toward Multi-Gigabit Wireless Design of High-Throughput MIMO Detectors With 
Hardware-Efficient Architecture 
VLSI 
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief 
Propagation 
VLSI 
…..connecting you to the power of IT 
OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE /BANGALORE / HYDRABAD 
CELL: +91 98949 17187 | +91 875487 1111 / 2222 / 3333 | +91 875487 2111 / 3111 / 4111 / 5111 / 6111

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2014 ieee vlsi project titles

  • 1. ECWAY TECHNOLOGIES ECWAY TECHNOLOGIES 2014-15 IEEE Software | Embedded | Mechanical Projects Development IEEE PROJECTS & SOFTWARE DEVELOPMENTS OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE BANGALORE / HYDRABAD CELL: 9894917187 | 875487 1111/2222/3333 | 8754872111 / 3111 / 4111 / 5111 / 6111 Visit: www.ecwayprojects.com Mail to: ecwaytechnologies@gmail.com IEEE 2014 VLSI TITLES BE, B.TECH PROJECTS INSTITUTE COST ONLY [ME, MTECH DEVELOPING EXTRA CHARGES] 2014 VLSI PROJECT TITLES DOMAIN A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification VLSI A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation VLSI A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits VLSI A Multicast Tree Router for Multichip Neuromorphic Systems VLSI Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for VLSI Memory-Dominated Wireless Communication Systems An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation VLSI An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory VLSI An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator VLSI Compact MOSFET Modeling for Process Variability-Aware VLSI Circuit Design VLSI Constructing Sub-Arrays with Short Interconnects from Degradable VLSI Arrays VLSI OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE /BANGALORE / HYDRABAD CELL: +91 98949 17187 | +91 875487 1111 / 2222 / 3333 | +91 875487 2111 / 3111 / 4111 / 5111 / 6111
  • 2. ECWAY TECHNOLOGIES 2014-15 IEEE Software | Embedded | Mechanical Projects Development Design and Analysis of Approximate Compressors for Multiplication VLSI Design of an NoC Interface Macrocell with Hardware Support of Advanced Networking VLSI Functionalities Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations VLSI Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor VLSI Efficient Parallel Turbo-Decoding for High-Throughput Wireless Systems VLSI Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation VLSI Function Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity VLSI Finite Alphabet Iterative Decoders for LDPC Codes Optimization, Architecture and VLSI Analysis High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture VLSI High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives VLSI Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions VLSI Iterative Linear Interpolation Based on Fuzzy Gradient Model for Low-Cost VLSI Implementation VLSI Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through VLSI Multifunction Residue Architectures for Cryptography VLSI Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches VLSI On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions VLSI Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial VLSI Interpolation Methods Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing VLSI Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority VLSI Recursive Approach to the Design of a Parallel Self-Timed Adder VLSI Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error- VLSI Floor Regaining Trust in VLSI Design Design-for-Trust Techniques VLSI OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE /BANGALORE / HYDRABAD CELL: +91 98949 17187 | +91 875487 1111 / 2222 / 3333 | +91 875487 2111 / 3111 / 4111 / 5111 / 6111
  • 3. ECWAY TECHNOLOGIES 2014-15 IEEE Software | Embedded | Mechanical Projects Development Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block VLSI Reverse Converter Design via Parallel-Prefix Adders Novel Components, VLSI Methodology,and Implementations Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs VLSI Switching Noise Improvement of a Limit-Cycle Amplifier Using a Negative Hysteresis VLSI Relay Toward Multi-Gigabit Wireless Design of High-Throughput MIMO Detectors With Hardware-Efficient Architecture VLSI VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation VLSI …..connecting you to the power of IT OUR OFFICES @ CHENNAI / TRICHY / KARUR / ERODE / MADURAI / SALEM / COIMBATORE /BANGALORE / HYDRABAD CELL: +91 98949 17187 | +91 875487 1111 / 2222 / 3333 | +91 875487 2111 / 3111 / 4111 / 5111 / 6111