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ゆるふわコンピュータ (IPSJ-ONE2017)

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ゆるふわコンピュータ (IPSJ-ONE2017)

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ゆるふわコンピュータ ((2017年情報処理学会全国大会IPSJ-ONE2017)

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  1. 1. Twitter/GitHub: @shtaxxx IPSJ-ONE 2017
  2. 2. Twitter/GitHub: @shtaxxx IPSJ-ONE 2017
  3. 3. J
  4. 4. Intel Intel Core i7 #include <stdio.h> int main(){ printf("Hello!¥n"); return 0; }
  5. 5. FPGA
  6. 6. [1] Agile Co-Design for a Reconfigurable Datacenter, FPGA'16
  7. 7. Digilent PYNQ-Z1 Python $229 (Academic $65)
  8. 8. ScalableCore System (Xilinx Spartan-6 128) CPU 100
  9. 9. L
  10. 10. int main(){ return 0; } J
  11. 11. J
  12. 12. conv1_input_enable:1 delay R conv1_input_act_0_0:8 * L conv1_input_wgt_0_0:8 R conv1_input_act_0_1:8 * L conv1_input_wgt_0_1:8 R conv1_input_act_0_2:8 * L conv1_input_wgt_0_2:8 R conv1_input_act_1_0:8 * L conv1_input_wgt_1_0:8 R conv1_input_act_1_1:8 * L conv1_input_wgt_1_1:8 R conv1_input_act_1_2:8 * L conv1_input_wgt_1_2:8 R conv1_input_act_2_0:8 * L conv1_input_wgt_2_0:8 R conv1_input_act_2_1:8 * L conv1_input_wgt_2_1:8 R conv1_input_act_2_2:8 * L conv1_input_wgt_2_2:8 R delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R + L R delay R + L R delay R + L R delayR delay R + L R + L R + L R delay R + L R delay R delay R + L R delay R < L delayR delay R Cond 0 2 conv1_act_output_valid:1 conv1_act_output:8 0 R 0 1
  13. 13. Intel Intel Core i7 #include <stdio.h> int main(){ printf("Hello!¥n"); return 0; } FPGA

Description

ゆるふわコンピュータ ((2017年情報処理学会全国大会IPSJ-ONE2017)

Transcript

  1. 1. Twitter/GitHub: @shtaxxx IPSJ-ONE 2017
  2. 2. Twitter/GitHub: @shtaxxx IPSJ-ONE 2017
  3. 3. J
  4. 4. Intel Intel Core i7 #include <stdio.h> int main(){ printf("Hello!¥n"); return 0; }
  5. 5. FPGA
  6. 6. [1] Agile Co-Design for a Reconfigurable Datacenter, FPGA'16
  7. 7. Digilent PYNQ-Z1 Python $229 (Academic $65)
  8. 8. ScalableCore System (Xilinx Spartan-6 128) CPU 100
  9. 9. L
  10. 10. int main(){ return 0; } J
  11. 11. J
  12. 12. conv1_input_enable:1 delay R conv1_input_act_0_0:8 * L conv1_input_wgt_0_0:8 R conv1_input_act_0_1:8 * L conv1_input_wgt_0_1:8 R conv1_input_act_0_2:8 * L conv1_input_wgt_0_2:8 R conv1_input_act_1_0:8 * L conv1_input_wgt_1_0:8 R conv1_input_act_1_1:8 * L conv1_input_wgt_1_1:8 R conv1_input_act_1_2:8 * L conv1_input_wgt_1_2:8 R conv1_input_act_2_0:8 * L conv1_input_wgt_2_0:8 R conv1_input_act_2_1:8 * L conv1_input_wgt_2_1:8 R conv1_input_act_2_2:8 * L conv1_input_wgt_2_2:8 R delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R * * * * * * * * * delay R + L R delay R + L R delay R + L R delayR delay R + L R + L R + L R delay R + L R delay R delay R + L R delay R < L delayR delay R Cond 0 2 conv1_act_output_valid:1 conv1_act_output:8 0 R 0 1
  13. 13. Intel Intel Core i7 #include <stdio.h> int main(){ printf("Hello!¥n"); return 0; } FPGA

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