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Veriloggen.Thread & Stream:
FPGA
(@shtaxxx)
E-mail: takamaeda_at_ist.hokudai.ac.jp
2017 9 24
FPGAX@
BRein Memory[Ando+,VLSI2017]
n A binary/ternary DNN accelerator
l Employing Processing in Memory (PIM) architecture
n 1st ...
n
n
:
3
:
QER(w) = || w – wq ||2
:
L(w) = E(w) + λQER(w)
E(w): , λ:
4
σσ
σσ
σσ
σ
σ
σ
σ
σ
σ
σ
σ
σσ
σσ σσ
σσ
σ
σ
σ
σ
σ
σ
σ
σ
σ
σ
σσ
σσ
σσ
σ
σ
σ
σ
σσ
σσ
σσ
σ
σ
σ
σ
σσ
MajorityVoterCircuit
Inver...
Veriloggen:
Python RTL
5
Design Generator by Python
from veriloggen import *
m = Module('blinkled')
clk = m.Input('CLK')
l...
Verilog
6
Module
Python
(m )Reg
"count <= 0"
"count==1023"
If
(m )Always
Module
Thread, Stream, and RTL together:
Veriloggen Mixed HW
7
Veriloggen.Core (RTL)
Thread
RAM
Thread
RAM
Stream
Stream
Computin...
Thread: Python-to-FSM
LED
8
Module I/O
Verilog
( : CLK, RST, LED )
Thread
Python
I/O
Thread
FSM
RTL
FSM
9
FSM
LED
(th_blink FSM )
RTL
10
RTL
Seq ( )
RTL
( : )
Thread
Python
RTL
Intrinsic function/method:
RTL
11
FSM
send(fsm, value)
data <= value;
enable <= 1;
/* then */
enable <= 0;
wait(fsm)
if(re...
Mutex
12
lock()
Mutex
unlock()
Mutex
Mutex
obj
DMA
13
I/F
RAM: RAM
AXIM: AXI4 IF
AXIS: AXI4 IF
Thread DMA
(Async )
dma_read: read
dma_write: write
Burst Read
Burst Write
: AXI-S
14
AXI4-lite
AXI4-lite
Stream:
15
Stream
ram_a ram_b
ram_c
ACC+
Stream
run()
join()
16
Stream
DMA
n Thread + Intrinsic: I/O
l RTL
n Thread + Stream:
l
l FPGA
n
l
l
17
n GitHub
l Veriloggen: https://github.com/PyHDI/veriloggen
l Pyverilog: https://github.com/PyHDI/Pyverilog
l IPgen: https:...
Thread, Stream, and RTL together:
Veriloggen Mixed HW
19
Veriloggen.Core (RTL)
Thread
RAM
Thread
RAM
Stream
Stream
Computi...
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Veriloggen.Thread & Stream: 最高性能FPGAコンピューティングを 目指したミックスドパラダイム型高位合成 (FPGAX 2017年9月24日@ドワンゴ)

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Veriloggen.Thread & Stream: 最高性能FPGAコンピューティングを
目指したミックスドパラダイム型高位合成 (FPGAX 2017年9月24日@ドワンゴ)

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Veriloggen.Thread & Stream: 最高性能FPGAコンピューティングを 目指したミックスドパラダイム型高位合成 (FPGAX 2017年9月24日@ドワンゴ)

  1. 1. Veriloggen.Thread & Stream: FPGA (@shtaxxx) E-mail: takamaeda_at_ist.hokudai.ac.jp 2017 9 24 FPGAX@
  2. 2. BRein Memory[Ando+,VLSI2017] n A binary/ternary DNN accelerator l Employing Processing in Memory (PIM) architecture n 1st test chip with 6 PIMs l Peak 1.38 TOPS @ 400 MHz, Efficiency 2.3 TOPS/W l First accelerator chip for binary & ternary DNNs 2
  3. 3. n n : 3 : QER(w) = || w – wq ||2 : L(w) = E(w) + λQER(w) E(w): , λ:
  4. 4. 4 σσ σσ σσ σ σ σ σ σ σ σ σ σσ σσ σσ σσ σ σ σ σ σ σ σ σ σ σ σσ σσ σσ σ σ σ σ σσ σσ σσ σ σ σ σ σσ MajorityVoterCircuit Inverter Inverter Inverter Inverter Inverter Inverter σN σS Random pulses (type1&type2) 10bit N S Spin E W h Phase1 Phase2 Phase3 Phase4 Phase1 Phase2 Phase3 Phase4 Coefficient Memory Spin Memory ~ phasecounter Spin Unit phase
  5. 5. Veriloggen: Python RTL 5 Design Generator by Python from veriloggen import * m = Module('blinkled') clk = m.Input('CLK') led = m.Output('LED', 8) count = m.Reg('count', 32) m.Assign( led(count[31:24]) ) m.Always(Posedge(clk)( count( count + 1 ) ) hdl = m.to_verilog() print(hdl) blinkled CLK RST LED count assign always Veriloggen Object module blinkled ( input CLK, output [7:0] LED ); reg [31:0] count; assign LED = count[31:24]; always @(posedge CLK) begin count <= count + 1; end endmodule Verilog Source Code module input CLK input RST blinkled Verilog AST to_verilog() Verilog AST Generator Verilog Code Generator Run on Python Interpreter Verilog HDL Python Verilog HDL
  6. 6. Verilog 6 Module Python (m )Reg "count <= 0" "count==1023" If (m )Always Module
  7. 7. Thread, Stream, and RTL together: Veriloggen Mixed HW 7 Veriloggen.Core (RTL) Thread RAM Thread RAM Stream Stream Computing Unit Thread Python-to-FSM Stream Control Thread Bus + DMA (AXI4 Master/Slave) AXI4 Interconnect DRAMCPU RTL Control Intrinsic RTL RTL Control DMA Control DMA Burst Transfer
  8. 8. Thread: Python-to-FSM LED 8 Module I/O Verilog ( : CLK, RST, LED ) Thread Python I/O Thread FSM
  9. 9. RTL FSM 9 FSM LED (th_blink FSM )
  10. 10. RTL 10 RTL Seq ( ) RTL ( : ) Thread Python RTL
  11. 11. Intrinsic function/method: RTL 11 FSM send(fsm, value) data <= value; enable <= 1; /* then */ enable <= 0; wait(fsm) if(ready) goto next; RTL → Intrinsic function RTL Intrinsic function
  12. 12. Mutex 12 lock() Mutex unlock() Mutex Mutex obj
  13. 13. DMA 13 I/F RAM: RAM AXIM: AXI4 IF AXIS: AXI4 IF Thread DMA (Async ) dma_read: read dma_write: write Burst Read Burst Write
  14. 14. : AXI-S 14 AXI4-lite AXI4-lite
  15. 15. Stream: 15 Stream ram_a ram_b ram_c ACC+ Stream run() join()
  16. 16. 16 Stream DMA
  17. 17. n Thread + Intrinsic: I/O l RTL n Thread + Stream: l l FPGA n l l 17
  18. 18. n GitHub l Veriloggen: https://github.com/PyHDI/veriloggen l Pyverilog: https://github.com/PyHDI/Pyverilog l IPgen: https://github.com/PyHDI/ipgen n PIP Python 18 $ pip install veriloggen $ pip install pyverilog $ pip install ipgen $ git clone https://github.com/PyHDI/veriloggen.git $ git clone https://github.com/PyHDI/Pyverilog.git $ git clone https://github.com/PyHDI/ipgen.git
  19. 19. Thread, Stream, and RTL together: Veriloggen Mixed HW 19 Veriloggen.Core (RTL) Thread RAM Thread RAM Stream Stream Computing Unit Thread Python-to-FSM Stream Control Thread Bus + DMA (AXI4 Master/Slave) AXI4 Interconnect DRAMCPU RTL Control Intrinsic RTL RTL Control DMA Control DMA Burst Transfer

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