ECET 230 Technology levels--snaptutorial.com

ECET 230 Week 1 Homework
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1. Develop the Boolean equation for the circuit shown below
2. Determine the output Y in Problem 1 for the input values shown
below
3. Redraw the circuit in Problem 1 using only 2-input NAND gates
4.Develop the Boolean equation for the circuit shown below
5.Determine the period of a clock waveform whose frequency is:
6.Write the VHDL text file (Entity and Architecture) for a 2-input
NAND gate.
7. Write the VHDL text file for a 3-input NOR gate.
8.Write the VHDL text file for the circuit shown below
9.Develop the look-up-table (LUT) for the circuit shown in Problem 8.
10. Develop the look-up table for the Boolean equation:
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ECET 230 Week 1 iLab Introduction to Quartus
II, VHDL, and the FPGA Board
Objectives:
1.Learn How to write basic logic circuits using VHDL.
2.Using Quartus II compile and simulate the text file and then analyze
the simulation for proper operation.
3.Learn how to assign pins and then how to download the program to the
eSOC II board.
4. Verify that the eSOC II board behaves correctly when the output is
what is expected depending on the input configuration.
Using the results of the compilation for the Design Project, what percent
of the FPGA is used to implement the design.
In the compilation process, what is the difference between an error and a
warning?
Use the zoom tool to measure the propagation delays, tPHL and tPLH,
for the FPGA implementing the Design Project (the times between an
input change of state and the subsequent output change of state in

response). The zoom tool is used by expanding the time scale, right
clicking on one signal and selecting “Insert Time Bar.”
What is “JTAG” and why is it used? Be sure to cite your sources.
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1. When a HIGH is on the output of the decoding circuit below, what is
the binary code appearing on the inputs?
2. Write the Boolean equations for each of the following codes if an
active-LOW decoder output is required:
3. Write the VHDL text file for a 3-to-8 decoder.
4. A 7-segment decoder/driver drives the display below. Using the
waveforms shown, determine the sequence of digits that appear on the
display.
5. Construct a truth table for an active-LOW output BCD (1-of-10)
decoder

6. Derive the truth table for the Y output in the diagram below.
7. Derive the Boolean equation for the Y output in Problem
8.For the multiplexer shown below, determine the output for the
following input state:
9. Determine the function of the circuit shown below.
10. Write the VHDL text file for the circuit shown in Problem 9
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ECET 230 Week 2 iLab Decoders and
Multiplexers
Objectives: Discover the operation of 7-segment displays, BCD-to-7-
semgment decoders, multiplexers and demultiplexers. Demonstrate the
simulation of a discrete DEMUX and decode operation with discrete
components. Construct a discrete circuit with these components. Use
VHDL to emulate this circuit within an FPGA.

Why are the 330 Ω resistors required for the discrete logic circuit, but
not for the MultiSim simulated circuit or the eSOC III circuit?
Create a partial truth table showing the requirements for a seven-
segment decoder to output a hexadecimal digit. This requires four input
bits and six output states, A – F. For each output state, show the
segments a-g. The output states for the inputs 0 – 9 are the same as for
the 74LS47 (see focus.ti.com). Use capital letters A, C, E, F and lower
case for b and d.
Why is the seven-segment display driven with an active-LOW signal
using discrete logic and an active-HIGH with the eSOC board?
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1.Determine the decimal value of each of the following unsigned binary
numbers:

2.Determine the decimal value of each of the following signed binary
number displayed in the 2’s complement form:
3. Determine the outputs (Cout, Sout) of a full-adder for each of the
following inputs:
4.The circuit below is an attempt to build a half-adder. Will the Cout and
Sout function properly? Demonstrate your rationale.
5.Determine the outputs for the circuit shown below. Assume that C0 =
0 for all cases.
6.Write the VHDL text for the 2-bit magnitude comparator shown
below.
7.Write the VHDL text file for a 2-bit full-adder using BIT types.
8.Write the VHDL text file for a 2-bit full-adder using INTEGER types.
9.Develop the VHDL text file for a 4 state, 8-bit arithmetic and logic
unit (ALU). The ALU inputs 2 8-bit numbers (A and B) and output an 8-
bit result (Y) as shown in the table. (2 points).
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ECET 230 Week 3 iLab Flip-Flops in VHDL

Objectives: Simulate an edge-triggered D flip-flop. Test a 74LS74 D
flip-flop and compare against predictions. Describe and simulate edge-
triggered D and J-K flip-flops with VHDL. Test a 74LS112 J-K flip-
flop and compare against predictions.
1. Why is the condition when both and are LOW considered illegal?
2. How does the value you measured for tsetup compare with value
specified in the 74LS74 data sheet? You may need to go on-line to find
this value.
3. Why were the LEDs removed before making the propagation delay
measurements?
4. Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that
the preset (PRE) is synchronous instead of asynchronous. The clear
(CLR) remains asynchronous.
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1. Sketch the Q output for the waveforms shown below applied to an
active-LOW S-R latch. Assume that Q starts LOW.
2. Sketch the Q output for the waveforms shown. Assume that Q starts
LOW.
3. Sketch the Q output for the circuit shown below. Assume that Q starts
LOW.
LOW.
LOW.
LOW.
LOW.
8. Using Quartus II, or an equivalent VHDL entry program, model the D
flip-flop shown below. Attach the simulation file.
9. Using Quartus II, or an equivalent VHDL entry program, model the J-
K flip-flop shown below. Attach the simulation file.
********************************************************

ECET 230 Week 4 iLab Introduction to Flip-
Flops
Objectives: Simulate an edge-triggered D flip-flop. Test a 74LS74 D
flip-flop and compare against predictions. Describe and simulate edge-
triggered D and J-K flip-flops with VHDL. Test a 74LS112 J-K flip-
flop and compare against predictions.
1. Why is the condition when both and are LOW considered illegal?
2. How does the value you measured for tsetup compare with value
specified in the 74LS74 data sheet? You may need to go on-line to find
this value.
3. Why were the LEDs removed before making the propagation delay
measurements?

4. Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that
the preset (PRE) is synchronous instead of asynchronous. The clear
(CLR) remains asynchronous.
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1.Using Quartus II, or an equivalent VHDL entry program, develop the
text file and simulation for the circuit below. Attach the .vhd and
simulation files.
2.What is the output frequency of Q1 in the circuit shown below?
3.A synchronous binary counter is used to divide a 1 MHz input
frequency to 3.90625 kHz. What is the MOD number of the counter and
how many flip-flops are required?
4. If the MOD-8 binary counter is driven by a 10 MHz input clock with
a 5% duty cycle, what is the output frequency and duty cycle of the final
stage?

5.Determine the output frequency for the cascaded counter configuration
shown below.
6.Determine the count sequence for the counter shown below.
7. Write the VHDL text file for a MOD-1024 counter using INTEGER
types
8.Develop the state diagram for a MOD-5 counter with the following
count sequence:
000, 001, 010, 110, 111, 000, etc. All undefined states must return to
000.
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ECET 230 Week 5 iLab Design of Synchronous
Counters
Objectives:
1.To understand the how to design sequential counters using a VHDL
logic design file.

2.To design a basic synchronous up binary counter using the VHDL
Integer type.
3.To be able to use IF…THEN…ELSE statements in the design of non-
binary counters.
4.To design a Gray code counter in a VHDL file and program the eSOC
II board.
Use the simulation run to find the delay time from clock edge to QOUT0
for the up-down counter.
Why is the delay time from the clock edge to any stage of the counter
(QOUT0, QOUT1, ... , QOUT7) the same?
Based on Questions 1 and 2, what is the maximum operating frequency
for this counter?
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1.The group of bits 10110101 is serially shifted (right-most bit first) into
an 8-bit shift register with an initial state of 11100100. After two clock
pulses, the register contains:
(a) 01011110 (b) 10110101 (c) 01111001 (d) 00101101
2. With a 100 kHz clock frequency, eight bits can be serially entered into
a shift register in:
(a) 80 ms (b) 8 ms (c) 80 ms (d) 10 ms
3. For a 10-bit serial-in/serial-out shift register, determine Data out for
the Data in and clock waveforms shown below. Assume that the register
is initially cleared.
4. Using Quartus II, or an equivalent VHDL entry program, develop the
text file and simulation for the shift register specified in Problem 3.
Verify the timing diagram shown in Problem 3. Attach the .vhd and
simulation files.
5.Using Quartus II, or an equivalent VHDL entry program, develop the
text file and simulation for the 74LS194A universal, bi-directional shift
register. Attach the .vhd and simulation files.
6.In your own words, explain the purpose of concatenation in a VHDL
signal assignment.

7. Develop the state diagram for a MOD-4 counter with an even number
count sequence: 000, 010, 100, 110, 000, etc. All undefined states must
return to 000.
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ECET 230 Week 6 iLab Design of a Simple State
Machine
Objectives:
Deisgn a simple state machine.
In Figure 6.3, what is the purpose for the arrows going from S1 to S0
and from S4 to S3? Why are these needed?
What are the advantages of using state variables instead of a series of
IF…THEN…ELSE statement?
Give an example of a finite state machine that can be easily development
using state diagrams and state variables?

Do some research and determine when the state variable method of
design was developed. Be sure to properly cite your sources.
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1. Is the state machine below a Moore machine or a Mealy machine?
Explain your rationale.
3. Using the state diagram in Figure 10.44 on page 663 of the Dueck
textbook, briefly explain the operation of the circuit shown.
4.Create the VHDL text file for the state machine described in Problem
3.
5. Create the Quartus II simulation for the state machine shown in
Problem 3.
6. Using the state diagram in Figure 10.46 on page 665 of the Dueck
textbook, how many state variables are required to implement this state
machine? Why?
7. List the unused states for Problem 6?

8. Create the VHDL text file for the state machine described in Problem
6.
9. Why do we need to specify unused states in the text file in Problem 8?
10. Create the Quartus II simulation for the state machine shown in
Problem 6.
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ECET 230 Week 7 iLab Traffic Light Design
Program
This lab will take a simple three light, two-way intersection as in figure
1.0 and create a working program for it. Based on the timing chart 2.0, I
will create a VHDL file and run a simulation to achieve a basic formula
for how the intersection will work. Then using the eSOC board, I will
create a visual simulation with the exception that I will be controlling
the timing of the light.
ANSWERS TO QUESTIONS

In Figure 6.3, what is the purpose for the arrows going from S1 to S0
and from S4 to S3? Why are these needed?
What are the advantages of using state variables instead of a series of
IF…THEN…ELSE statement?
Give an example of a finite state machine that can be easily development
using state diagrams and state variables?
Do some research and determine when the state variable method of
design was developed. Be sure to properly cite your sources.
********************************************************

ECET 230 Technology levels--snaptutorial.com

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