- Francesco Sgherzi, Computer Science [and Engineering] @Politecnico di Milano and University of Illinois at Chicago - Alberto Parravicini, PhD studenti in Computer Science @Politecnico di Milano Personalized Pagerank (PPR) is a common building block of Recommender Systems. In this setting, the computation of the topmost ranked vertices needs to be executed extremely fast, with low latency and possibly for multiple elements concurrently. In this work, we present a high throughput implementation of the PPR algorithm leveraging a reduced precision-fixed point computation in order to achieve up to 6x speedup and 42x lower energy consumption with respect to a state of the art CPU implementation.

1. Francesco Sgherzi
Alberto Parravicini
Approximate
Personalized PageRank
on FPGA

2. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Approximating Personalized
PageRank (PPR) on FPGA
PPR is a building block of recommender systems
in e-commerce and social networks
● For an input node, find the most similar nodes
● We need real-time results, with
high energy efficiency
2

3. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Approximating Personalized
PageRank (PPR) on FPGA
PPR is a building block of recommender systems
in e-commerce and social networks
● For an input node, find the most similar nodes
● We need real-time results, with
high energy efficiency
No need for 100% accuracy
● The ranking is what matters!
● Use reduced-precision fixed-point arithmetic
for better performance at no accuracy cost
● FPGAs provides high-performance
and energy efficiency
3

4. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Problem Definition
Graphs can be seen as sparse matrices
● E.g. COO format, list of edges/non-zero
matrix entries
4

5. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Problem Definition
Graphs can be seen as sparse matrices
● E.g. COO format, list of edges/non-zero
matrix entries
● The PPR equation becomes a repeated
SpMV (Sparse matrix-vector multiplication)
● The SpMV is the biggest bottleneck
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6. Francesco Sgherzi
Alberto Parravicini
29 July 2020
SpMV Architecture
The heart of our implementation is a
data-flow reduced-precision SpMV core
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● Implemented on a
Xilinx Alveo U200
Accelerator Card
● Use UltraRAM for fast
random accesses
● Use DRAM for burst
sequential reads, at
peak bandwidth

7. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Experimental Setup
We compare against a multi-threaded SoA CPU
and a floating-point FPGA implementations
Test with 8 different real and synthetic graphs
● Between 500K and 2M edges
● Size similar to real community and co-purchasing graphs
Different fixed-point sizes, from 20 to 26 bits
● Lower bit-width gives better clock speed and lower resource usage
CPU: 2x Intel Xeon E5-2680 v2, 384GB RAM
FPGA: Xilinx Alveo U200
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8. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Results - Speedup
Up to 6x speedup w.r.t. CPU and floating-point FPGA
● 42x higher energy efficiency w.r.t. CPU and up to 6x w.r.t. floating point
FPGA
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9. Francesco Sgherzi
Alberto Parravicini
29 July 2020
Results - Ranking
Accuracy of results tested with many metrics
● Num. of errors, NDCG, Precision, Kendall’s 𝜏, ...
● 26 bits provide no accuracy loss
Fixed-point arithmetic provides 2x faster convergence
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10. ● High-Performance FPGA implementation of Approximate PPR
● Use fixed-point data-flow SpMV for maximum throughput
● Up to 6.8x faster than CPU and 42x higher energy efficiency
● No accuracy loss and 2x faster convergence
Thank you!
Approximate Personalized Pagerank on FPGA
Francesco Sgherzi - francesco1.sgherzi@mail.polimi.it
Alberto Parravicini - alberto.parravicini@polimi.it