Serial Digital Interface (SDI), From SD-SDI to 24G-SDI, Part 1

Dr. Mohieddin Moradi
mohieddinmoradi@gmail.com
1
Dream
Idea
Plan
Implementation

UHDTV 1
3840 x 2160
8.3 MPs
Digital Cinema 2K
2048 x 1080 2.21 MPs
4K
4096 x 2160 8.84 MPs
SD (PAL)
720 x 576
0.414MPs
HDTV 720P
1280 x 720
0.922 MPs
HDTV 1920 x 1080
2.027 MPs
UHDTV 2
7680 x 4320
33.18 MPs
8K
8192×4320
35.39 MPs
Wider viewing angle
More immersive
SD, HD, UHD1/4K, UHD2/8K
7

UHD
4K Digital Cinema
UHD Application for Home Delivery
4K Application for Digital Cinema
9

Up to Multi-link 3G-SDI Historical Context
10

Up to Multi-link 3G-SDI Historical Context
2015
6G-SDI
12G-SDI
2017
24G-SDI
11

Up to 12G-SDI Historical Context
12

-
5.0
10.0
15.0
20.0
25.0
30.0
1.5Gb/s
3Gb/s
3Gb/s
12Gb/s
24Gb/s
Gb/s
Belden 1855
52m
Belden 1855
52m
Belden 1855
87m
Belden 1855
46m
Belden 4731R/4731ANH
117m
CANARE L-8CUHD
148m
PERCON VK 90 Silver+
173m
24G-SDI
13

SDI Physical Layer Parameters -Electrical
14

ANSI/SMPTE 259M – It is a standard published by SMPTE which describes a 10-bit serial digital interface operating at 143/270/360 Mb/s. The
goal of SMPTE 259M is to define a serial digital interface (based on a coaxial cable), called SDI or SD-SDI.
ANSI/SMPTE 240M – Signal Parameters – 1125-Line High-Definition Production Systems. Defines the basic characteristics of analog video
signals associated with origination equipment operating in 1125 (1035 active) production systems at 60 Hz and 59.94 Hz field rates.
SMPTE 260M – Digital Representation and Bit-Parallel Interface – 1125/60 High-Definition Production System. Defines the digital representation
of 1125/60 high-definition signal parameters defined in analog form by ANSI/SMPTE 240M.
ANSI/SMPTE 274M – 1920 x 1080 Scanning and Analog and Parallel Digital Interfaces for Multiple Picture Rates. Defines a family of scanning
systems having an active picture area of 1920 pixels by 1080 lines and an aspect ratio of 16:9.
ANSI/SMPTE 292M – Bit-Serial Digital Interface for High-Definition Television Systems. Defines the bit-serial digital coaxial and fiber-optic
interface for high-definition component signals operating at 1.485 Gb/s and 1.485/1.001 Gb/s.
ANSI/SMPTE 295M – 1920x1080 50 Hz – Scanning and Interface
ANSI/SMPTE 296M – 1280 x 720 Scanning, Analog and Digital Representation and Analog Interface. Defines a family of progressive scan
formats having an active picture area of 1280 pixels by 720 lines and an aspect ratio of 16:9.
ANSI/SMPTE 372M – Dual Link 292M. Defines a method for carrying 1080i/p YCbCr formats and RGBA 1080i/p formats in either 10- or 12-bit
formats via two HD-SDI links.
ANSI/SMPTE 424M – 3 Gb/s Signal/Data Serial Interface. Defines a method for transporting 3 Gb/s serial digital signal over a coaxial interface.
ANSI/SMPTE 425M – 3 Gb/s Signal/Data Serial Interface – Source Image Format Mapping. Defines the method of transporting 1920x1080 and
2048x1080 picture formats over a single transport interface of 3 Gb/s.
SMPTE ST 2082 – 12G-SDI Bit-Serial Interfaces
SDI Standards
15

SD-SDI and HD-SDI Interface (Serial Digital Interface)
17

3G-SDI 12G-SDI6G-SDI
SD-SDI and HD-SDI Interface (Serial Digital Interface)
18

Line blanking
(12.05uS)
Y
Pb
&
Pr
0.35V
0.35V
0.7V
0.3V
Active line
(52uS)
Line sync
(4.7uS)
Line 64uS
Back porchFront porch
Analogue Component Signal
20

− Combined Y, R-Y and B-Y signals.
− Professional equipment normally uses a single 75 Ohm BNC connector.
− Consumer and domestic equipment may use a RCA connector.
− RCA connector sometimes called Phono connector.
Analogue Composite Signal
21

Analogue Composite Colour Bar Signal
22

621
308 309 310 311 312 313 314 315 316 317 318 319 320 333 334 335 336 337 338
622 623 624 625 1 2 3 4 5 6 7 8 21 22 23 24 26259
Field 2 Field 1
Field 1 Field 2
Field blanking
Field blanking
20
Y
video
signal
Line number
Y
video
signal
Line number 332321
Horizontal and Vertical Blanking in Analogue Signal
23

Answered the industry’s call for a standard digital video connection
CCIR-601 published in 1982.
– CCIR-601 specified the signal (sampling structure for 525 and 625)
– Simple document, but allowed the industry to standardise.
CCIR-656 published in 1986.
– CCIR-656 specified the interconnection (Serialization process for standard definition signal).
– Both a parallel and a serial transmission format are defined.
– CCIR-601 rewritten.
CCIR-601 & CCIR-656 should be taken together.
– Certain amount of overlap between 601 & 656.
CCIR disbanded in favour of ITU.
– Now called ITU-BT R601.
– Also ratified as SMPTE-259M (SD-SDI Signal).
CCIR Recommendations
24

Pin 1
Pin 25
Pin 13
Pin 14
Clock +
Function
Data 2+
Data 5-
Spare B-
Spare A-
Data 0-
Data 1-
Data 2-
Data 3-
Data 7-
Data 4-
GND
Spare B+
Data 6-
Clock -
Data 0+
Shield/shell
Data 6+
Data 7+
GND 15
25
24
23
22
21
20
19
18
17
Pin
no.
Data 5+
Data 1+
Data 4+
Data 3+
Spare A+
1
Pin
no. Function
2
3
4
5
6
7
8
9
10
11
12
13
14
16
The CCIR 601/656 Connector
25

– Digitised component analogue.
– 4:2:2 sample structure.
– 720 pixels per active line (1440 samples).
– 13.5M pixels per second (27M samples).
– Special sync words.
– Partial commonality between 525 and 625 systems.
– Parallel connector with D25 connector and differential signals.
• CCIR601 cables and connectors were bulky.
• Cables could not be very long.
• Broadcast industry wanted serial digital video.
– Use standard commonly available BNC cables and connectors.
CCIR 601 & CCIR 656 Specifications
26

Parallel in
Serial out
Sync Detector
Sony designed two ground breaking devices, SBX-1601 and SBX-1602.
– SBX-1601 : Parallel to serial converter : Used as transmitter.
Sony SBX 1601 (SDI Encoder), Sony SBX 1602 (SDI Decoder)
27

Parallel out
Serial in
Sony designed two ground breaking devices, SBX-1601 and SBX-1602.
– SBX-1602 : Serial to parallel converter : Used as receiver.
28

– Serial form of CCIR 601 and CCIR 656.
– Full 10 bit resolution.
– 270Mbps stream.
• Uses 4:2:2 sample structure.
– Half the colour samples and black-&-white samples.
• Up to 300 metres connection.
– 280 metres without error.
• Using good quality BNC cables and connectors.
– Sometimes use thinner versions of BNC.
• Component video connection.
– Digital connection keeps the samples separate.
MSW-M2000
29

ANSI/SMPTE 259M (SD-SDI) (or ITU- BT.R 656-4)
– It is a standard published by SMPTE which describes a 10-bit serial digital interface operating at 143/270/360
Mb/s. (8,10-bits)
– The goal of SMPTE 259M is to define a serial digital interface (based on a coaxial cable), called SDI or SD-
SDI.
 SMPTE 125M (or ITU- BT.R 601-5)
– Component Video Signal 4:2:2 – Bit-Parallel Digital Interface
 ITU-R BT.601
– Standard Definition sampling structure for 525 and 625
 ITU-R BT.656
– Serialization process for standard definition signal.
– Interfaces for digital component video signals in 525-line and 625-line television systems operating at the
4:2:2 level of Recommendation ITU-R BT.601 (Part A)
ANSI: American National Standards Institute
SMPTE: Society of Motion Picture & Television Engineers
SDI Standards
30

21
24
1
22
23
310
311
313
335
336
623
624
625
2
309
312
334
337
622
314
Field 2
Field 1
SDI
Horizontal and Vertical Blanking in Digital SD-SDI Signal
31

Review of SD-SDI Encoder
4:2:2 Sampling Serialized
35

Review of SD-SDI Encoder
Parallel To Serial Conversion
36

Luma and Chroma Video Components
38

− A number of other color-difference formats are in use for various applications.
− In particular it is important to know that the coefficients currently in use for
composite PAL, SECAM, and NTSC encoding are different, as shown in Table.
Component Color Difference
39

− The RGB signals in the camera are gamma-corrected with the inverse function of the CRT.
− Gamma corrected signals are denoted R', G', and B'; the prime mark (') indicating a
correction factor has been applied to compensate for the transfer characteristics of the
pickup and display devices.
Gamma Correction
40

Conversion of R'G'B' into Luma and Color-Difference
(Bandwidth-Efficient Method)
41

− The luma signal has a dynamic range of 0 to 700 mv.
− The color-difference signals, R'-Y' and B'-Y', may have different dynamic ranges
dependent on the scaling factors for conversion to various component formats.
Conversion of R'G'B' into Luma and Color-Difference
42

Routers
Switchers
Storage Equipment
Cameras
Monitors
Editing equipment
R', G', B' Conversion to Y',P'b,P'r
43

− The analog component format denoted by Y'P'bP'r is scaled so that both color-difference
values have a dynamic range of ±350 mv.
− This allows for simpler processing of the video signals.
Y', (R'-Y'), (B'-Y') Conversion to Y',P'b ,P'r
44

− Analog Y'P'bP'r values are offset to produce Y'C'bC'r values typically used within the
digital standards.
− The resulting video components are a Y’ or luma channel similar to a monochrome video
signal, and two color-difference channels, C'b and C'r that convey chroma information
with no brightness information, all suitably scaled for quantization into digital data.
Y', P'b, P'r Conversion to Y', C'b, C'r
45

Digitizing RGB Camera Signal
47

− A coprocessor is a computer processor used to supplement the functions of the primary processor
(the CPU). A co-processor is used to add timing reference signals, AES/EBU formatted digital audio,
and other ancillary data.
Processing and Serializing the Parallel Data Stream
Error detection code:
CRCC (Cyclic Redundancy Check Code)
48

– At the receiver, energy at half-clock frequency is sensed to apply an appropriate analog equalization to the incoming 270
Mb/s data signal.
– A new 270 MHz clock is recovered from the NRZI signal edges, and the equalized signal is sampled to determine its logic state.
– The deserializer unscrambles the data using an algorithm complimentary to the encoder’s scrambling algorithm and outputs a
10-bit data stream at 27 MB/s.
– The embedded checksum is extracted by the receiver and compared with a new checksum produced from the received data
and any error is reported and an appropriate flag added to the data stream.
SDI Receiver De-Serializes to Parallel
Unscrambles the data
49

– The 10-bit data is then demultiplexed into digital luma and chroma data streams,
converted to analog by three digital-to-analog converters, filtered to reconstruct the
discrete data levels back to smooth analog waveforms, and matrixed back to the original
R'G'B' for display.
Recovering Analog R'G'B' from Parallel Data
50

– ITU-R BT.601 is the sampling standard that evolved out of a joint SMPTE/EBU task force to
determine the parameters for digital component video for the 625/50 and 525/60 television
systems.
– This document specifies the sampling mechanism to be used for both 525 and 625 line signals. It
specifies orthogonal sampling at 13.5 MHz for analog luminance and 6.75 MHz for the two
analog color-difference signals.
– The sample values are digital luma Y' and digital color-difference C'b and C'r, which are scaled
versions of the analog gamma corrected B'-Y' and R'-Y'.
– 13.5 MHz was selected as the sampling frequency because the sub-multiple 2.25 MHz is a
factor common to both the 525 and 625 line systems.
601 Sampling
51

Luminance Quantizing
16: Granular noise effect on color component is avoided.
The decimal value prior to quantization
52

Component Luminance
10-bit Quantizing
53

Color-Difference
The decimal value prior to quantization
55

Video Levels
Digital 10- and 12-bit integer representation (ITU-R BT.2100-1)
Round( x ) = Sign( x ) * Floor( | x | + 0.5 )
Floor( x ) the largest integer less than or equal to x
Resulting values that exceed the
video data range should be
clipped to the video data range
Narrow Range
𝑫 = 𝑹𝒐𝒖𝒏𝒅 [(𝟐𝟏𝟗𝑬′
+ 𝟏𝟔) × 𝟐 𝒏−𝟖
)]
𝑫 = 𝑹𝒐𝒖𝒏𝒅 [(𝟐𝟐𝟒𝑬′ + 𝟏𝟐𝟖) × 𝟐 𝒏−𝟖)]
Full Range
𝑫 = 𝑹𝒐𝒖𝒏𝒅 [(𝟐 𝒏
− 𝟏)𝑬′
]
𝑫 = 𝑹𝒐𝒖𝒏𝒅 [ 𝟐 𝒏 − 𝟏 𝑬′ + 𝟐 𝒏−𝟏)]
Coding 10-bit 12-bit 10-bit 12-bit
Black
(R' = G' = B' = Y' = I = 0)
DR', DG', DB', DY', DI
64 256 0 0
Nominal Peak
(R' = G' = B' = Y' = I = 1)
DR', DG', DB', DY', DI
940 3760 1023 4095
Achromatic
(C'B = C'R = -0.5)
DC'B, DC'R, DCT, DCP
64 256 0 0
Nominal Peak
(C'B = C'R = 0)
512 2048 512 2048
Nominal Peak
(C'B = C'R = +0.5)
960 3840 1023 4095
Video Data Range 4~1019 16~4079(?) 0~1023 0~4095
59

(In NTSC switching window is on line 10 and 273)
PAL and NTSC Vertical Blanking Interval Overview
60

PAL Horizontal Blanking Interval Overview
61

NTSC Horizontal Blanking Interval Overview
62

End of Active Video (EAV) & Start of Active Video (SAV)
63

Header : 3FFh, 000h, 000h
64

EAV SAV
65

Timing Reference Signal (TRS) Codes
66

− The “xyz” word is a 10-bit word with the two least significant bits set to zero
to survive an 8-bit signal path. Contained within the standard definition
“xyz” word are functions F, V, and H, which have the following values:
• Bit 8 – (F-bit): 0 for field one and 1 for field two
• Bit 7 – (V-bit): 1 in vertical blanking interval; 0 during active video lines
• Bit 6 – (H-bit): 1 indicates the EAV sequence; 0 indicates the SAV sequence
67

Notes:
1. The values shown are those recommended for 10–bit interfaces.
2. For compatibility with existing 8–bit interfaces, the values of bits D1 and D0 are not defined. These bits should be set to a fixed value and not left floating.
Protection bits for
SAV and EAV
It provides a double
error detection, single
error correction.
68

Structure of Fourth TRS Word (SAV, EAV)
69

Parallel to Serial Conversion
Non –return to
zero inverted
on one
70

Header : 3FFh, 000h, 000h Header : 3FFh, 000h, 000h
72

Luminance (Y):
Number of luminance samples in each line: 864 (858)
Number of luminance samples in each active line: 720
Number of samples in each horizontal blanking: 144 (138)
R-Y (Cr):
Number of chrominance samples in each line: 432 (429)
Number of chrominance samples in each active line: 360
Number of chrominance samples in horizontal blanking: 72 (69)
B-Y (Cb):
Number of chrominance samples in each line: 432 (429)
Number of chrominance samples in each active line: 360
Number of chrominance samples in horizontal blanking: 72 (69)
Total number of samples in each line:
864+432+432=1728 (in NTSC 1716)
Total number of samples in each active line:
720+360+360=1440
Samples in PAL and NTSC
74

625 Line / 50 Hz
Luminance (Y):
864 samples/line × 625 lines/frame ×25 frames/sec × 10bits/sample = 135Mbit/sec
R-Y (Cr):
432 samples/line × 625 lines/frame × 25 frames/sec × 10 bits/sample = 67.5Mbit/sec
B-Y (Cb):
432 samples/line × 625 lines/frame × 25frames/sec × 10bits/sample = 67.5Mbit/sec
Total Bit Rate
Y + Cr + Cb = 270 Mbit/sec
SD Video Bit Rate (PAL)
75

525 Line / 60 Hz
Luminance(Y):
858 samples/line × 525 lines/frame ×29.97 frames/sec × 10bits/sample = 135Mbit/sec
R-Y(Cr):
429 samples/line × 525 lines/frame × 29.97 frames/sec × 10bits/sample = 67.5Mbit/sec
B-Y(Cb):
429 samples/line × 525 lines/frame × 29.97 frames/sec ×10bits/sample = 67.5Mbit/sec
Total Bit Rate
Y + Cr + Cb = 270 Mbit/sec
SD Video Bit Rate (NTSC)
76

VANC
HANC
Ancillary (ANC) Data Space
78

VANC VANC
HANC
HANC
79

Active Video field 1
frame n
Active Video field 2
frame n
H
A
N
C
S
P
A
C
E
VBI
E
M
B
E
D
D
E
D
A
U
D
I
O
FRAME N
FRAME N
FRAME N+ 1
VBI
VBI
S
A
V
S
A
V
S
A
V
S
A
V
E
A
V
E
A
V
E
A
V
E
A
V
Vert. Switch point
Vert. Switch point
Vert. Switch point
VBI
Vertical
Blanking
Interval
80

− Room for eight AES 2-channel audio data streams
16 audio channels total
• Group 1 = Channels 1&2, 3&4
• Group 4 = Channels 13&14, 15&16
− Room for RP 165 EDH error detection signals
− Room for future data signals
− May be added or stripped by source/destination or external equipment
SDTV - ANC Data Types
81

– In the ideal situation
– The signal transitions align with the clock’s falling edges
– The sampling occurs at the clock’s rising edges
Data Sampling by Clock
83

– Each bit consists of two sections: the first section assumes a value that represents the bit value, and
the second section is always equal to a logical zero.
– In other words, every two symbols carrying information are separated by a redundant zero symbol.
It seems like “AND” operation of NRZ data with a clock having period of Tb
RZ data Encoding
84

“AND” operation in time domain  The convolution in frequency domain
( RZ data spectrum * Periodic square clock spectrum)
BWRZ = 2 * BWNRZ
It has energy at bit rate
but
– In contrast to NRZ data, RZ waveforms exhibit a spectral line at a frequency equal to the
bit rate, thereby simplifying the task of clock recovery.
RZ data Encoding
85

Advantages
 Easy line Failure detection (because its bipolar ) (like NRZ encoding).
 Polarity insensitivity (In NRZ encoding high is a “1” and low is a “0.” It means it has polarity sensitivity).
• For a transmission system its convenient to not require a certain polarity of the signal at the receiver polarity.
• A data transition is used to represent each “1” and there’s no transition for a data “0.” The result’s that it’s only
necessary to detect transitions; this means either polarity of the signal may be used.
 A signal of all “1”s after encoding to NRZI results in a square wave at one-half the clock frequency.
Disadvantage
 NRZI is not a DC–free code.
 If there are many consecutive “0”s, the clock recovery may be impaired; in effect the PLL oscillator
will run “free” for excessively long periods because it has nothing to lock–on to.
NRZI Data Encoding
88

Scrambling = Make Something Nonsense
– Long strings of 0 after encoding to NRZI , can make some problems In clock recovery.
– By scrambling we mix bits to overcome this problems and consequently DC term and Low frequency of signal will removes.
X
1
X4
X9
1
Scrambling
NRZI Coding
Scrambling
89

Descrambling=Make Something Sense
1 X4X9
1
X
(Descrambling)
Descrambling
90

− Scrambling can also produce long runs of 1s or 0s.
− This happens infrequently in video
− It happens occasionally with EAV and SAV which contain 2 or 3 words of all 0s
− It can be encouraged to happen with certain input signals
− Scrambler Concern
− Specific pattern of .1s. and .0s input can create strings of 0s output.
Scrambled NRZI Problem
91

− A Cyclic Redundancy Check (CRC) can be used to provide information to the operator or even sound
an external alarm if the data does not arrive intact.
− Digital monitors may provide both a display of CRC values and an alarm on any CRC errors.
− A unique CRC pair is present in each video line with a separate value for chroma and luma
components in HD, and may be optionally inserted into each field in SD.
− A CRC is calculated and inserted into the data signal for comparison with a newly calculated CRC at
the receiving end.
CRC (Cyclic Redundancy Check) Error Testing
92

The CRC for SD is inserted into the vertical interval, after the switch point.
− SMPTE RP165 defines the optional method for the detection and handling of data errors in SD.
− Full Field and Active Picture data are separately checked and a 16-bit CRC word generated once
per field.
• The Full Field (FF) check covers all data transmitted except in lines reserved for vertical interval
switching (lines 9-11 in 525, or lines 5-7 in 625 line standards).
• The Active Picture (AP) check covers only the active video data words, between but not
including SAV and EAV. Half-lines of active video are not included in the AP check.
The CRC for HD (SMPTE 292M and in SMPTE 425) is inserted following the EAV and line number words
− The CRC checking is performed on a line-by-line basis.
− The user can then monitor the number of errors they have received along the transmission path.
CRC (Cyclic Redundancy Check) Error Testing
93

Quality of an SDI Signal Input
− The quality of a serial digital input is characterized by the following criteria:
− Design and dynamics of the input circuitry (impedance matching, frequency response and phase
linearity)
− Cable equalizer design (equalizing circuit matching cable loss characteristics)
− Robust and jitter resilient clock recovery
− For example doubling the data rate from 1.5 Gbit/s to 3 Gbit/s has increased the difficulty of building
workable equipment and systems:
− For example at 3 Gbit/s, cable losses increase by 40%, connector discontinuities become twice as
significant, the signal bandwidth doubles, the crosstalk potential increases and amplifier gain is
harder to achieve at the higher bandwidth.
96

Measurement in physical domain of the SDI Signal:
– Eye pattern
– Signal level
– Signal ripple
– Low–frequency signal level distortion
– DC offset
– Overshoot
– Rise and fall times
– Impedance
– Return loss
– Jitter.
Measurements in the data domain of SDI Signal:
– Number of active bits (eight or ten)
– Digital signal level
– Check for forbidden digital values
– Timing reference signal (TRS) verification
– Rise and fall times
– Bit–error ratio
– Cyclic redundancy check (CRC)
– Luminance/chrominance delay
– Picture position relative to the TRS
– Ancillary data verification
(including type and length identification)
– Color gamut verification
– Propagation delay in SDI equipment
SDI Signal Measurements
97

I. Jitter testing
II. Out-of-service testing (SDI check field)
III. In-service testing (CRC :Cyclic Redundancy Check)
IV. Eye-pattern testing
V. Cable-length stress testing
Digital System Testing
98

Unit Interval =1/Clock Frequency
Component Digital (SD-SDI)
1UI = 1/270MHz = 3.70 ns
Component Digital (HD-SDI)
1UI = 1/1.485GHz = 0.673 ns
Component Digital (3G-SDI)
1UI = 1/2.97 GHz = 0.336 ns
AES/EBU Digital Audio
1UI = 1/6.144MHz = 163 ns
Unit Interval (UI)
99

SDI signal with sinusoidal edge variation
(ideal positions shown in darker lines).
− Jitter is a significant, undesired issue with any communication link and can be defined as the temporal
deviation from a periodic signal with ideal duty cycle. This is known as Time Interval Error (TIE).
Jitter
Jitter Frequency and Jitter Amplitude
100

– In actual SDI signals, jitter will rarely have the simple sine wave characteristics. The jitter spectrum in
actual SDI signals generally contains a range of spectral components.
– In real systems, a wide variety of factors influence the timing of signal transitions. These different
sources introduce variations over a range of “frequencies and amplitudes”.
– The peak amounts that any particular edge leads or lags its ideal position may differ and there may
be long time intervals between edges with large peak-to-peak variation.
– Jitter waveform: the amount of variation in a signal’s transitions as a function of time-domain
– Jitter spectrum: the frequency-domain representation of the time-domain jitter waveform
– In actual signals, the jitter waveform typically has a complex shape created by the combined effects
of various sources, and the jitter spectrum contains a wide range of spectral components at different
frequencies and amplitudes.
Jitter
Jitter Frequency and Jitter Amplitude
101

– The significant instants are the exact
moments when the transitioning signal
crosses a chosen amplitude threshold, which
may be referred to as the reference level or
decision threshold.
– Phase and amplitude jitter influence digital
systems and can cause bit errors.
Phase Jitter and Amplitude Jitter
102

Random Jitter (RJ) and Deterministic Jitter (DJ)
Deterministic
Jitter (DJ)
Random
Jitter (RJ)
Data Dependent
Jitter (DDJ)
Inter-symbol
Interference (ISI)
Duty Cycle
Distortion (DCD)
Periodic Jitter
PJ or SJ
Data-Correlated Data-Uncorrelated
Total
Jitter (TJ)
Echo jitter
(ECJ)
104

105

Measure jitter spectrum as shown with a Real-Time Scope or TIA and subtract RJ background spectrum
Deterministic
Jitter (DJ)
Random
Jitter (RJ)
Data Dependent
Jitter (DDJ)
Inter-symbol
Interference (ISI)
Duty Cycle
Distortion (DCD)
Periodic
Jitter PJ
or SJ
Total
Jitter (TJ)
Echo jitter
(ECJ)
Bounded Uncorrelated
Jitter (Crosstalk)
108

− The Key to reducing jitter is to reduce deterministic jitter.
− Optimizing deterministic jitter causes the gap between right and left RJ to overlap so that it
can exist as an ideal normal distribution.
109

Random Jitter
− It has essentially no discernable pattern.
− It is best characterized by a Gaussian probability
distribution and statistical properties like mean and
variance.
− Random processes, e.g., thermal or shot noise, introduce
random jitter into an SDI signal.
− We typically use a Gaussian probability distribution to
model this jitter behavior, and we can use the standard
deviation of this distribution (equivalent to the RMS value)
as a measure of the jitter amplitude.
− However, the peak-to-peak jitter amplitude and the RMS
jitter amplitude are not the same.
110

Random Jitter
− In particular, the peak-to-peak amplitude value depends on the observation time.
− On average, we would expect that a peak-to-peak amplitude measurement made over a long
observation time would have a larger value than a peak-to-peak amplitude measurement
made over a short observation time.
− The “tails” of a Gaussian distribution can reach arbitrarily large amplitudes. Hence, by observing
over a sufficiently large time interval, we could theoretically measure arbitrarily large peak-to-
peak jitter amplitude.
− We describe this property by saying that random jitter has “unbounded” peak-to-peak
amplitude.
− Thus, we can say that over any region of interest, random jitter in actual SDI signals has
unbounded peak-to-peak amplitude.
111

Deterministic Jitter
− It is more predictable (determinable) and is often characterized by some definable periodic or
repeatable pattern with a determinable peak-to-peak extent.
− A wide range of sources can introduce deterministic jitter into an SDI signal.
− For example:
• Noise in a switching power supply can introduce periodic deterministic jitter.
• The frequency response of cables or devices can introduce data-dependent jitter that is
correlated to the bit sequence in the SDI signal.
• Differences in the rise and fall times of transition can introduce duty-cycle dependent jitter.
112

− In addition to these general sources of deterministic jitter, SDI signals can contain deterministic
jitter correlated with video properties.
− For example:
• The line and field structure of video data can introduce a periodic deterministic jitter that we will
call raster dependent jitter.
• Converting the 10-bit words used in digital video to and from a serial bit sequence can introduce
high frequency data-dependent jitter at 1/10 the clock rate, typically called word-correlated
jitter.
113

− Deterministic jitter attains some maximum peak-to-peak amplitude within a determinable time
interval.
− Increasing the observation time beyond this time interval will not increase the peak-to-peak
jitter amplitude measurement.
− Unlike random jitter, repeatable deterministic jitter has a determinable upper bound on its peak-
to-peak jitter amplitude.
− Even if deterministic jitter has infrequent long-term determinable behavior, this jitter can be
adequately modeled with a predictable pattern that has bounded peak-to-peak amplitude.
Thus, for all practical purposes, deterministic jitter has bounded peak-to-peak amplitude and
random jitter has unbounded peak-to-peak jitter amplitude.
114

Eye Pattern
Typical Output Voltage Levels
115

Eye Pattern
Typical Output Voltage Levels
116

– Measurement instruments create Eye diagrams by
superimposing short segments of the serial data signal.
– The finite rise and fall times of these transitions create the
characteristic ‘X’ patterns in the Eye diagram.
– Since the data transport stream contains components
that change between high and low at rates of 270 Mb/s
for SD, up to 1.485 Gb/s for some HD formats, the ones
and zeros will be overlaid for display on a video
waveform monitor.
– This is an advantage since we can now see the
cumulative data over many words, to determine any
errors or distortions that might intrude on the eye opening
and make recovery of the data high or low by the
receiver difficult.
Eye Pattern
122

Eye Pattern
− To make the Eye diagram, the instrument aligns the segments using a reference clock
signal.
− Typically this reference clock is extracted from the data signal, but may be a separate
reference clock signal (It can be externally supplied, e.g., through the trigger input on an
oscilloscope, or extracted within the measurement instrument).
− If the transitions in the input signal align with the edges in this reference clock they will lie
on top of each other in the Eye diagram.
− Any transitions that vary from the nominal positions determined by this reference clock will
appear in different locations.
124

Eye Pattern
crossoverpoint
crossoverpoint
crossoverpoint
− The time interval between the crossover points in the Eye equals the unit interval.
− In the ideal case, the decoding process samples the signal at the mid-point between the crossover
points and the decision threshold or decision level corresponds to the widest part of the Eye opening.
125

Eye Pattern
crossover point crossover point
− For signals with a small amount of jitter, the edges in the aligned segments occur in nearly the same
location.
− As the amplitude of the jitter increases, more transitions move into the open space between
crossover points, i.e. the Eye starts to “close”.
− Overally, a signal that forms a large, wide-open Eye is less likely to produce decoding errors than a
signal that forms a small or closed Eye.
126

– Jitter within the SDI signal will change the time when a transition occurs and cause a widening of the
overall transition point.
– This jitter can cause a narrowing or closing of the eye display and make the determination of the
decision threshold more difficult.
Eye Pattern
127

– To extract the digital content from an SDI signal, video equipment samples the SDI signal at the midpoint
of the time intervals containing data bits and converts these sampled levels to the corresponding bit
values.
– To determine whether a sampled signal voltage corresponds to a “high” or “low” signal level, decoders
compare the sampled voltage against a particular voltage level called the decision threshold or decision
level.
– SDI receivers generally use fixed decision thresholds in the decoding process.
– For optimal performance, signal levels must keep the same relative relationship to this fixed voltage level.
– A shift in the signal relative to the decision threshold reduces the noise margin for one of the signal levels,
which can lead to decoding errors.
Eye Pattern
128

− Real SDI signals, have some amount of jitter in their edges.
− Jitter of sufficiently large amplitude will cause sampling errors.
− The impact of incorrect sampling, if jitter is greater than 0.5 UI, is incorrect data.
Decoding Errors
129

– In the decoding process, SDI receivers use
a reference clock to determine when to
sample the input SDI signal.
– Ideally, the transitions in the input SDI
signal occur at appropriate clock edges
and sampling occurs at the midpoint of
the unit interval.
– In the ideal situation, the signal transitions
align with the clock’s falling edges and
sampling occurs at the clock’s rising
edges.
Decoding Errors
• The signal transitions align with the clock’s falling edges
• The sampling occurs at the clock’s rising edges
130

0 1
Sampling Point
BER (Bit Error Rate)
Decoding Errors and Ideal Sampling Position
131

Ideal sampling position
Timing skew of Sampling Position Jitter
Ideal reference point
Voltage offset
Jitter
Decoding Errors and Ideal Sampling Position
132

– To generate the clock waveform we employ
a VCO, and to define its frequency and
phase we phase-lock the VCO to the input
data using a DFF operating as a phase
detector (PD).
– The low-pass filter (LPF) suppresses ripple on
the oscillator control line.
– Also, to retime the data, we add another DFF
that is clocked by the VCO output.
– The recovered clock, CKout, drives the D input
of the phase detector and the clock input of
the retimer. a) The role of a CDR circuit in retiming data
b) An example of CDR implementation.
Clock and Data Recovery (CDR)
Phase Detector (PD)
133

− At Low Frequency Jitter that are below the clock recovery bandwidth → The clock will follow timing
variations in the input signal
Jitter Amplitude
Jitter Tracking in Clock Recovery
SignalTransitions
FallingEdge
SamplingRisingEdge • The signal transitions align with the clock’s falling edges.
• The sampling occurs at the clock’s rising edges.
134

Small Jitter Amplitude
− High Frequency Jitter → The clock can not follow timing variations in the input signal
− Small Jitter Amplitude → Correct samples
135

Large Jitter Amplitude
− High Frequency Jitter → The clock can not follow timing variations in the input signal
− Large Jitter Amplitude → Incorrect samples
136

Jitter in Clock and Decoding errors
137

– The recovered clock will follow timing variations in the input signal that fall within the bandwidth of the
clock recovery process.
– The timing variations in the SDI signal introduce variations in the transitions of the recovered clock.
– So, actual reference clocks used in decoding are not jitter free.
Jitter frequency is within the bandwidth of the clock recovery process.
138

– The recovered clock does not track variations in signal transitions if the frequency of the variation lies
above the bandwidth of the clock extraction/recovery process.
– At these higher frequencies, the position of signal transitions can vary relative to the edges of the
recovered clock and these variations can create decoding errors (if jitter amplitude was bigger than
specified value).
Jitter frequency is above the bandwidth of the clock recovery process.
If jitter amplitude in input data was bigger than specified value then, create decoding errors
139

– The recovered signal can be as perfect as the original if the data is detected with a jitter-free clock.
– In a communications system with forward error correction, accurate data recovery can be made with
the eye nearly closed.
– As noise and jitter in the signal increase through the transmission channel, certainly the best decision
point is in the center of the eye.
Data Recovery
140

– Jitter refers to short-term time interval error, i.e. spectral components above some low frequency
threshold (for timing jitter> 10Hz)
(Difficult for receiver to adjust, so can be a problem)
– Wander refers to long-term time interval error (<= 10Hz)
(The receivers can generally track these long-term variations, so normally not a problem)
– The recovered clock will generally track spectral components below the clock recovery bandwidth,
but will not track spectral components above this bandwidth.
– Hence, the impact of jitter on decoding SDI signal depends on both the jitter’s amplitude and its
frequency components. This has led to a frequency-based classification of jitter.
Jitter and Wander
141

Timing Jitter:
− The changes related to an ideal
time reference.
− It is preferable to use the original
reference clock, but it is not
usually available, so a heavily
averaged oscillator in the
measurement instrument can be
used.
Alignment Jitter/Relative Jitter:
− The changes related to a
reference derived from the signal
itself.
Timing and Alignment Jitter Measurement
The receiver PLL cannot track this jitter
(PLL out of Band Jitter)
142

“Bandwidths of the clock recovery”
The receiver PLL can track this jitter
The receiver PLL cannot track this jitter
Timing and Alignment Jitter
143
Timing Jitter is used to determine general health of system
Alignment jitter can cause system problems

– The variation in time of the significant instants (such as zero crossings) of a digital signal relative to a clock with no
jitter.
– The standards set threshold at 10 Hz and refer to spectral components above this frequency as timing jitter.
 Measurement based on very stable clock in test device
(It is preferable to use the original reference clock, but it is not usually available, so a heavily averaged oscillator in
the measurement instrument can be used)
 Used to determine general health of system
Timing Jitter
In SDTV
f1=10Hz, f3=1KHz f4=PLL Upper limit (27KHz)
SD-SDI
144

– The variation in time of the significant instants (such as zero crossings) of a digital signal relative to a hypothetical
clock recovered from the signal itself.
– Alignment jitter refers to components in the jitter spectrum above a specified frequency threshold related to typical
bandwidths of the clock recovery processes (1kHz (SD), 100kHz (HD)).
– Alignment jitter shows signal-to-latch clock timing margin degradation.
 Measured based on clock recovered from the signal itself
 Indicates jitter that can cause system problems (Jitter that the receiver PLL cannot track it)
Bandwidths of the
clock recovery
Alignment Jitter or Relative Jitter
In SDTV
f1=10Hz, f3=1KHz f4=PLL Upper limit (27KHz)
SD-SDI
The digital systems will work beyond alignment jitter specification, but will fail at some point.
145

HD-SDI
– Since video equipment can track wander
and low frequency timing jitter, these spectral
components often have less impact on signal
decoding.
– The digital systems will work beyond
alignment jitter specification, but will fail at
some point.
– In general, video equipment does not track
alignment jitter, though some equipment may
track some low frequency alignment jitter.
– High amplitude alignment jitter generally
introduces decoding errors.
Bandwidths of the
clock recovery
The receiver PLL
cannot track this jitter
Timing Jitter
Timing Jitter
146

Eye Pattern Measurement Specification
– For SD-SDI signals, SMPTE 259M specifies that measurements of source output signal characteristics shall be
made across a resistive load connected by a “short coaxial cable.”
– For HD-SDI signals, SMPTE 292M specifies a “1-m coaxial cable.”
– Hence, the standards only specify jitter performance near the source output as measured over a short
cable.
147

– For SDI signal receivers, the standards place some requirements on the SDI inputs, including impedance and
return loss.
– They do not, however, define any performance limits on the jitter input tolerance of an SDI receiver.
– Also, the standards do not define performance limits on jitter transfer in system elements.
148

149
𝑓1
𝑓4
𝑓3
𝑓4

Jitter Measurements Review
150

Jitter Measurements Review
OutputJitterLimitsforSDIClocks
151

152

SDI Physical Layer Parameters -Electrical
153

HD-SDI
154

– Since video equipment can track wander and low
frequency timing jitter, these spectral components often
have less impact on signal decoding.
– Low frequency variations can have significant impact in
other areas, E.g., digital-to-analog conversion stages, use
this recovered clock, or a sub-multiple of this clock.
– Since this clock tracks the low frequency jitter in the input
SDI signal, its edges vary from their ideal positions. This
jitter in the clock signal can introduce errors, e.g., non-
linearity in D-to-A conversion.
Wander and Low Frequency Timing Jitter Effect on Clock
155

Recall of Linearity in Video ADC
If INL is big...Distortion and color unevenness occurred at a gradation part of an image. If DNL is big...Vertical noise occurred at a gradation part of an image
156

− Has been a problem at D/A conversion points
− Must be able to see analog version of signal
Wander and Low Frequency Timing Jitter Effect on Clock
157

Jitter Display with 10 Hz Filter(0.2UI) Jitter Display with 100 Hz Filter(0.12UI)
Jitter Display with 1 kHz Filter(0.12UI) Jitter Display with 100 kHz Filter(0.07UI)
Jitter Display with Different Filter Selections
158

− There are several ways in which jitter may be measured on a single waveform.
− It is important to understand how these measurements relate to each other and what they reveal.
Period Jitter (JPER)
• Time difference between measured period and ideal period (rising edge to next adjacent rising
edge)
Cycle to Cycle Jitter (JCC)
• Time difference between two adjacent clock periods
• Important for budgeting on-chip digital circuits cycle time
• It shows the instantaneous dynamics a clock recovery PLL might be subjected to.
Time Interval Error (TIE) (or Accumulated Jitter (JAC) )
• Time difference between measured clock and ideal trigger clock
• Jitter measurement most relative to high-speed link systems
Jitter measurements
159

– The period jitter (P1, P2 and P3) measures the period of each clock cycle.
– The cycle-cycle jitter (C2 and C3) measures how much the clock period changes between any two
adjacent cycles.
• It can be found by applying a first-order difference operation to the period jitter. (The ideal edge
locations of the reference clock was not required for above measurements)
– The TIE measures how far each active edge of the clock varies from its ideal position (The ideal edges
must be known or estimated)
Jitter measurements
160

Jitter Tolerance refers to how much jitter, as a function of the jitter frequency, can be tolerated by a
system.
– All receiving equipment needs to be tolerant to a specified level of jitter at different frequencies.
– Test and measurement equipment should be tolerant to a higher level of jitter.
Rx Jitter Tolerance
f2 = f3/(A1/A2)
f4 = 148.5MHz (ie 1/10th clock rate)
A1 = 8 UI (168psec) Timing Jitter
A2 = 0.3 UI (25.2psec) Alignement
162

Jitter Tolerance refers to how much jitter, as a function of the jitter frequency, can be tolerated by a
system.
– All receiving equipment needs to be tolerant to a specified level of jitter at different frequencies.
– Test and measurement equipment should be tolerant to a higher level of jitter.
Rx Jitter Tolerance
Timing Jitter
Alignement Jitter
10Hz 3.75kHz 100kHz 1.2GHz
SMPTE RP184 and RP192 jitter tolerance template (SMPTE 2082-1 for 12G-SDI interfaces)
f2 = f3/(A1/A2)
f4 = 148.5MHz (ie 1/10th clock rate)
A1 = 8 UI (168psec) Timing Jitter
A2 = 0.3 UI (25.2psec) Alignement
163

Rx Jitter Tolerance
– A receiver with low jitter input tolerance can generate errors in decoding a signal that forms a wide-
open Eye diagram
– A receiver with high jitter input tolerance may correctly decode a signal that forms a closed Eye
diagram.
Receiver with
low input jitter tolerance
Receiver with
high input jitter tolerance
It can generate errors in decoding
It may correctly do decoding
A wide-open Eye diagram
A closed Eye diagram
164

Jitter Transfer refers to the jitter on the output of equipment that is the result of jitter applied on
the equipment’s input.
– The jitter transfer function is the ratio of output jitter to applied input jitter as a function of
frequency.
Jitter Transfer
𝟏𝟎 𝒍𝒐𝒈 𝟏𝟎
𝑶𝒖𝒕𝒑𝒖𝒕 𝑱𝒊𝒕𝒕𝒆𝒓
𝑰𝒏𝒑𝒖𝒕 𝑱𝒊𝒕𝒕𝒆𝒓
165

– Some video equipment, e.g., a distribution amplifier, produces an SDI output from an SDI signal applied
at an input.
– This kind of jitter can also be the result of jitter from an analogue locking reference such as black & burst.
– Typically, jitter in the input SDI signal does not directly translate to jitter in the corresponding output.
– In particular, clock recovery
• can filter out high frequency jitter
• may amplify some jitter in the input signal
Jitter Transfer
Digital Video Distribution
Amplifier (DVDA)
Input SDI Signal Output SDI Signal
Analog Reference
166

– Jitter Transfer can be measured practically by generating a known level of jitter to the input of the
device under test, for each frequency from f1 to f3 and then measuring the jitter at the output of the
device under test.
– A non-stressing test pattern, such as color bars, should be used to avoid introducing data dependent
jitter into the measurements.
– The device under test and the jitter generator should not be connected to any external locking
reference as this may introduce Output Jitter.
Jitter Transfer Measurement
They should not be connected to any external locking reference
A known level of jitter @ f1 to f3
(non-stressing test pattern)
167

Output Jitter
It is the total jitter measured on the output of the equipment itself and includes:
I. Intrinsic Jitter introduced by the equipment’s own output circuitry
II. Jitter Transfer inherited from a signal connected to the equipment’s input.
– A device’s Output Jitter can be measured by directly monitoring the output of the device using a
jitter analyzer.
– The device’s Intrinsic Jitter can be measured when there is no input or locking reference connected.
Intrinsic Jitter and Output Jitter
168

– In electronics, slew rate is defined as the change of
voltage or current, or any other electrical quantity, per
unit of time.
– The slow slew rate increases the level of jitter (as shown by
the thicker line of the Eye patter display) and therefore
increases the risk of bit errors due to a narrower data
sample area.
– In practice the higher the signal slew rate the larger the
sample area which reduces the risk of bit errors.
Fast Slew Rate
Slow Slew Rate
Slew Rate and Jitter
169

− ITU-R BT.1120-7 requires the transmission loss to be ≤ 30 dB at ½ clock frequency for 3 Gbit/s
operation.
− The current generation cable equalizers are capable of 35 to 40 dB gain at this frequency.
− Some losses
• cable loss (has a √f characteristic)
• losses through connectors
• losses through patch panels
• etc.
− By planning installations with regard to possible losses, the overall link losses not to exceed
the recommended values of 30 dB at 3 Gbit/s, there should be sufficient safety margin to
ensure reliable operation
Cable Length & Equalization
170

− Coaxial cable has signal losses that increase with frequency, much like a low pass filter.
− Some of the losses are due to
1. the resistance of the wire
2. skin effect
− while other losses are caused by
3. dielectric absorption in the insulation.
− The loss curve is approximated by the following formula where L is the loss in dB per unit of cable
length:
− Where “f” is frequency and A, C and D are constants that depend upon the type of cable and unit
length.
− D is the resistive loss constant, C is the dielectric loss constant, F frequency in MHz
(MIL-C-17 Attenuation and Power Handling in coaxial cables).
𝑳 = 𝑨 + 𝑪𝒇 + 𝑫 𝒇
171

− D is the resistive loss constant, C is the dielectric loss constant, F frequency in MHz)
− In many cases, the A and C components are ignored, resulting in the common approximation of
cable losses being proportional to 𝒇.
− This means, if the frequency is multiplied by four, the attenuation of the cable, expressed in dB,
doubles.
− This can be a good rule of thumb, but the other terms are still a part of the losses and may be
important.
𝑳 = 𝑨 + 𝑪𝒇 + 𝑫 𝒇
𝑳 𝛼 𝒇
172

− To enable proper recovery of the serial data, a system (from the transmitter to detector),
must have a frequency response that is nearly flat to at least “half the clock rate”.
− It is also important that the roll-off be reasonably gentle out to three times the clock rate.
SDI
Transmitter
Input SDI SignalOutput SDI Signal
SDI
Receiver
Frequency Response
Frequency
𝒇 𝒄𝒍𝒐𝒄𝒌
𝟐
𝟑𝒇 𝒄𝒍𝒐𝒄𝒌
Nearly Flat
Reasonably gentle roll-off
173

− Belden 1694A cable, for example, is specified
to have a frequency dependent insertion loss
of 26 dB per 100 m at 1.5 GHz.
− This amount of loss requires equalization in
order for the cable to work successfully for
serial digital video.
− Since the length of a cable is not always
predictable, adaptive equalizers have
become a practical solution (automatically
adjust the equalization to match the
apparent cable losses)
174

SMPTE ST 292 and SMPTE ST 424
− For example, the maximum cable lengths listed by Belden are for a 20dB equaliser in the
receiver.
− In real systems, this distance will increase or decrease depending upon the receiver
characteristics.
− If a better receiver is available, the maximum cable lengths will be greater.
SDI
Transmitter
Input SDI SignalOutput SDI Signal
SDI
Receiver
175

In receiver, energy at half-clock frequency is sensed to apply an appropriate analog equalization to the incoming data signal.
Equalizer (Signal Recovery) in SDI Signal
Eye display with closed eye Equalized eye display of same signal
176
After using equalizer, the edge energy of the equalized signal is kept at a constant level which is
representative of the original edge energy at the transmitter.

In receiver, energy at half-clock frequency is sensed to apply an appropriate analog equalization to the incoming data signal.
177

− Adding lengths of cable results in attenuation of the amplitude and frequency losses along
the cable producing longer rise and fall time of the signal (the eye opening closes).
− However, this signal is still able to be decoded correctly because the equalizer is able to
recover the data stream (it is an filter, low jitter and low power).
178

Intersymbol interference (ISI)
− Consider a 1 UI output pulse applied to a buffer:
If rise/fall time >> 1 UI, then the output pulse is attenuated and pulse width decreases.

 UI

  UI

  UI
1UI
< 1UI
179

0 0 11 0 1
Consider 2 different bit sequences:
t = ISI
Steady-state not reached
at end of 2nd bit
2 output sequences superimposed for
eye construction
ISI is characterized by a double edge
in the eye diagram.
− The frequency-dependent cable attenuation “spreads” transitions in SDI signals
180

− It occurs when the spreading of transitions in earlier bits affect transitions in later bits.
− It Caused by
• channel loss
• dispersion
• reflections
– These effects cause transitions to vary from their ideal shapes and locations.
– Specifically, it produces predictable and repeatable jitter whose magnitude depends on the
• frequency responses of devices
• Channels
• data patterns in the signal
– Hence, ISI produces deterministic, data-dependent jitter.
– In particular, cable attenuation greater than 1 dB can introduce significant intersymbol interference.
181

The typical frequency responses of
a 300m cable and equalizer
− It is able to recover signal so that the
equalized eye could be open.
− To avoid data errors due to ISI, receivers
typically have cable equalizers that
compensate for the 1/√𝑓 frequency
response of the cable (cable losses being
proportional to √𝒇).
− The standards do not specify particular
cable types, but require that coaxial
connections have 1/√𝑓 the frequency
response needed for the correct operation
of cable equalizers.
182

– If the equalizer within the instrument is able to recover signal, the equalized eye display
should be open.
– However, it should be remembered that not all receivers use the same designs and there
is a possibility that some device may still not be able to recover the signal.
– If eye is partially or fully closed then the receiver is going to have to work harder to recover
the clock and data.
– In this case there is more potential for data errors to occur in the receiver.
183

– Cable equalization algorithms need many edges in the signal to determine and maintain the
frequency-dependent gain that compensates for the
1
𝑓
frequency response of the cable.
– Long intervals of constant signal level stress equalizer and reclocker and can lead to decoding
errors or synchronization problems.
– Further, AC-coupling can reduce noise margins in decoding if the input signal remains at the
same voltage level for a significant percentage of time.
It must have a sufficient transition
density for equalizing and reclocking.
184

– The edge energy of the equalized signal is monitored
by a detector circuit which produces an error signal
corresponding to the difference between the “desired
edge energy” and the “actual edge energy”.
– This error signal is integrated by both an internal and an
external AGC filter capacitor providing a steady
control voltage for the gain stage.
– As the frequency response of the gain stage is
automatically varied by the application of negative
feedback, the edge energy of the equalized signal is
kept at a constant level which is representative of the
original edge energy at the transmitter.
SD SDI Adaptive Cable Equalizer
The “energy at half-
clock frequency” is
sensed to apply an
appropriate analog
equalization to the
incoming data
signal.
185

Reclocker and alignment jitter reduction
− Recovering the embedded clock from a digital video signal and retiming the incoming video data.
– The reclocker uses the recovered clock to regenerate the SDI signal.
– Since the recovered clock does not track alignment jitter well, reclocking can substantially reduce
alignment jitter.
Reclocking SDI Signal
186

Reclocker and wander/low-frequency timing jitter
– The Reclocking “may not significantly reduce” wander or low-frequency timing jitter since the recovered
clock tracks these variations.
– Hence, low-frequency variations can build through a video system.
– Amplitudes can eventually grow beyond the tracking capability of clock recovery processes.
– At this point, decoding errors will appear and the clock recovery hardware might not remain locked to the
input signal.
– So, the clock recovery also affects the way jitter and wander accumulate in a video system.
Reclocking SDI Signal
187

LMH0303
It drives SDI Signal to Cable.
• Loss-of-signal (LOS) detector
• The cable detect feature senses near-end
termination to determine if a cable is
correctly attached to the output BNC.
• The output amplitude is adjustable ±10% in
5mV steps through the SM Bus configuration
(System Management Bus).
• Input interfacing (accepts either differential
or single-ended input)
• Output interfacing (current mode outputs)
• Output slew rate control
• Cable fault detection (no cable is connected
to the output (near end))
SDI Cable Driver
The LMH0303 drives 75-Ω transmission lines (Belden 1694A,
Belden 8281, or equivalent) at data rates up to 2.97 Gbps.
188

– (1) Defined by mid-amplitude point of the signal.
– (2) Measured across a 75 Ω resistive load connected through a 1 m coaxial cable.
– (3) In the frequency range of 5 MHz to fc/2. (fc: serial clock frequency)
– (4) In the frequency range of fc/2 to fc.
– (5) Determined between the 20% and 80% amplitude points and measured across a 75 Ω resistive load.
– Overshoot of the rising and falling edges of the waveform shall not exceed 10% of the amplitude.
– (6) 1 UI corresponds to 1/fc. Specification of jitter and jitter measurements methods shall comply with Recommendation ITU-R BT.1363 – Jitter specifications and methods for
jitter measurement of bit-serial signals conforming to Recommendations ITU-R BT.656, ITU-R BT.799 and ITU-R BT.1120.
– Output amplitude excursions due to signals with a significant dc component occurring for a horizontal line (pathological signals) shall not exceed 50 mV above or below the
average peak-peak signal envelope. (In effect, this specification defines a minimum output coupling time constant.)
Line driver characteristics (source) (HD)
189

Line Receiver and Transition Line characteristics
190

Equipment that does not modify the serial data
• Routing switcher
• Patch panel
• Digital delay
Equipment that should not modify the active picture data
• Frame synchronizer with Proc-amp controls at unity
• Embedded audio mux and Demux
Equipment that may modify the active picture area
• Digital VTR or disk recorder or production switcher
Types of Equipment in term of SDI Signal Modification
191

– If any digital data word changes value between the serial transmitter and receiver there is an error.
– Data errors can produce sparkle effects in the picture, line drop outs or even frozen images.
– At this point, the receiver is having problems extracting the clock and data from this SDI signal.
– Types of Errors:
Active Picture Error
• An error in the data representing the active picture as defined by the appropriate standard.
Full Field Error
• An error in the data representing all lines except those affected by a standard vertical interval switch.
(lines 9-11 in 525, or lines 5-7 in 625 line standards).
Bit Error Rate (BER)
• BER requires measurement over many bits, and is often measured over long periods of time.
• Typical video errors occur in bursts, maybe hundreds of errors in a burst.
Errored Second
• Errored Seconds is a count of seconds-with-errors.
• One errored second in a program gives more information about the type of problem than single bit error rate.
Types of Errors
192

0 1
Sampling Point
BER
Time
BER
Time
BER
– The BER is a useful measure of system performance in situations where the SNR at the
receiver is at such a level that random errors occur.
Bit - Error Ratio (BER)
193

The ratio of the number of incorrect bits received to the total number of bits received.
− As an example, consider the serial digital interface (SDI) which has a data–rate of 270
Mbit/s. If there were one error per frame, the BER would be:
− To illustrate the significance of BER values, table
relates mean time intervals between errors to
approximate BER values in the case of the SDI.
194

– Scrambling is used in the SDI to reduce the DC component of the transmitted signal and ensure that
the signal reaching the receiver has a sufficiently large number of zero–crossings to permit reliable
clock recovery.
– An inherent feature of the descrambler:
A single bit error → will cause an error in two data words (samples) → with 50% probability, the error in
one of the words will be in either the most–significant bit or in the second–most significant bit.
– Therefore, an error–rate of 1 error per frame will be noticeable by a reasonably patient observer.
–
– The fact that the error is noticeable is sufficient to make it unacceptable (in purist engineering terms,
at least, if not subjectively), but it is even more unacceptable because of the indications it gives
about the operation of the SDI system.
195

− In most cases, scrambling and NZRI encoding ensures that SDI signals have many transitions.
− Typical SDI signals do not have long intervals of constant voltage that stress clock recovery,
equalization, or decoding processes.
− However, particular word patterns in digital video content can produce SDI signals with long constant-
voltage intervals.
− If the shift register used in the scrambling process has a particular state and the scrambler receives one
of several special input bit sequences, the resulting SDI signal after NRZI encoding will have one of the
patterns shown.
Out-of-service testing (SDI check field)
Stress Testing for Clock Recovery and Cable Equalization
196

– The SDI Check Field is also known as “pathological
signal”
– It has a maximum amount of low-frequency energy in
two separate signals.
– One signal tests equalizer operation and the other
tests phase-locked loop operation.
– Video equipment designers can use these signals to
“stress test” clock recovery and equalization
processes and to verify the correct operation of
clamping or DC-restoration circuits that compensate
for AC-coupling effects.
197

• The upper part of the image creates data
words with long runs of zeros in the serial data
stream.
• This results in a DC step in the SDI signal.
• Using an equalizer with insufficient dynamic
could lead to image distortions.
198

• The data words in the lower image of the
check field provide only very few reference
edges for the clock recovery.
• Insufficient design of the input PLL will result in
image distortions.
199

An eye display in field mode shows the DC offset (DC glitch)
inserted into the signal path by the SDI Check Field test signal.
200

– If errors occur they can manifest themselves as
• transient dropouts in the video signal or
• worse yet, a complete loss of synchronization
− If the SDI-check field fails to be transmitted successfully then tearing of the picture will be
observed on a display.
201

The longest sequence of 0s in the active video signal will
occur if the value 80.0hex is followed by 01.Xhex
Creation of the longest possible sequence of
“0”s in active video data words.
Another SDI Check Field
202

Composition of the SDI Check Field
203

Composition of the SDI Check Field
204

SDI Check Field for 3G-SDI Signals
205

− To determine whether a sampled signal voltage corresponds to a “high” or “low” signal level,
decoders compare the sampled voltage against a particular voltage level called the decision
threshold or decision level.
− Optimally chosen decision threshold
“will equally protect against errors generated by noise on either signal level”.
− If each signal level has the same amount of noise, the optimal decision threshold equals the average
of the two signal voltage levels.
Decoding Decision Threshold
206Sameamountofnoise
The optimal decision threshold
=
The average of the two signal voltage levels.

− SDI receivers generally use fixed decision thresholds in the decoding process.
− For optimal performance, signal levels (level high and low) must keep the same relative relationship
to this fixed voltage level.
− A shift in the signal relative to the decision threshold reduces the noise margin for one of the signal
levels, which can lead to decoding errors (ex: DC shift in SDI Signal).
Decoding Decision Threshold
207
The Fixed decision thresholds
in the decoding process
High signal level
Low signal level
Average signal level

− DC offsets in the input SDI signal could lead to decoding errors.
− SDI receivers typically have AC-coupled inputs that remove DC-offsets in the input SDI signal.
− So a constant average voltage will exist in the AC-coupled signal (because possible variable DC term is
removed from SDI Signal).
− In many implementations, this average signal level equals zero volts, although biasing circuitry in the
receiver could set the average signal level of the AC-coupled signal to a non-zero value.
Decoding Decision Threshold and AC Coupling Effects
Example Cable Equalizer Connections
208
AC-coupling
ShiftDC-offsets Removal
To maintain an average
signal level of zero volts

− SDI receivers generally use fixed decision thresholds in the decoding process.
− Typically, the fixed decision threshold is used by receiver is equal to the average voltage of the AC-
coupled signal.
If the average signal voltage of AC-coupled signal is always an optimal value for fixed decision threshold ?
The optimal decision threshold may differ from the average signal voltage if one signal level can have
more noise than the other.
209
The AC-coupling set the “Fixed decision threshold for transition
detection” to the average signal voltage of the AC-coupled signal.
Fixed Decision Threshold
=
AC-couple Signal Average Voltage

− The amount of shift depends on the coupling time constant.
• For example, with a coupling constant of 10 µsec, an equalizer stress pattern will shift almost 78%
closer to the fixed decision level over one-half of an HD video line.
• For example, with a coupling time constant of 75 µsec, the stress pattern will shift by less than 33%
over an entire HD video line.
− The value of the AC coupling capacitors should be large enough to support the pathological patterns
present in the SDI waveforms.
− For SDI applications, the AC coupling capacitors are typically in the 1 μF to 10 μF range.
While AC-coupling filters out DC offsets in the input SDI signal, it can also shift the signal
levels in the AC-coupled signal relative to a fixed decision threshold.
210

Example 1: non-stressing test pattern
− Input SDI signal not contain any long duration at the same voltage level.
− The situation for an implementation of AC-coupling that maintains the average signal level in the AC-
coupled signal at zero volts.
− The decoding process also uses zero volts as the fixed decision threshold.
− Here both signal levels can have same noise.
− The fixed decision threshold falls at an optimal position midway between the two levels.
Fixed Decision Threshold = Average Signal Voltage
211A segment of an AC-coupled signal derived from an input SDI signal

Example 2: stress testing input
− Input SDI signal stays at the low signal level for long periods of time.
− The signal remains at the low signal level 95% of the time.
− To maintain an average signal level of zero volts, the low signal level in the AC-coupled signal must
equal -0.05 Vpp, while the high signal level must equal +0.95 Vpp.
An example of the equalizer stress patterns.
212

Example 2: stress testing input
− The low signal level is very close to the fixed decision threshold for decoding → eliminates the noise
margins for this signal level → will lead to decoding errors (in the next stage).
− In effect, the AC-coupling has generated intersymbol interference. The values of earlier bits (long
strings of ‘0’ bit values after scrambling) have impacted the decoding of later bits.
A segment of an AC-coupled signal derived from an input SDI signal
213

− Due to scrambling and NRZI encoding, SDI signals are symmetric, i.e. they spend nearly the same
amount of time at each signal level.
− More specifically, typical SDI signals are symmetric when signal levels are averaged over many unit
intervals.
− Shorter-term, SDI signals can have several periods of constant signal level, with pathological SDI
signals as the extreme case.
Decoding Decision Threshold and Clamp or DC-Restore
To compensate for this AC-coupling shift, SDI receivers typically clamp or DC-restore the AC-coupled
signal to maintain the relationship between the signal levels (∓400mv) and the fixed decision threshold.
Input SDI Signal
SDI Receiver
AC-coupling
Shift
DC-Restore
(Clamp)
Equalizer Reclocker
214
DC-offsets Removal

– The Equalizer Filter block is a multi-stage adaptive filter.
If Bypass is high, the equalizer filter is disabled.
– The DC Restoration/Level Control block incorporates a
self-biasing DC restoration circuit to fully DC restore the
signals. If Bypass is high, this function is disabled.
– The signals before and after the DC Restoration/Level
Control block are used to generate the Automatic
Equalization Control (AEC) signal. This control signal sets
the gain and bandwidth of the equalizer filter.
– The Carrier Detect/Mute block generates the carrier
detect signal and controls the mute function of the
output. The Output Driver produces SDO and NOT SDO.
DC Restore or Clamping
1 µF capacitor
The “energy at half-clock frequency” is
sensed to apply an appropriate analog
equalization to the incoming data signal.
215
≈ 𝑺𝑫𝑰 𝑺𝒊𝒈𝒏𝒂𝒍 𝒂𝒕 𝑻𝒓𝒂𝒏𝒔𝒎𝒊𝒕𝒕𝒆𝒓

Conclusion
•The AC-coupling set the “decision threshold for transition detection” to the average signal voltage of
the AC-coupled signal.
•While AC-coupling filters out DC offsets in the input SDI signal, it can also shift the signal levels in the AC-
coupled signal relative to a fixed decision threshold.
•Shifts due to AC coupling can reduce noise margins in decoding if the input signal remains at the same
voltage level for a significant percentage of time (by SMPTE pathological test patterns).
•SDI receivers typically clamp or DC-restore the AC-coupled signal to maintain the relationship between
the signal levels and the fixed decision threshold.
•The equalized signal is DC restored, effectively restoring the logic threshold of the equalized signal to its
correct level (∓400mv) independent of shifts due to AC coupling (compensate for AC-coupling effects).
216

Even in SDI signals with frequent transitions, AC-coupling can introduce a shift in the signal relative to the
fixed decision level.
− For example, if the signal has fast rise times and slow fall times, it will spend more time in the high
signal state (In general, If the rise and fall times of signal transitions differ significantly)
− AC-coupling will then shift the high signal level closer to the fixed decision threshold, reducing noise
margin.
AC Coupling Effects in Asymmetric Signals
High Signal Time
Low Signal Time
AC-coupling
217

− Typically, SDI signals have symmetric rise and fall times, but asymmetric line drivers and optical signal
sources (lasers) can introduce non-symmetric transitions.
− While significant, these source asymmetries do not have especially large impacts on signal rise and
fall times.
− In particular, cable attenuation will generally have a much larger impact on signal transition times.
− Without appropriate compensation or other adjustments, asymmetries in SDI signals can reduce noise
margins with respect to the decision threshold used in decoding and can lead to decoding errors.
− These same asymmetric conditions can also impact jitter measurements.
AC Coupling Effects in Asymmetric Signals
218

Some typical approaches for determining optimal decision level for transition detection
– The standards do not give any guidance regarding the decision threshold for the transition detection
stage in the jitter measurement process.
• The 50% point in transition
• The Eye crossover points below the 50% point in transition
• The average signal voltage of the AC-coupled signal.
Transition Detection Issues
219
(maximum Eye width)
Decision threshold = Eye
crossover points
Decision level = 50%
point in the transition.
50% point 50% point
Eye crossover points
Decision level = Average signal
voltage of the AC-coupled signal

220
Optimal decision threshold in symmetric signals for transition detection
– To measure jitter, the measurement process needs to determine the point in time when an actual
signal transition occurs.
– For transitions with equal rise and fall times, this optimal decision level equals the 50% point in the
transition.
Optimum decision threshold for
transition detection at the 50% point.
50% point in the transition 50% point in the transition

221
IdealPosition
IdealPosition
NonIdealPosition
NonIdealPosition
NonIdealPosition
NonIdealPosition
Non-optimal decision threshold effect on transition
detection in measurement instruments
– To measure jitter, the measurement process needs to
determine the point in time when an actual signal transition
occurs.
– For transitions with equal rise and fall times, this optimal
decision level equals the 50% point in the transition.
• Using a non-optimal decision threshold in transition detection,
the detected transitions vary from their ideal positions.
• This non-optimal transition detection process has introduced a
deterministic jitter component called duty-cycle dependent
jitter.
• The time between two edges would be less than the
appropriate multiple of the unit interval.

Non-symmetric signal transitions effect on transitions detection in measurement instruments
– The standards do not give any guidance regarding the decision threshold for the transition detection
stage in the jitter measurement process.
– The standards allow a significant difference in rise and fall times.
– If the transition detection stage in a jitter measurement process used a decision level equal to the 50%
point in the transition, the results would include a significant amount of duty-cycle dependent jitter.
– A jitter measurement method that could align (set) the decision threshold with the Eye crossover points
(maximum Eye width) would give a smaller result (minimal jitter).
222
(maximum Eye width)
Fixed decision threshold equals
to the Eye crossover points
Decision level equals the
50% point in the transition.
50% point 50% point

Non-symmetric signal transitions effect on transitions detection in measurement instruments (cont.)
– The standards do not have specifications on compensating for AC-coupling effects or
accommodating non-symmetric signal transitions.
– Acceptable SDI signal with slow rise time and a fast fall time shows the 50% point in transition does
not always equal the optimal decision level for transition detection.
– The Eye crossover points appear well below the 50% point in transition in the transition (A jitter
measurement method that could align the decision threshold with the Eye crossover points
(maximum Eye width) would give a smaller result (minimal jitter)).
223
(maximum Eye width)
Fixed decision threshold equals
to the Eye crossover points
Decision level equals the
50% point in the transition.
50% point 50% point

AC-coupling effect on transition detection in measurement instruments
– Most measurement instruments have AC-coupled inputs and set the decision threshold for transition
detection to the average signal voltage of the AC-coupled signal.
– In most cases, this approach results in near-optimal transition detection because typical SDI signals
are symmetric “in the long term”.
– In the short term, typical SDI signals can spend several unit intervals at the same signal level.
• Generally, measurement instruments adequately compensate for AC-coupling effects related to
this short-term behavior.
– In the long term (durations equal to many unit intervals) the signal spends nearly the same amount of
time at each voltage level.
• The average signal voltage over these durations lies close to optimal position for transition
detection at the midpoint of the Eye height (does not introduce duty-cycle dependent jitter).
224

AC-coupling effect on transition detection in measurement instruments (cont.)
– In particular, long constant-voltage intervals in an SDI signal can shift the signal relative to a fixed
decision threshold.
– In this case, the transition detection stage in the jitter measurement introduces duty-cycle dependent
jitter.
– Equalizer stress patterns in pathological signals can cause significant shifts in the AC-coupled signal.
– In this case, duty-cycle dependent jitter introduced in the transition detection stage could increase
the peak-to-peak jitter amplitude measurement.
225

− Scrambling can also produce long runs of 1s or 0s.
− This happens infrequently in video
− It happens occasionally with EAV and SAV which contain 2 or 3 words of all 0s
− It can be encouraged to happen with certain input signals
− Scrambler Concern
− Specific pattern of .1s. and .0s input can create strings of 0s output.
Scrambled NRZI Problem
226

– For SD formats, the CRC value is inserted into the vertical interval, after the switch point.
– SMPTE RP165 defines the optional method for the detection and handling of data errors in standard
definition video formats (EDH: Error Detection Handling).
– Full Field and Active Picture data are separately checked and a 16-bit CRC word generated once
per field.
1. The Full Field (FF) check covers all data transmitted except in lines reserved for vertical interval
switching (lines 9-11 in 525, or lines 5-7 in 625 line standards).
2. The Active Picture (AP) check covers only the active video data words, between but not
including SAV and EAV. Half-lines of active video are not included in the AP check (Just
complete lines are used).
Digital monitors may provide both a display of EDH CRC values and an alarm on AP or FF CRC errors .
In-Service Testing (CRC: Cyclic Redundancy Check)
227

Error Detection and Handling (EDH) in Digital Television
– SMPTE RP165 defines the optional method for the
detection and handling of data errors in standard
definition video formats (EDH Error Detection
Handling).
– Basic principal similar to computer file transfer
(CRC)
– EDH is not used with high definition video, as the
HD serial digital interface includes a mandatory
embedded CRC for each line.
228

In HD formats, CRCs for luma and chroma follow EAV and line count ancillary data words.
– The CRC for high-definition formats is defined in SMPTE 292M to follow the EAV and line number words.
– So CRC checking is on a line by line basis for Y-CRC and C-CRC.
 Ideally, the instrument will show zero errors indicating an error-free transmission path.
 If the number of errors starts to increase, the user should start to pay attention to the increase in
errors.
 As the errors increase to one every hour or minute, this is an indication that the system is getting
closer to the digital cliff.
 If errors occur every minute or every second, the system is approaching the digital cliff and
significant CRC errors would be seen in the display.
3FF(C)
3FF(Y)
000(C)
000(Y)
XYZ(C)
XYZ(Y)
LN0(C)
LN0(Y)
LN1(C)
LN1(C)
CCR0
YCR0
CCR1
YCR1
000(C)
000(Y)
CbData
YData
CrData
YData
EAV LN CRC
229

Eye-Pattern Testing
To make the Eye diagram, the instrument aligns the segments using a reference clock signal.
− Typically this reference clock is extracted from the data signal, but may be a separate reference
clock signal.
− If the transitions in the input signal align with the edges in this reference clock they will lie on top of
each other in the Eye diagram.
− Any transitions that vary from the nominal positions determined by this reference clock will appear in
different locations.
− If the instrument uses a recovered clock to form the Eye diagram, the reference clock will track jitter
below the loop bandwidth of this clock recovery process in the measurement instrument.
Thus, the Eye diagram will only show jitter components with
frequencies above this bandwidth threshold, called the “Eye
Clock Recovery Bandwidth” of the measurement instrument.
230

Eye-Pattern Testing
The Eye diagram will only show jitter components with frequencies above
the “Eye Clock Recovery Bandwidth” of the measurement instrument.
Input SDI Signal
Frequency
If this signal is fed to
recorder, it has different
clock extraction circuit
from measurement
instrument
Eye Clock Recovery Bandwidth
Clock recovery bandwidth in the receiver
Frequency
0
231

Eye-Pattern Testing
Qualitative assessment of signal jitter using Eye diagrams
− The size of the Eye opening correlates reasonably well with the potential for decoding errors.
− If the input signal forms a large, “wide-open” Eye, the decoding process will most likely sample the signal before the
transition to the next bit.
The clock recovery bandwidth in the receiver
Frequency
Frequency
The Eye Clock Recovery Bandwidth=
0
232

− The signal may contain jitter frequencies below the Eye Clock Recovery Bandwidth that impact the decoding process
but do not appear in the Eye diagram.
− The decoding process may generate errors even though the Eye diagram has a large Eye opening.
Eye-Pattern Testing
Frequency
Frequency
The clock recovery bandwidth in the receiver The Eye Clock Recovery Bandwidth<
0
233

− The Eye diagram may show jitter that does not impact the decoding process.
− The receiver may decode the signal without errors even though the Eye diagram has a small Eye opening or is
completely closed.
Eye-Pattern Testing
Frequency
Frequency
The clock recovery bandwidth in the receiver The Eye Clock Recovery Bandwidth>
0
234

Other factors also influence the qualitative assessment of signal jitter using Eye diagrams.
− If receivers introduce a significant amount of internal jitter or do not consistently sample near the middle of the unit
interval, they may generate more decoding errors than suggested by the size of the Eye opening.
− In using an Eye diagram to assess the potential for data errors, engineers need to consider the combined effects of
the
• receiver’s clock recovery
• equalization
• decoding processes
− In other words, they need to consider the receiver’s jitter input tolerance.
Eye-Pattern Testing
Receiver with
low input jitter
tolerance
Receiver with
high input jitter
tolerance
It can generate errors in decoding
It may correctly do decoding
A wide-open Eye diagram
A closed Eye diagram
235

The cable equalization used in receivers will restore the signal’s transitions and “re-open” the Eye.
− With adequate equalization, the ISI from cable attenuation will not significantly impact the decoding
process.
− Without adequate equalization, the data-dependent jitter introduced by cable effects can lead to
decoding errors.
− While equalization can compensate for cable effects, the equalized signal can still contain signal
jitter or amplitude noise that reduces or closes the Eye opening.
− To qualitatively assess the remaining potential for decoding errors after equalization, engineers can
use an Equalized Eye Diagram constructed from the equalized version of the input signal.
Eye-Pattern Testing
Equalization
(WFM 7200)
Equalized Eye Diagram
SDI Signal
Non-equalized Eye Diagram
236

Eye diagrams can also show AC-coupling effects.
− Signal level shifts due to AC-coupling, causes a corresponding shift in the superimposed segments that form the Eye
diagram.
− This can occur even if the measurement instrument forming the Eye-diagram has a DC-coupled input.
− Other equipment in the system may have AC-coupled inputs, causing shifts in the SDI signal before it reaches the
measurement instrument.
Eye-Pattern Testing
DC-Coupled Eye Diagram with DC-coupled input
SDI Signal
Eye Diagram with AC-coupled inputAC-Coupled
237

Jitter Histogram Representation
Reference
Point Histogram
Reference
Point
238

Long cable
• Decrease in amplitude
• Decrease in Frequency
response
• Eye opening narrows
• Rise/Fall time increases
Termination
• Incorrect termination
causes overshoot and
undershoot
Shift in Eye Crossing
• Shifts 50% point of eye
opening
• Caused by unequal rise
or fall time
Eye Pattern Distortions
239

• Signal amplitude is important because of:
1- Its relationship to noise tolerance
2- The receiver estimates the half-clock-frequency energy remaining in arrived signal.
Incorrect amplitude at the sending side could result in an incorrect equalization being applied at the
receiving end, causing signal distortions.
• Incorrect rise time could cause signal distortions such as ringing and overshoot, or if too slow, could reduce
the time available for sampling within the eye.
• Overshoot will likely be caused by impedance discontinuities or poor return loss at the receiving or sending
terminations.
SDI Signal with incorrect
amplitude Incorrect equalization
Signal distortions
240

Improper Termination and Return Loss
– It means that not all of the energy will be absorbed by the receiving termination or device.
– This residual energy will be reflected back along the cable creating a standing wave.
– These reflections will produce ringing within the signal and the user will observe overshoot and
undershoots on the eye.
– Note that this termination error by itself would not cause a problem in the signal being received.
However, this error added cumulatively to other errors along the signal path will narrow the eye
opening more quickly and decrease the receiver’s ability to recover the clock and data from the
signal.
241

Unterminated eye display
Internal and External Termination
– The termination within an HD system is more critical because of the high clock rate of the signal.
– The HD inputs are usually terminated internally and because that in-service eye-pattern testing
will not test the transmission path (cable) feeding other devices.
– Out-of-service transmission path testing is done by substituting a test signal generator for the
source, and a waveform monitor with eye-pattern display in place of the normal receiving
device.
242

Cable Loss
– It tends to reduce the visibility of reflections, especially at HD data rates and above.
– A low value of return loss is more likely to cause problems when short cable lengths are used.
– With long cable lengths, the effect of a mismatch is reduced owing to the greater cable attenuation.
It reduce the
visibility of
reflections
Cable attenuation
243

Non-symmetrical eye (inequality between the transitions)
– The eye display typically has the cross point of the transition in the middle of the eye display at the 50%
point.
– If the rises time or fall time of the signal transitions are unequal then the eye display will move away from the
50% point depending on the degree of inequality between the transitions.
– AC-coupling within a device will shift the high signal level closer to the fixed-decision threshold reducing
noise margin.
Non-symmetrical eye display
244

Typically, SDI signals have symmetric rise and fall times
– Without appropriate compensation or other adjustments, asymmetries in SDI signals can reduce noise
margins with respect to the decision threshold used in decoding and can lead to decoding errors.
– An asymmetric line drivers (cable drive) and optical signal sources (lasers) can introduce non-
symmetric transitions. While significant, these source asymmetries do not have especially large
impacts on signal rise and fall times.
– In particular, cable attenuation will generally have a much larger impact on signal rise and fall times.
Non-symmetrical eye display
245

– Low frequency jitter cause the hole eye move to left and right on waveform monitor.
– High frequency jitter cause eye edges move to left and right on waveform monitor.
– Larger opening indicates better receiver sensitivity and a greater tolerance for noise and jitter
– Wide top, base and transition region indicates reduced receiver sensitivity.
– As long as the noise and jitter don’t exceed the threshold of the detection circuits (that’s, the eye is
sufficiently open) the data will be perfectly reconstructed.
246

Things to consider during installation
– Choose appropriate cable
– Treat Cable with respect
– Cable Margin
– Apply stressing Pathological signal
Things to consider for operational monitoring
– Monitor the EDH of the SD-SDI signal
– Monitor the CRCs of the HD-SDI signal
– Set alarm thresholds for physical layer
– Use Eye and Jitter displays
Keeping an Eye on the SDI System
247

– Unlike analog systems that tend to degrade gracefully, digital systems tend to work without fault until
they crash.
– To date, there are no in-service tests that will measure the headroom of the SDI signal.
– Out-of-service stress tests are required to evaluate system operation.
• Stress testing consists of changing one or more parameters of the digital signal until failure occurs.
• The amount of change required to produce a failure is a measure of the headroom.
Stress Testing
Cable attenuation
248

– The most intuitive way to stress the system is to add cable until the onset of errors.
– Experimental results indicate that cable-length testing, in particular when used in conjunction with the
SDI check field signals, is the most meaningful stress test because it represents real operation.
– Stress testing the receiver’s ability to handle amplitude changes and added jitter are useful in
evaluating and accepting equipment, but not too meaningful in system operation.
– In the testing of in-studio transmission links and operational equipment, a single error is defined as one
data word whose digital value changes between the signal source and the measuring receiver.
Cable-Length Stress Testing
249

Calculated 525/625 component bit-error rate Calculated NTSC bit-error rate
Cable-Length Stress Testing
250

− Unlike analog systems that tend to degrade gracefully, digital systems tend to work
without fault until they crash.
Signal Strength/Quality
PictureQuality
Cliff Effect
251

252
− When the upper energy bands disappear, the HD stream
no longer resembles a bit stream and more like a sine
wave.
− When this happens the signal is no longer recoverable.
− Do you know how much high frequency energy is left?
− The only way to check the headroom of a digital signal
used to be with expensive test equipment.
− The 4sight offers an inexpensive way to check how close
your signals are to the error headroom cliff.
− The HRM-1500 is a portable hand held device that quickly
displays the spectral health of an HD signal.
HD Signal Error Headroom Meter
HRM-1500, $1500

Serial Digital Interface (SDI), From SD-SDI to 24G-SDI, Part 1

Serial Digital Interface (SDI), From SD-SDI to 24G-SDI, Part 1

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Serial Digital Interface (SDI), From SD-SDI to 24G-SDI, Part 1