Leveling to the Last Mile: Near-zero-cost Bit Level Wear Leveling for PCM-based Main Memory Paper presentation

1. Leveling to the Last Mile: Near-zero-
cost Bit Level Wear Leveling for
PCM-based Main Memory
Speaker: Po-Chuan, Chen

2. Table of contents
• Abstract
• Introduction
• Related work : Existing wear leveling
• Bit-level wear leveling : necessary & challenges
• Intra – line flipping (ILF)
• Basic scheme of ILF
• Flipping frequency
• Flipping granularity
• Case study : combining start-gap and enhanced ILF
• Evaluation
• Conclusion

3. Abstract
• Phase change memory (PCM)
characteristics of non-volatility, scalability and near-zero leakage power.
• Drawbacks
the comparatively poor endurance of PCM largely limits its adoption.
• Solution
propose a near-zero-cost bit-level wear leveling strategy to improve PCM endurance

4. Introduction
• To fully exploit PCM write potential, many techniques have been
proposed for endurance enhancement, which can be summarized in
two categories
 Reducing the write counts in order to elongate PCM lifetime
 Wear leveling through migrating writes from heavily burdened regions to
less written regions to relief the wear-out risk

5. Contribution
 A bit-level wear leveling design
 Near-zero-cost intra-line flipping scheme (ILF) for PCM endurance
enhancement and then extend it to an enhanced, dynamic ILF scheme.
 Evaluate the efficacy of the proposed schemes by combining them with
existing coarser-grained wear leveling approaches.

6. Wear leveling can be conducted at various granularities
 Segment level
aim at balancing writes across segments
 Page level
evenly spread writes across pages
 Line level
balance write counts across memory lines

7. Some other things that hasn’t done it before
Few work considers wear leveling at the bit level since it is impractical to
precisely record write counts of different bits.
However, bit-level wear leveling is of great necessity due to the significant
write imbalance within memory lines caused by program characteristics.

8. In this work
• A near-zero-cost bit-level wear leveling scheme, intra-line flipping (ILF).
 It periodically flips the bit mapping in a memory line so as to swap the
writes on hot and cold bits
 And solve this problem in a regular manner without any counter or
address mapping table.

9. Table of contents
• Abstract
• Introduction
• Related work : Existing wear leveling
• Bit-level wear leveling : necessary & challenges
• Intra – line flipping (ILF)
• Basic scheme of ILF
• Flipping frequency
• Flipping granularity
• Case study : combining start-gap and enhanced ILF
• Evaluation
• Conclusion

10. Existing related works (Categories)

11. Existing related works (Strategies)

12. Row shifting
• It conducts bit-level wear leveling, and is most closely related to this paper.
 a counter recording the write counts for each line is maintained.
 Data are shifted periodically based on the write count information.
 The shift location is also recorded for each line.
• Compared to this approach, the proposed technique does not record
detailed write information.

13. Table of contents
• Abstract
• Introduction
• Related work : Existing wear leveling
• Bit-level wear leveling : necessary & challenges
• Intra – line flipping (ILF)
• Basic scheme of ILF
• Flipping frequency
• Flipping granularity
• Case study : combining start-gap and enhanced ILF
• Evaluation
• Conclusion

14. Bit-level wear leveling : necessary & challenges
To examine the write distribution within lines, we
record the bit flip rate at different bit positions for
SPEC2006 benchmarks
We quantify this potential of endurance
improvement using Max(counterArray) /
Ave(counterArray)
Database searching
Chess playing
C++ program library 286%
227%
280%
824%
417%
Endurance improvement

15. Prohibitive overhead
• For pervious studies, if quasi start-gap is applied, it will need two
counters as well as one empty bit for each 512-bit memory line,
imposing an overhead of 9*2+1=19 bits.
• The balancing scheme needs to take into consideration application-
specific write patterns to achieve endurance benefit.

16. How to solve it ?
Yet the challenge is to develop a wear leveling scheme effective for
applications of different write patterns, with no need of any counter or
address mapping table.
In this paper, we achieve this goal through a cost-efficient intra-line
flipping (ILF) scheme.

17. Table of contents
• Abstract
• Introduction
• Related work : Existing wear leveling
• Bit-level wear leveling : necessary & challenges
• Intra – line flipping (ILF)
• Basic scheme of ILF
• Flipping frequency
• Flipping granularity
• Case study : combining start-gap and enhanced ILF
• Evaluation
• Conclusion

18. Basic scheme
• Motivated by the fact that in most programs the least significant bits
are more frequently programmed than the most significant bits

19. Two important characteristics
There are two key issues pertaining to flipping frequency and flipping
granularity in designing the ILF scheme.
 Flipping frequency defines how often the storage direction is flipped.
 Flipping granularity defines the unit size for flipping.

20. Flipping frequency
When ILF is used exclusively, a counter can be used to record the
desired flipping frequency and trigger flipping periodically.
A more efficient usage is to combine bit-level wear leveling with
coarser-grained wear leveling strategies.

21. Table of contents
• Abstract
• Introduction
• Related work : Existing wear leveling
• Bit-level wear leveling : necessary & challenges
• Intra – line flipping (ILF)
• Basic scheme of ILF
• Flipping frequency
• Flipping granularity
• Case study : combining start-gap and enhanced ILF
• Evaluation
• Conclusion

22. Flip_bit
The status bit flip bit is updated accordingly.
 ILF eliminates the overhead for maintaining counters, and the flipping
frequency is the same as the data migration frequency in random page
swap.
 The same strategy can be applied when ILF is combined with other
coarser-grained wear leveling techniques.

23. Flipping granularity
• Application specific ILF
(The best flipping granularity)
• Uniform ILF :
the most effective flipping granularity for all benchmarks on average
• Enhanced ILF :
almost all the benchmarks benefit from enhanced ILF when compared
against the uniform ILF

24. Application specific ILF
Media applications usually process data in 8-byte unit, and thus can
adopt a 64-bit flipping granularity to even out the writes within every
64 bits.
Computation intensive applications can choose the granularity that
effectively flips the least significant and the most significant bits to
even out the writes within one line.

25. Flipping granularity
• Application specific ILF
(The best flipping granularity)
• Uniform ILF :
the most effective flipping granularity for all benchmarks on average
• Enhanced ILF :
almost all the benchmarks benefit from enhanced ILF when compared
against the uniform ILF

26. Uniform ILF
We varied the granularity among {8, 16, 32, 64, 128, 256, 512} bits,
collected the resulting average memory lifetime, and found that
granularity of 128-bit is generally the best for all tested benchmarks.
With this uniform flipping granularity, the runtime flipping can be
conducted in a regular and effective manner, with no need of
application specific information.

27. Flipping granularity
• Application specific ILF
(The best flipping granularity)
• Uniform ILF :
the most effective flipping granularity for all benchmarks on average
• Enhanced ILF :
almost all the benchmarks benefit from enhanced ILF when compared
against the uniform ILF

28. Enhanced ILF
The flipping granularity can be iteratively chosen from the set of {8, 16,
32, 64, 128, 256, 512} bits, and a three-bit vector flip bits can be
maintained to record the flip status.
As the scheme is furthermore application independent and input-
variance tolerant, it is applied in the rest of this paper.

29. In this way, flipping is periodically
triggered by
 Data migrations in coarser-grained
wear leveling and
 The writes within memory lines can
be evenly distributed.

30. Case study (start-gap + enhanced ILF)
• Coarser-grained wear leveling : start – gap (memory line level)
• Bit level wear leveling : enhanced ILF

31. Table of contents
• Abstract
• Introduction
• Related work : Existing wear leveling
• Bit-level wear leveling : necessary & challenges
• Intra – line flipping (ILF)
• Basic scheme of ILF
• Flipping frequency
• Flipping granularity
• Case study : combining start-gap and enhanced ILF
• Evaluation
• Conclusion

32. Setup
Our experiments adopt all the settings suggested in the original work, including
Name Setup Name Setup
segment size 1MB swapping frequency
(segment swap)
2 × 106 writes for
segment swap
page size 4KB swapping frequency
(random page swap)
once per 512
writes
Line size 64 bytes swapping frequency
(start-gap line wear
leveling)
once per 100
write

33. Evaluation
Comparing 3 different setup in experiment
 Only start – gap (line wear leveling scheme)
 Start – gap + row shifting
 Start – gap + intra – line flipping

34. 199.2 % enhancement
39.7 % enhancement
66.8 % enhancement

35. Compare with row shifting
Row shifting Intra – line flipping
Start – gap 124.8 % 199.2 %
Random page swap 23.0 % 39.7 %
Segment swap 55.8 % 66.8 %

36. Overhead
• Row shifting :
8 bit counter + 6 bit shifting location register
(8 + 6) / 512 (each memory line) = 2.73 %
• ILF :
3 bit flip bits
3 / (4096 / 8) = 0.01 %

37. Overhead
• Row shifting :
512 bit outputs + 6 bit control signals
512 (64 to 1 mux)
• ILF :
512 bit outputs + 3 bit control signals
512 (8 to 1 mux)
The performance and power consumption of the ILF
flippers is 1/9 of the shifters used in row shifting.

38. Conclusion
• Intra – line flipping (PCM wear leveling)
• Combining with coarser – grained wear leveling strategy
(start – gap line level wear leveling)
• 34 % higher endurance
• Low storage, performance and energy overhead