Beyond Write-reduction Consideration: A Wear-leveling-enabled B+-tree Indexing Scheme over an NVRAM-based Architecture Paper presentation

1. Beyond Write-reduction Consideration: A Wear-
leveling-enabled B+-tree Indexing Scheme over
an NVRAM-based Architecture
Speaker: Po-Chuan, Chen

2. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Low-power memory technology
• B+-tree indexing scheme
• Related works
• Motivation
• Wear-leveling-aware B+-tree Scheme
• The overview of waB+ tree scheme
• Circular Node Structure
• Node-based Wear-leveling Strategy
• Global Wear-leveling Strategy
• Evaluation
• Conclusion

3. Abstract
• Non-volatile random-access memory (NVRAM)
 Feature : zero-static power consumption
 Nightmare : endurance
• Rethinking data management systems indexing scheme
• Usually using B+ tree indexing structure
• Prior studies focus on reducing the amount of write traffic to memory

4. Unfortunately
• Prior studies haven’t considered to extend the NVRAM lifespan
• All nodes within B+-tree indexing structure have different update
frequencies.
• This paper introduce “waB+ -tree”, it can evenly scatter the amount of
write traffic to the NVRAM cells.

5. Introduction
• The elements for build database and file systems
 B+ tree indexing scheme
 Effective on traditional storage devices
 Extensively applied
 Non-volatile random access memory
 Zero-static power consumption
 Fast read/write performance
 But short endurance
Prior studies focus on reducing write operation,
not on wear leveling problems

6. Problems
• Internode wear leveling problems :
• Hot leaves & cold internal nodes
• Intranode wear leveling problems :
• Shifting keys in a node

7. A wear-leveling-aware B+ tree indexing scheme
• waB+ tree has
 A circular node structure
 A node-based wear leveling strategies
 A global wear leveling strategies
• It can both solve wear leveling problems & reduce write traffic

8. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Low-power memory technology
• B+-tree indexing scheme
• Related works
• Motivation
• Wear-leveling-aware B+-tree Scheme
• The overview of waB+ tree scheme
• Circular Node Structure
• Node-based Wear-leveling Strategy
• Global Wear-leveling Strategy
• Evaluation
• Conclusion

9. Low-power memory technology
STT-RAM屬於第二代MRAM技術，能夠解決傳統MRAM結構所存在的一些問題。
目前開發的大多數MRAM，都是通過使磁場改變磁化方向來寫入數據，而磁場則是由流經隧
道磁阻（TMR）元件附近導線的電流所產生的。其漏電功耗接近於零，這是它的主要優點
STT方法使用一種極化旋轉電流使磁位元翻轉，這種技術在降低功耗的同時可以增大容量。

10. Related work
• B+ -tree indexing :
 Overflow node structure (reduce PCM write traffic)
 Predictive tree called B^(p) tree
• Write reduction :
 Unsorted (counter) / Sorted (bitmap)
 PB+ -tree (insertion area, if full go to sorted area)
Although the above solutions effectively reduced the amount of write
traffic to NVRAM, they failed to resolve the wear leveling issue for
prolonging NVRAM’s lifetime

11. B+-tree Indexing Scheme
• Because B+-tree structures, will be frequently updated while data is
inserted or deleted.
• So, it have wear leveling problems.
• A B+-tree structure has different update frequencies at not only each
node but each tree level.

12. Problems
• Internode wear leveling problems :
• Hot leaves & cold internal nodes
• Intranode wear leveling problems :
• Shifting keys in a node

13. Wear leveling issue
Intranode wear leveling
Internode wear leveling

14. Challenges
 How to evenly distribute the write requests in a “sorted” node
structure ? intranode
 How to replace old with young nodes in the B+-tree indexing
scheme for extending NVRAM’s lifespan ? internode

15. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Low-power memory technology
• B+-tree indexing scheme
• Related works
• Motivation
• Wear-leveling-aware B+-tree Scheme
• The overview of waB+ tree scheme
• Circular Node Structure
• Node-based Wear-leveling Strategy
• Global Wear-leveling Strategy
• Evaluation
• Conclusion

16. System architecture overview
 Circular Node :
• Reducing write requests
 Node-based WL :
• Evenly distributing the write request in a node
 Global WL :
• Prolonging the lifespan of NVRAM

17. System architecture overview
 Index area :
• Small size and contains a key and a data pointer
• Frequently update contains
 Data area :
• Big size
• For storing data
• Compared with index area, data area won’t wear
out soon

18. Circular Node Structure
• Goal : Moving the start point of insertion in a tree node for evenly
distributing the amount of write traffic generated by key movements
to each entry within a node.
The pivot is the position of the first insertion key in a node
The boundary is a pointer to indicate the position of the
largest or smallest key in a node.

19. Benefits
• The pivot point will reduce the number of shifting positions from n to
𝑛
2
on
average because the pivot divides a node space into two insertion area.
• The boundary pointer (i.e., BDRY) is the indicator to borrow the free
entries.
Larger than pivot right side, otherwise left side

20. To take free space …
the waB+ -tree scheme set the boundary pointer to the last (resp. first)
position of borrowed free entries in the left-side (resp. right-side) of
the pivot.

21. Node-based Wear-leveling Strategy
• Goal :
 The key stored in the pivot position is only altered when the node is
allocated, or the pivot key is deleted in the circular node structure.
 The entry storing metadata will be frequently updated because the bitmap
will be modified when a key is inserted/deleted into/from the node.
• Method : In order to resolve such intranode wear-leveling issue

22. How ?
• Node-based wear-leveling strategy will shift the metadata and pivot
to a new position for evenly distributing the amount of write traffic to
each entry when the node is reallocated.
P_n : new positions of pivot or metadata
P_s : start positions of pivot or metadata
T_allocated : how many times the node has been allocated
P_predefined : predefined number of shifting node
N_E : the totally number of entries within a node

23. Global Wear-leveling Strategy
• Goal : swap hot with cold nodes during node allocation.
• The global strategy will trigger the swapping process when the
amount of write traffic of the (to-be-allocated) free node is larger
than the threshold value derived from Equation.
AVG_writes : yje average amount of the write traffic to a memory cell
L_NVRAM : the lifespan of the NVRAM technology

24. For example
 A new node needs to be allocated
 Global strategy will estimate the amount of write traffic of the new node space
 Its amount of write traffic is larger than the value derived from Equation.
 The swapping process will be triggered to swap the new node with the (old) node
 The global wear-leveling strategy will move the cursor to the next to-be-swapped
node in the B+-tree structure.
By multiplying the new node’s allocation frequency and the
average amount of write traffic to an NVRAM cell.
The cursor through copying all keys and information from the old
node to the new node and modifying the pointer of the parent
node of the old node to reconnect with the new node.

25. The new cursor will move to
 The next right sibling
 The leftmost child node at the one lower level
 Reset to the root node of B+ -tree structure

26. Table of contents
• Abstract
• Introduction
• Background & Motivation
• Low-power memory technology
• B+-tree indexing scheme
• Related works
• Motivation
• Wear-leveling-aware B+-tree Scheme
• The overview of waB+ tree scheme
• Circular Node Structure
• Node-based Wear-leveling Strategy
• Global Wear-leveling Strategy
• Evaluation
• Conclusion

27. Experimental Enviorment
• Normal Distribution :
it contains the set of indexing key
requests collected from the randomly-
generating mechanism
• YCSB :
it’s a database testing tool to examine
the performance of NoSQL database

28. Results
• Write Distribution
• Insertion Performance
• Query Performance
• Write Statistics
• Advanced Analysis

29. Write Distribution (Normal Distribution)

30. Write Distribution (YCSB) wB+-Tree needs to maintain an
extra structure, namely slot array, to
record the sorted sequence of keys.

31. Normal Distribution

32. YCSB

33. Internode wear leveling
 B+ -tree
 PB+ -tree
 wB+ -tree
 waB+ -tree

34. Write counts (B+ -tree vs. waB+ -tree)

35. Write counts (wB+ -tree vs. waB+ -tree)

36. Write counts (PB+ -tree vs. waB+ -tree)

37. Internode wear leveling

38. Overhead analysis

39. Latency analysis
 Normal indexing key
reading/writing latency
 Boundary information and node
swapping latency
 Reading latency for pivot
comparison

40. Conclusion
• A wear-leveling-aware B+-tree indexing scheme (waB+-tree)
• Reducing the amount of write traffic to NVRAM storage and evenly
distribute the amount of write traffic to all memory cells
• Prolonging the lifespan of the NVRAM storage device by at least two
times