This paper deals with a fault detection technique for insulated-gate bipolar transistors (IGBTs) open-circuit faults in voltage source inverter (VSI)-fed induction motor drives. The novelty of this idea consists in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. The proposed method requires line-to-line voltage measurement, which provides information about switching states and is not affected by the load. The fault diagnosis scheme is achieved using simple hardware and can be included in the existing inverter system without any difficulty. In addition, it allows not only accurate single and multiple faults diagnosis but also minimization of the fault detection time to a maximum of one switching period (). Simulated and experimental results on a 3-kW squirrel-cage induction motor drive are displayed to validate the feasibility and the effectiveness of the proposed strategy.

1. ISA Transactions 51 (2012) 333–344
Contents lists available at SciVerse ScienceDirect
ISA Transactions
journal homepage: www.elsevier.com/locate/isatrans
PWM-Switching pattern-based diagnosis scheme for single and multiple
open-switch damages in VSI-fed induction motor drives
Mohamed Trabelsia,1
, Mohamed Boussaka,∗
, Moncef Gossab
a
Laboratoire des Sciences de l’Information et des Systèmes (LSIS), UMR CNRS 6168 Ecole Centrale Marseille (ECM), 38 rue Joliot Curie, 13451 Marseille Cedex 20, France
b
Unité de recherche en commande, surveillance et sûreté de fonctionnement des systèmes ‘‘ C3S’’, Ecole Supérieure des Sciences et Techniques de Tunis (ESSTT), 5 Avenue Taha
Hussein, BP 56, Bab Mnara 1008, Tunisia
a r t i c l e i n f o
Article history:
Received 31 March 2011
Received in revised form
18 October 2011
Accepted 21 October 2011
Available online 6 December 2011
Keywords:
AC motor drives
Fault detection
Line-to-line voltage sensing
Pulse-width modulation switching pattern
Voltage source inverter (VSI)
Single open-switch diagnosis
Multiple open-switch diagnosis
a b s t r a c t
This paper deals with a fault detection technique for insulated-gate bipolar transistors (IGBTs) open-
circuit faults in voltage source inverter (VSI)-fed induction motor drives. The novelty of this idea consists
in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels
during the switching times, under both healthy and faulty operating conditions. The proposed method
requires line-to-line voltage measurement, which provides information about switching states and is not
affected by the load. The fault diagnosis scheme is achieved using simple hardware and can be included
in the existing inverter system without any difficulty. In addition, it allows not only accurate single
and multiple faults diagnosis but also minimization of the fault detection time to a maximum of one
switching period (Tc ). Simulated and experimental results on a 3-kW squirrel-cage induction motor drive
are displayed to validate the feasibility and the effectiveness of the proposed strategy.
Crown Copyright © 2011 Published by Elsevier Ltd on behalf of ISA. All rights reserved.
1. Introduction
Motor drive systems fed by pulse-width modulation voltage
source inverters (PWM-VSIs) are widely used in industrial ap-
plications for variable-speed operation, such as aeronautics, rail-
way traction and robotics. The wide use of the VSIs is due to
the high switching frequency of the semiconductors [1,2] and the
use of the PWM speed controllers. Most of these inverters use
power switches based on the IGBTs because of their high efficiency,
fast switching, easy control of the gate-signal commutations, and
their ability to handle short-circuit currents for periods exceeding
10 µs [3,4].
In most cases, the drive systems are exposed to loading and hard
environmental conditions which may lead, in addition to the nat-
ural aging process, to many faults essentially related to the induc-
tion motor or inverter. Faults detection and diagnosis in induction
motors are widely investigated in the literature [5,6]. Concerning
the VSIs, in spite of their better qualities, they can present some
drawbacks and remain sensitive to abnormal operating conditions.
∗ Corresponding author. Tel.: +33 491054490.
E-mail addresses: mohamed.trabelsi@centrale-marseille.fr (M. Trabelsi),
mohamed.boussak@centrale-marseille.fr (M. Boussak), Moncef.Gossa@esstt.rnu.tn
(M. Gossa).
1 Tel.: +33 491054490.
Besides, in the previously published statistical studies, as in [7,8],
the percentage of faults for variable-speed drives was evaluated
to 63% of the user-experienced drive faults during the first year of
operation. In addition, the majority (70%) of these faults was re-
lated to power switches, such as open circuit faults, short-circuit
faults and gate-misfiring faults. Insulated-gate bipolar transistors’
(IGBTs’) open-circuit faults are usually linked to the loss of bonding
wires of the control signal or to a short-circuit fault causing rup-
ture of the transistor [3]. In the case of a gate-misfiring fault, the
inverter can operate during an important time interval, but with a
degraded output voltage and overstress on the other semiconduc-
tors, as investigated in [9,10]. An over-voltage or over-temperature
can lead to a short-circuit fault [11].
In this context, to improve the reliability and allow continuous
operation of the inverter in degradation mode during fault
conditions, several fault-tolerant strategies have been adopted,
as investigated in [1,12–17]. They consist of three essential
processes [4]. The first one is fault detection. This task is achieved
by deciding whether the inverter operates under normal or fault
conditions. The second one is fault identification. This task is
executed to identify the faulty device, and estimate the size, type
and nature of the fault. These first two processes are often called
‘‘fault diagnosis’’. After identifying the fault, isolating it consists in
removing the faulty device for safety operation. Here, it is obvious
that the implementation of fault-tolerant strategies requires first
0019-0578/$ – see front matter Crown Copyright © 2011 Published by Elsevier Ltd on behalf of ISA. All rights reserved.
doi:10.1016/j.isatra.2011.10.012

2. 334 M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
and foremost the information provided by diagnosis methods
that will be used to introduce appropriate control of the drive
system.
Concerning the IGBT open circuit fault mode, there are a
number of techniques and approaches that address the fault
detection and identification (FDI) problem. The most interesting
strategies are based on current or its variants, or voltage measure-
ments of the VSIs. In [18], the average values of the Park’s vector
currents in α − β frame and the phase-angle determination are
used to detect the fault occurrence. In [19–21], the authors suggest
the normalized DC current method. This technique has some draw-
backs when implemented in a closed-loop control scheme. The
same authors have proposed the modified normalized DC current
method. This technique has been improved in [22,23] for single
and multiple-fault modes by using fuzzy logic symptoms. Recently,
in [4], the fault detection scheme is achieved based on the oper-
ating characteristics of the BLDC motor. Other techniques, based
on discrete wavelet transform and fuzzy logic, have been investi-
gated in [10,24]. In [25], the knowledge-based model is used for
VSI diagnosis where the authors suggested two techniques using
the current vector’s instantaneous frequency and the slope of the
stator currents trajectory in the α − β frame. More recently, in
[26–28], the diagnosis of the VSIs focuses on multiple-fault occur-
rence in power switches.
The time minimization between the fault occurrence and its
detection is researched in [29–33]. In [29], the fault occurrence
is detected by analyzing the error between the measured and
estimated pole voltages in the inverter. By using a ‘‘time criterion’’
and a ‘‘voltage criterion’’, the detection time is less than 10 µs.
In [30], the fault detection is achieved by monitoring the voltages
endured by the lower switches. From simulation results, the fault
condition is detected within 2.7 ms. In [31], the pole, the phase, the
line-to-line and the neutral voltages are used for open-switch fault
diagnosis. The fault detection is accomplished in less than fourth
current period, by evaluating the residual signals deriving from
a direct comparison of the measured voltages to their respective
references. Recently, in [32], a fast diagnosis method is proposed.
It consists in combining the collector–emitter voltage of lower
switch for each inverter leg and the reference switching signals.
This task is performed based on simple hardware and without
voltage sensor. More recently, in [33], the authors proposed a
fault detection circuit for open- and short-circuit faults diagnosis.
Such a technique is based on the gate-voltage behavior at turn-On
transient of the IGBTs. The detection time is less than 3 µs.
Generally, it is strongly desirable to avoid the use of extra sen-
sors. So, the methods based on current analysis are more attrac-
tive for simplicity and cost effectiveness. Unfortunately, because
of the high fault detection time, which is about one fundamen-
tal current period, the technique based on current analysis tends
to be highly unreliable for some industrial applications (e.g., as
those based on sensorless vector control techniques), where the
speed and torque tracking is essential [34,35]. The main problem
is the high sensitivity to switching device failure. Hence, if the fault
is not quickly detected and compensated, it can lead to hard fail-
ure and to disconnecting the system. Consequently, the use of extra
sensors is justified when it is necessary to maintain the operation
of the drive system and to improve its reliability.
This paper proposes a detection and identification technique
for IGBTs’ open-circuit faults in the switching devices of PWM-
VSI-fed induction motor drives. As in [31], the measured output
quantities used for the FDI scheme are the output line-to-line
voltages, but here, a significant extension of such a technique is
proposed that does not compare the output voltages with their
respective references, but instead aims at improving the previous
effort on two aspects. The first one is that this extension requires
two voltage sensors instead of three. The second is that it permits
to reduce diagnosis time to a maximum of one switching period
instead of fourth of the fundamental current period. The new
approach is achieved by analyzing the switching pattern and the
change of the line-to-line voltage levels during the switching
times, under both healthy and faulty operating conditions. The
implementation of the proposal is realized by adding a simple
circuit into the existing inverter system. The feasibility and the
effectiveness of the proposed diagnosis scheme are verified by both
simulation and experimental results.
2. System description and VSI topology
The considered electric drive system is illustrated in Fig. 1. It
is composed of an AC/DC converter, a three-phase voltage source
inverter (Three-Phase VSI), an induction motor controlled by the
indirect stator field oriented control (ISFOC) strategy and a variable
load generated through a magnetic powder brake. The additional
blocs are dedicated to prevent the breakdowns in the dc-bus
voltage, the AC/DC converter or the DC/AC converter. Here, the
protection scheme includes circuitries to prevent overcurrent in
the inverter, overvoltage and/or undervoltage in the dc-link. When
a short-circuit fault occurs in one of the three inverter legs, the
faulty leg is isolated during a short-lived time by means of the
fast fuses or the standard protection systems that detect an over
current in the power switches or in the dc-link, [7–10].
2.1. VSI topology
The three-phase voltage source inverter is composed by
the parallel connection of three inverter legs, as shown in
Fig. 2(a). It uses a constant voltage source provided by a voltage
source rectifier and a capacitive DC-link. Each leg features two
semiconductor switches (TK , TK+3 k = 1, 2, 3) with antiparallel
connected freewheeling diodes (DK , DK+3) used to provide a
negative current path through the switch. The VSI is controlled
by binary gate signals (SK , SK+3) ∈ {0, 1}. The gate signal SK or
SK+3 is equal to ‘‘1’’ when the switch is conducting and equal to
‘‘0’’ when the switch is open. Note that SK and SK+3 must work in
a complementary way to prevent the short circuit of the dc-bus
voltage and to avoid both switches to be open producing undefined
output voltages. For a healthy condition, the positive alternation of
the phase current in (n = a, b, c) is built by means of the transistor
TK and the diode DK+3. During the negative alternation, the phase
current in is built by TK+3 and DK . Without considering the dead
time, DK+3 or DK is turned On at the same instant when TK or TK+3
is turned Off, respectively. According to different combinations of
the switching states SK and SK+3, the inverter can generate three
different output line-to-line voltage-levels (vdc , 0, −vdc ).
For illustration, consider the two inverter legs a and b, as they
are shown in Fig. 2(b), which illustrates which semiconductor is
conducting (the transistor or the diode), the polarity of the output
phase currents and the corresponding output line-to-line voltage.
Here, these two inverter legs are controlled by S1 and S2. Therefore,
they feature four different switching states, which are given in
Table 1. To each switching state corresponds one output line-to-
line voltage level. For example, consider the first case (case 1)
shown in Fig. 2(b). In this case, the switching state is defined by
S1 and S2 = 1. Hence, leg a is connected to the negative potential
through the diode D4, while leg b is connected to the positive
potential through the diode D2. So, the output line-to-line voltage
uab generated by the inverter is equal to −vdc . However, under
normal conditions and neglecting the dead time introduced in the
switching pattern, the general expression of the output line-to-line
voltages can be given by

uab
ubc
uca

= vdc

1 −1 0
0 1 −1
−1 0 1
 
S1
S2
S3

. (1)

3. M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344 335
Fig. 1. Electric drive system structure.
a b
c
a
bia > 0 ia > 0 ia < 0 ia < 0
ib < 0 ib > 0 ib > 0 ib < 0a
b
a
b b
a
Vdc
-Vdc
ia ib
uab
t
a
b
Fig. 2. (a) Inverter topology. (b) Two inverter legs conduction states when (Case 1) uab = +vdc , ia > 0 and ib < 0, (Case 2) uab = 0, ia > 0 and ib > 0, (Case 3)
uab = −vdc , ia < 0 and ib > 0, (Case 4) uab = 0, ia < 0 and ib < 0.
Table 1
Switching state and line-to-line voltage under normal conditions.
Case n° Gating signals Output current sign Semiconductor conducting Output line-to-line voltage
S1 S2 ia ib uab
1 0 1 >0 <0 D4 and D2 −vdc
2 1 1 >0 >0 T1 and T2 0
3 1 0 <0 >0 D1 and D5 +vdc
4 0 0 <0 <0 T4 and T5 0
Note that Eq. (1) is valid if all switches of the inverter are
faultless. Under faulty conditions, these relations are no longer
valid and the estimated line-to-line voltages do not correspond any
more to the real ones. Also, the applicability of Eq. (1) depends,
essentially, on the knowledge of the inverter switching pattern
resulting from an appropriate modulation strategy. This work is
focused on a sine-triangle modulation technique (SPWM). Hence,
the modulation of each leg is generated by comparing a voltage
reference and a triangular carrier.
3. Post-fault behavior and diagnosis reasoning for the inverter
The aim of the present section is double. The first consists in
studying the influence of the power semiconductors’ faults on
the switches’ conduction states. The second concerns the fault
detection principle. Indeed, most of the faults which can occur
within an inverter are short- and open-circuit faults of the power
switches. The standard protection included in the electric drive
system can detect the over-current due to short circuit faults. In

4. 336 M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
Fig. 3. Switches’ conduction states and current paths under an open circuit fault of the upper transistor T1: (a) ia > 0, ib > 0, S1 = 1 and S2 = 1. (b) ia > 0, ib > 0, S1 = 1
and S2 = 0. (c) ia > 0, ib > 0, S1 = 1 and S2 = S5 = 0 (dead time in leg b). (d) ia > 0, ib < 0, S1 = 1 and S2 = 1. (e) ia > 0, ib < 0, S1 = 1 and S2 = 0.
(f) ia > 0, ib < 0, S1 = 1 and S2 = S5 = 0 (dead time in leg b).
this case, the faulty switch or faulty leg is immediately isolated by
the fast-acting fuses or the circuit breakers and the fault will result
in an open circuit of the power switch or the inverter leg.
In this work, only the single or multiple open-circuit faults
(due to gates misfiring) will be considered. Also, the output line-
to-line voltages of the inverter are used to perform the fault
detection and diagnosis. Indeed, after the fault occurrence, the
conduction intervals of the by-pass diodes change. Thus, the
voltage components given by Eq. (1) are no longer valid. Based
on this fact, the open circuit fault detection can be achieved by
evaluating the error between the actual line-to-line voltages and
those obtained from Eq. (1).
3.1. Post-fault behavior for an open circuit of the upper switch in leg
a (T1)
To analyze the faulty IGBT’s impact on the commutating
sequences of the diodes, let’s consider Fig. 3 which presents the
switches conduction states and current paths of two inverter legs
when the upper transistor T1 is faulty. The switching state S2 =
S5 = 0 corresponds to the dead time interval of the second
inverter leg. The open circuit fault causes a loss of the phase current
reversibility of the upper switch T1. Therefore, the current of the
faulty leg becomes connected to the negative potential of the dc-
bus voltage through bypass diode D4, when gate signal S1 is at high
level and phase current ia is positive. During the interval where
phase current ia is negative, the inverter’s behavior is the same
as under healthy operating conditions. Here, it is clear that the
measured line-to-line voltage uab depends on the switching-gate
signals and the sign of phase current ia. So, line-to-line voltage uab
is interpreted as follows:
if ia > 0 and S1 = S2 = 1 (∀ sign ib) ⇒ uab = −vdc (2)
if ia > 0 and S1 = 1 and S2 = 0 (∀ sign ib) ⇒ uab = 0 (3)
if ia < 0 and S1 = S2 = 1 (∀ sign ib) ⇒ uab = 0 (4)
if ia < 0 and S1 = 1 and S2 = 0 (∀ sign ib) ⇒ uab = vdc . (5)
Table 2 summarizes the different possible states of the line-to-
line voltage uab for a healthy inverter and when an open circuit
fault of the upper IGBT T1 occurs, where ‘‘fault’’ denotes the cases
in which the fault can be detected and ‘‘no-fault’’ denotes the cases
in which the fault is undetectable.
Here, it is important to underline that the fault can be identified
in four cases according to the phase currents signs and the
switching pattern. These cases correspond to a positive alternation
of phase current ia and when gate signal S1 is at high level.
Otherwise, the fault is undetectable.
3.2. Post-fault behavior for an open circuit of the lower switch in leg
a (T4)
Fig. 4 presents the switches’ conduction states and current
paths in two inverter legs when the lower transistor T4 is faulty.
With similar observations, when current ia is negative and gate
signal S4 is at high level, the phase current of the faulty leg
becomes connected to the positive potential of the dc-bus voltage
through bypass diode D1. Otherwise, if phase current ia is positive,
the inverter operates under normal conditions and the drive
system behavior is the same as under healthy operating conditions.
Measured line-to-line voltage uab can be changed according to
the switching pattern and the sign of the phase current uab,
therefore:
if ia > 0, S1 = 0 (S4 = 1) and S2 = 1 (∀ sign ib)
⇒ uab = −vdc (6)
if ia > 0, S1 = 0 (S4 = 1) and S2 = 0 (∀ sign ib) ⇒ uab = 0 (7)
if ia < 0, S1 = 0 (S4 = 1) and S2 = 1 (∀ sign ib) ⇒ uab = 0 (8)
if ia < 0, S1 = 0 (S4 = 1) and S2 = 0 (∀ sign ib)
⇒ uab = vdc . (9)
Table 3 presents line-to-line voltage uab for both a healthy
inverter and when an open circuit fault of the lower IGBT T4 occurs.
Similarly to the previous case, the fault of the lower transistor
can be detected in four cases (denoted by: Fault). These cases
correspond to a negative alternation of phase current ia and when
gate signal S4 is at high level. During the positive alternation of the
phase current, the fault is undetectable.
3.3. Post-fault behavior for simultaneous open-switches (e.g. T1
and T5)
Other possible fault combinations can appear in the inverter
legs (e.g. leg a and leg b); for example, the double fault involving

5. M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344 337
Table 2
Line-to-line voltage for healthy inverter and when an open circuit fault of the upper switch T1 occurs.
ia ib S1 S2 Healthy inverter T1 is faulty
D1 D4 D2 D5 uab D1 D4 D2 D5 uab
>0 >0
1 1 Off Off Off Off 0 Off On Off Off −vdc Fault
1 0 Off Off Off On vdc Off On Off On 0 Fault
0 1 Off On Off Off −vdc Off On Off Off −vdc No fault
0 0 Off On Off On 0 Off On Off On 0 No fault
Dead time S1 = S4 = S2 = S5 = 0 Off On Off On 0 Off On Off On 0 No fault
>0 <0
1 1 Off Off On Off 0 Off On On Off −vdc Fault
1 0 Off Off Off Off vdc Off On Off Off 0 Fault
0 1 Off On On Off −vdc Off On On Off −vdc No fault
0 0 Off On Off Off 0 Off On Off Off 0 No fault
Dead time S1 = S4 = S2 = S5 = 0 Off On On Off −vdc Off On On Off −vdc No fault
Fig. 4. Switches’ conduction states and current paths under an open circuit fault of the lower transistor T4: (a) ia < 0, ib < 0, S1 = 0 and S2 = 1. (b) ia < 0, ib < 0, S1 = 0
and S2 = 0. (c) ia < 0, ib < 0, S1 = 0 and S2 = S5 = 0 (dead time in leg b). (d) ia < 0, ib > 0, S1 = 0 and S2 = 1. (e) ia < 0, ib > 0, S1 = 0 and S2 = 0.
(f) ia < 0, ib > 0, S1 = 0 and S2 = S5 = 0 (dead time in leg b).
Table 3
Line-to-line voltage for a healthy inverter and when an open circuit fault of the lower switch T4 occurs.
ia ib S1 S2 Healthy inverter T4 is faulty
D1 D4 D2 D5 uab D1 D4 D2 D5 uab
<0 <0
1 1 On Off On Off 0 On Off On Off 0 No fault
1 0 On Off Off Off vdc On Off Off Off vdc No fault
0 1 Off Off On Off −vdc On Off On Off 0 Fault
0 0 Off Off Off Off 0 On Off Off Off vdc Fault
Dead time S1 = S4 = S2 = S5 = 0 On Off On Off 0 On Off On Off 0 No fault
<0 >0
1 1 On Off Off Off 0 On Off Off Off 0 No fault
1 0 On Off Off On vdc On Off Off On vdc No fault
0 1 Off Off Off Off −vdc On Off Off Off 0 Fault
0 0 Off Off Off On 0 On Off Off On vdc Fault
Dead time S1 = S4 = S2 = S5 = 0 On Off Off On vdc On Off Off On vdc No fault
one inverter leg ((T1 and T4) or (T2 and T5)) or the double fault
involving two inverter legs ((T1 and T2), (T4 and T5), (T1 and T5)
or (T2 and T4)). The idea to study these faulty cases is to evaluate
the effectiveness and robustness of the proposed strategy against
the multiple open-switches, in particular the line-to-line voltage
change after the fault occurrence. For instance, let’s suppose
simultaneous faults of transistors T1 and T5. According to the phase
currents’ signs and the switching pattern, Table 4 covers only the
cases in which the fault detection can be achieved. Note that line-
to-line voltage uab takes the same states (same values) compared
to the cases of the single fault of the upper transistor in the first
inverter leg and the single fault of the lower transistor in the second
inverter leg. So, the detection of simultaneous multiple faults
involving one inverter leg or two inverter legs can be achieved
based on the same information resulting from a single open switch.
Therefore, only the measurement of the line-to-line voltage is
necessary to diagnose four IGBTs within two inverter legs.
4. Proposed FDI hardware for IGTBs open-circuit faults
From the above analysis, it can be concluded that open-circuit
fault information could be obtained by monitoring the output line-
to-line voltage levels and knowing the control signals applied on
the gates of the switching devices. The design of the proposed

6. 338 M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
&
&
&
&
Fig. 5. Proposed hardware for IGBTs open-circuit fault detection and identification.
Table 4
Line-to-line voltage for a healthy inverter and for a simultaneous open circuit fault
of T1 and T5. (Only the cases in which the fault can be detected are presented.)
ia ib S1 S2 Healthy
inverter
T1and T5 are faulty
uab uab
>0 >0
1 1 0 vdc Fault
1 0 vdc 0 Fault
Dead time S1 = S4 = S2 = S5 = 0 0 0 No fault
>0 <0
1 1 0 −vdc Fault
1 0 vdc −vdc Fault
0 0 0 −vdc Fault
Dead time S1 = S4 = S2 = S5 = 0 −vdc −vdc No fault
<0 <0
1 0 vdc 0 Fault
0 0 0 −vdc Fault
Dead time S1 = S4 = S2 = S5 = 0 0 0 No fault
hardware is illustrated in Fig. 5. It consists of three subcircuits: line-
to-line voltage sensing and adaptation, comparison and voltage-
level detection, and fault signals generation.
The first task (line-to-line voltage sensing and adaptation) is
achieved by measuring the line-to-line voltage. Its adaptation can
be realized by a resistive voltage divider. Here, it should be noted
that the measured line-to-line voltage is classified as three voltage
levels. These three voltage levels are defined as positive level (vdc ),
zero level (0), and negative level (−vdc ).
This proposed FDI strategy is achieved by the detection of the
zero level change after the fault occurrence (from zero level (0)
to positive level (vdc ), or from zero level (0) to negative level
(−vdc )). However, the second task (comparison and voltage level
detection) is performed by using a simple circuit based on two
voltage comparators and two transistors. In this circuit, the output
of the resistive voltage divider is compared to a negative reference
voltage (Comp-I) to detect the fault occurrence in transistor T1 or
T5, and it is compared to a positive reference voltage (Comp-II)
to detect an open-circuit fault in T2 or T4. For instance, consider
the first comparator (Comp-I): if ‘‘uab’’ is greater than the negative
reference voltage, then the line-to-line voltage is considered as
positive level. Contrariwise, it is considered as negative level if
‘‘uab’’ is lower than the negative reference voltage. The difference
between normal and fault condition is that the zero level (0) is not
the same before and after the fault occurrence and it changes its
sign according to the faulty switch.
Furthermore, considering that the line-to-line voltage is
affected by the dc-link voltage ripple, the voltage levels will not
be exactly zero, (vdc ) or (−vdc ). Thus, the negative and positive
reference voltage must be carefully selected by running the electric
drive system under normal and fault conditions.
Finally, to detect whether the inverter presents an open-circuit
fault, a simple logical circuit is adopted. In this circuit, the detection
of the fault occurrence is achieved by combining the output of each
transistor and the reference switching signals applied on the gates
of the power semiconductors. According to the faulty switch, the
fault detection signals can be expressed as follows:
FT1
= S1 AND S2 AND VTD1
(10)
FT5
= S1 AND S2 AND VTD1
(11)
FT2
= S1 AND S2 AND VTD2
(12)
FT4
= S1 AND S2 AND VTD2
(13)
where FTi
are the fault detection signals and Si are the switching
gate signals. VTD1
, VTD2
are the output voltage levels of the first and
second diagnosis transistor of the ‘‘comparison and voltage-level
detection’’ subcircuit, as shown in Fig. 5.
In Eqs. (10)–(13), the detection of the open-circuit fault
occurrence in the power transistors is achieved by combining
the gate control signals and the output quantities given by the
subcircuit ‘‘comparison and voltage-level detection’’. These last
quantities are the results of the line-to-line voltage levels’ changes
before and after fault occurrence. For example, consider the upper

7. M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344 339
Fig. 6. Diagnosis hardware, voltage sensor and IGBTs-switching delay times
compensation on the fault detection signal FT1
.
IGBT in first inverter leg (T1). Under normal conditions, line-to-line
voltage uab is equal to zero or vdc when phase current ia is positive
and S1 is at a high level. But, after the fault occurrence, line-to-line
voltage uab becomes equal to zero or −vdc although control gate
signal S1 is at a high level. Consequently, the output voltage of the
diagnosis transistor TD1
reaches a high level and detection signal FT1
indicates the fault occurrence of transistor T1, as given in Eq. (10).
Here, it is important to announce that the fault information can be
obtained when S1 = S2 = 1 and uab = −vdc or when S1 = S2 = 0
and uab = 0. In this work, only fault information when S1 = S2 = 1
and uab = −vdc is considered, to simplify the detection circuit and
achieve all possible fault combinations which can appear in two
inverter legs.
The open-circuit fault detection and identification in the other
IGBTs can be interpreted with similar analysis. In addition, the
diagnosis of multiple IGBTs open-circuit faults can be achieved
using the same hardware and the same fault signals resulting from
single open-switch damage.
4.1. Compensation of the delay time propagation
In real operating conditions, false alarms can be present in the
fault output signals FTi
(i = 1, . . . , 6) that are due to the delay time
induced by the IGBTs turn-On and turn-Off processes, and the delay
time of the proposed diagnosis strategy (comparator, transistor
and voltage sensor). Fig. 6 shows the switching sequences during
a fundamental current period and the principle of delay time
compensation, to avoid false alarms of fault detection signal FT1
.
In this figure, the time interval between t1 and t2 is due to the
turn-On time of the power switch T1. The other interval, between t3
and t4, corresponds to the response time of the proposed hardware
and the voltage sensor. The false alarms appear during the interval
when S1 and S2 are both in ‘‘On’’ state and VTD1
is at high level.
They can be avoided by delaying the switching signal S1 used for
fault diagnosis process. Hence, the total delay time which must
be introduced on the switching signal S1 (as for the switching
signal S2) is calculated as
tOn + tpc + ts < tdelay-On < tsk-min (14)
tOff + tpc + ts < tdelay-Off < tsk-min (15)
where, tdelay-On and tdelay-Off indicate the necessary delay times that
must be introduced on the switching signals SK . tOn and tOff denote
the turn-On time (including the turn-On delay time and the rise
time) and the turn-Off time (including the turn-Off delay time and
the fall time) of the switching devices, respectively. tpc and tS are
the delay times of the proposed hardware and the used voltage
sensor, respectively. tsk-min indicates the minimal pulse width and
is given by
tsk-min =
Tc
2
(1 − Mi) (16)
where Tc and Mi are the switching period and the modulation
index, respectively.
Finally, instead of using gate signals S1 and S2 for fault diagnosis
process, the new delayed switching signals S′
1 and S′
2 can be
adopted. Therefore, the new fault detection signals become
F′
T1
= S′
1 AND S′
2 AND VTD1
(17)
F′
T5
= S′
1 AND S′
2 AND VTD1
(18)
F′
T2
= S′
1 AND S′
2 AND VTD2
(19)
F′
T4
= S′
1 AND S′
2 AND VTD2
. (20)
In this work, an integrated power module (IPM)-SKM50GB123D
from SEMIKRON is used in the experimental system. The typical
values of turn-On time and turn-Off time are defined as 0.13 µs
and 0.445 µs, respectively. The delay time of the used voltage
sensor is less than 50 ns. In addition, by using fast comparators
and diagnosis transistors, tpc is about 0.5 µs. Therefore, tdelay-On
and tdelay-Off are evaluated to 0.68 µs and 0.995 µs, respectively.
Here, it is important to underline that the IGBT turn-On and turn-
Off delay times (tOn and tOff) depend on the actual operating
conditions of the switching devices. However, tdelay-On and tdelay-Off
must be carefully selected regarding the motor load current, the
actual dc-bus voltage, the IGBT power rating and the IGBT junction
temperature. For these reasons, the values of both tdelay-On and
tdelay-Off are selected to 2 µs, keeping a safety margin of 1 µs
compared to the calculated value.
The delay time compensation is achieved by using an RC-
circuit, as shown in Fig. 5. Therefore, for practical implementation,
the values of the used resistor (R) and capacitor (C) are fixed to
1.33 k and 1.5 nF, respectively, corresponding to 2 µs as a delay
time.
5. Performances evaluation results
5.1. Simulation results
To check the performance of the proposed fault detection
technique, a simulation software has been set up by using
Matlab/Simulator. Under normal operating conditions and for
faulty states, the inverter has been modeled with a real model of
the power switches and the by-pass diodes. A dead time of 4 µs
has introduced to prevent short-circuits within the inverter legs.
The diagnosis circuit has been set up by using the analog devices
of Simulink/Simscape. All tests have been carried out in permanent
operating conditions. The parameters used in both simulation and
experimental tests are displayed in Table 5.
The waveforms given in Fig. 7 show the three phase currents,
the line-to- line voltage uab, the zoomed line-to-line voltage,
the fault detection signal FT1
and the commanded fault for an
open circuit fault of the upper IGBT T1. A fault condition is
caused in transistor T1, at t0 = 0.88 s, by keeping gate-signal
S1 permanently in ‘‘Off’’ state. After the fault occurrence, phase
current ia suddenly drops to zero and is flowing only in a negative
direction. As announced in Section 4, the proposed diagnosis
strategy is achieved by detecting the zero level change. However,
in Fig. 7(b), it is observed that the line-to-line voltage presents
a great drop from zero-level to negative-level. Consequently,

8. 340 M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
ia ib ic
zoomed voltage,
Blue: without fault, Red: under fault
a
b
c
Fig. 7. Simulation results for an open-circuit fault in the upper IGBT (T1). (a) Phase
currents. (b) Line-to-line voltage uab. (c) Fault detection signal and commanded
fault.
fast fault detection is accomplished, since it takes only 200 µs
(fault detection = 0.8802 s) to detect the fault condition in the
switching device T1.
A second test is displayed in Fig. 8 which presents the same
waveforms as the previous test, but here, the fault condition is
applied to the lower switch in first inverter leg (transistor T4).
The fault is simulated at t0 = 0.91 s when phase current ia is
positive, by keeping gate-signal S4 permanently in ‘‘Off’’ state. Here,
it is important to underline that the positive alternation of current
ia is obtained only through transistor T1 or diode D4. However,
when ia is positive, the inverter’s behavior under T4 open-circuit
fault is the same as under normal conditions. Consequently, the
fault information can be obtained only after current zero-crossing.
Fault detection is accomplished at t1 = 0.9172 s, taking 150 s as
fault detection time. (The fault detection time is calculated from
the first instant in which transistor T4 is supposed to be in ‘‘On’’
state.)
Similar results have been obtained for multiple open-circuit
faults of the upper transistor T1 in the first inverter leg and of
the lower transistor T5 in the second inverter leg, as displayed in
Fig. 9. A fault condition is caused in transistor T5 at t0 = 0.87 s.
Its detection is achieved after a short-lived interval, since it takes
only 170 µs. The fault condition in IGBT T5 occurs at t1 = 0.8744 s
when phase current ia crosses zero. Fast fault detection is achieved
at t1 = 0.87453 s, taking 130 µs as fault detection time.
ia ib ic
zoomed voltage,
Blue: without fault, Red: under fault
b
c
a
Fig. 8. Simulation results for an open-circuit fault in the lower IGBT (T4). (a) Phase
currents. (b) Line-to-line voltage uab. (c) Fault detection signal and commanded
fault.
Table 5
Technical data of induction motor and inverter.
Induction motor
Rated power 3 kW
Rated speed 1430 r/m
Pairs of poles np = 2
Rated frequency 50 Hz
Rs = 2.3 , Rr = 1.55 , Ls = Lr = 0.261 H, Lm = 0.249 H, J =
0.02 kg m2
, f = 710−4
N m s/rad
Operating speed 1000 rpm (simulation)
1000 rpm (experimental)
Inverter: IPM-SKM50GB123D
DC-bus voltage 540 V
Turn-On time 0.13 µs
Turn-Off time 0.445 µs
Dead time 4 µs
Duty-cycle frequency 5 kHz
5.2. Experimental results
In order to prove the feasibility of the proposed FDI strategy,
an experimental evaluation has been performed using a 3-kW
induction motor (IM), coupled to a magnetic-powder brake to
load profile change. The configuration of the experimental setup
is shown in Fig. 10. The test bench is displayed in Fig. 11. The
relevant parameters of the induction motor and the inverter

9. M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344 341
ia ib ica
b
c
Fig. 9. Simulation results for multiple open-circuit faults of the upper IGBT (T1)
and the lower IGBT (T5). (a) Phase currents. (b) Line-to-line voltage uab. (c) Fault
detection signals.
used in the experiments are given in Table 5. The proposed
diagnosis strategy is tested in closed-loop for the ISFOC control.
Hence, the control algorithm is implemented through a dSPACE
DS1104 real-time controller board running at 20 kHz as sampling
frequency. The three-phase inverter is built with SEMIKRON IGBTs
Fig. 11. Experimental platform.
components (SKM50GB123D). The switching signals for the six
IGBTs are generated from the dSPACE DS1104 board through an
adaptation stage using an IR2130 3-phase bridge driver. The PWM-
inverter is running with a switching frequency of 5 kHz. To create
the open-switch faults, magnetic relays are used, that are also
controlled from the dSPACE DS1104. The experimental tests have
been carried out under several fault conditions: single open-circuit
fault in an inverter leg and multiple open-circuit faults involving
two transistors in two inverter legs. All experiments have been
performed during permanent operating conditions.
Fig. 12 shows the experimental waveforms of the switching
process for an IGBT. As announced earlier, tOn and tOff denote the
turn-On time (including the turn-On delay time and the rise time)
and the turn-Off time (including the turn-Off delay time and the
fall time) of the switching device, respectively. Fig. 13 shows the
line-to-line voltage uab, the phase current ia and the fault detection
signal FT1
under healthy operating conditions. Here, it is observed
Fig. 10. Experimental setup.

10. 342 M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
Fig. 12. Experimental waveforms of the switching process for an IGBT.
that the false alarms appear during the negative sequences of line-
to-line voltage uab, notably, during the turn-On process of IGBT
T1, as shown in Fig. 14 which corresponds to the theoretical study
shown in Fig. 6. This drawback has been avoided by introducing a
delay time on the switching signals used for fault diagnosis process.
The experimental waveforms of the switching signals, before and
after delay time compensation, are displayed in Fig. 15. In this
figure, S is the actual switching signal applied on the gate of the
IGBT and S′
is the delayed signal used for FDI process. Here, the
delay time, which must be introduced on the switching signal, is
about 2 µs.
The accurate open-circuit fault diagnosis using the proposed
hardware is illustrated in Figs. 16–18. Fig. 16 shows the phase
current ia, the line-to-line voltage uab and the fault detection signal
FT1
for an open-circuit fault of IGBT T1. After fault occurrence, phase
current ia suddenly drops to zero. Also, it is observed that the line-
to line voltage uab is affected by the fault condition and becomes
equal to zero or −vdc during the positive alternation of phase
current ia and when switching signal S1 is in ‘‘On’’ state. Hence, fast
fault detection in IGBT T1 is achieved in less than one switching
period (fault detection time is close to200 µs).
Fig. 17 presents the experimental results of the phase current ia,
of the line-to-line voltage uab and of the fault detection signal FT4
for an open circuit of IGBT T4. After fault occurrence, phase current
ia is flowing only in a positive direction. Furthermore, line-to-line
voltage quickly shows the presence of this fault. Once more, fast
fault detection is achieved in less than one switching period.
Another experiment is displayed in Fig. 18 which shows the
phase currents (ia, ib) and the fault detection signals (FT1
, FT5
)
for multiple open-circuit faults of two transistors involving two
inverter legs (leg a and leg b).
In this experiment, the fault condition is caused in transistors
T1 and T5 by keeping gate-signals S1 and S5 permanently in ‘‘Off’’
state. As a consequence, current ia and current ib are flowing only
in negative and positive directions, respectively. Similar to the
previous cases, fast fault detection of both upper IGBT T1 and lower
IGBT T5 is achieved after one switching period ( t ≈ 200 µs).
To conclude this section, the following criteria are selected to
evaluate and compare the performance of the proposed diagnosis
strategy [3]:
(1) Effectiveness: Considering simulation and experimental re-
sults, it is shown that the proposed method indicates success-
fully single and multiple IGBTs open-circuit faults.
(2) Resistivity against false alarms: As discussed earlier, false
alarms may occur during switching times, due to IGBT-
switching process and response times of the used diagnosis
hardware and voltage sensor. This drawback has been avoided
Fig. 13. Experimental waveforms of the line-to-line voltage uab, the phase current
ia and the fault detection signal FT1
without delay time compensation (healthy
inverter).
Fig. 14. Experimental waveforms of the switching signals S1 and S2, the line-to-line
voltage uab and the fault detection signal FT1
during the switching times (healthy
inverter).
Fig. 15. Experimental results of the delay time compensation on a switching signal.
by introducing the necessary delay time on the PWM-
switching signals used for fault diagnosis process. Hence, the
required delay time has been calculated according to these
facts, permitting an accurate fault diagnosis of the open-circuit
fault.
(3) Detection time: based on the proposed diagnosis technique,
the delay time between the fault occurrence and its detection
is minimized to a maximum of one switching period (Tc ).

11. M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344 343
Fig. 16. Experimental results of the phase current ia, the line-to-line voltage uab
and the fault detection signal FT1
under an open-circuit fault of IGBT T1.
Fig. 17. Experimental results of the phase current ia, the line-to-line voltage uab
and the fault detection signal FT4
under an open-circuit fault of IGBT T4.
Fig. 18. Experimental results of the phase currents (ia and ib) and the fault detection
signals (FT1
and FT5
) under multiple open-circuit faults of IGBTs T1 and T5.
(4) Implementation effort: The fault diagnosis process is based on
simple hardware and can be included in an existing inverter
system. Although it is only applied in sinusoidal PWM, it can be
applied to most commercial inverters using other modulation
methods, such as space-vector PWM. A disadvantage of this
strategy is that it needs to incorporate extra voltage sensors
in the system.
(5) Tuning effort: The proposal implies an accurate calculating of
the delay time which must be introduced on the switching
signals to avoid false alarms, since it varies according to the
IGBT switching process, the used hardware and the voltage
sensor.
6. Conclusion
In this paper, a PWM-Switching pattern based diagnosis scheme
has been proposed to detect open-switch damages in the switching
devices of VSI-fed induction motor drives. The procedure of
fault detection and identification is achieved by analyzing the
switching pattern and the change of the line-to-line voltage-levels
during the switching times. In previous works, it is expected
that the technique based on line-to-line voltage measurement
requires three sensors and is achieved over a fourth of the
fundamental current period for fault detection. This work shows
the effectiveness of the proposed FDI, but only with two voltage
sensors and over a maximal one switching period to detect single
and multiple IGBTs-open-circuit faults in the inverter. Moreover
the proposed hardware can be included in an existing electric drive
system without any complexity. Simulation and experimental
results performed on a 3-kW induction motor have shown the
validity and feasibility of the proposed strategy.
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