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A LOW-COST HARDWARE ARCHITECTURE FOR ILLUMINATION ADJUSTMENT
IN REAL-TIME APPLICATIONS
ABSTRACT
For real-time surveillance and safety applications in intelligent transportation systems,
high-speed processing for image enhancement is necessary and must be considered. In this
paper, we propose a fast and efficient illumination adjustment algorithm that is suitable for low-
cost very large scale integration implementation. Experimental results show that the proposed
method requires the least number of operations and achieves comparable visual quality as
compared with previous techniques. To further meet the requirement of real-time image/video
applications, the 16-stage pipelined hardware architecture of our method is implemented as an
intellectual property core. Our design yields a processing rate of about 200 MHz by using TSMC
0.13-μmTechnology. Since it can process one pixel per clock cycle, for an image with a
resolution of QSXGA (2560 × 2048), it requires about 27 ms to process one frame that is
suitable for real-time applications. In some low-cost intelligent imaging systems, the processing
rate can be slowed down, and our hardware core can run at very low power consumption.

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A low cost hardware architecture for illumination adjustment in real-time applications

  • 1. A LOW-COST HARDWARE ARCHITECTURE FOR ILLUMINATION ADJUSTMENT IN REAL-TIME APPLICATIONS ABSTRACT For real-time surveillance and safety applications in intelligent transportation systems, high-speed processing for image enhancement is necessary and must be considered. In this paper, we propose a fast and efficient illumination adjustment algorithm that is suitable for low- cost very large scale integration implementation. Experimental results show that the proposed method requires the least number of operations and achieves comparable visual quality as compared with previous techniques. To further meet the requirement of real-time image/video applications, the 16-stage pipelined hardware architecture of our method is implemented as an intellectual property core. Our design yields a processing rate of about 200 MHz by using TSMC 0.13-μmTechnology. Since it can process one pixel per clock cycle, for an image with a resolution of QSXGA (2560 × 2048), it requires about 27 ms to process one frame that is suitable for real-time applications. In some low-cost intelligent imaging systems, the processing rate can be slowed down, and our hardware core can run at very low power consumption.