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An Overview Study on USB OTG Device ISP1761

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An Overview Study on USB OTG Device ISP1761

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An Overview Study on USB OTG Device ISP1761

  1. 1. An Overview Study on USB OTG Device ISP1761 <ul><li>Source: ST-NXP Wireless </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>An Overview Study on USB OTG Device ISP1761 </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Features </li></ul></ul><ul><ul><li>Applications and Connection Diagram </li></ul></ul><ul><ul><li>Internal Block Diagram, Hub, Clock. </li></ul></ul><ul><ul><li>Power supply connection and Interrupt </li></ul></ul><ul><ul><li>Endpoint Description, OTG State Diagram. </li></ul></ul><ul><li>Content </li></ul><ul><ul><li>18 pages </li></ul></ul>
  3. 3. Features <ul><li>It supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). </li></ul><ul><li>The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream port, an upstream port or an OTG port. </li></ul><ul><li>Supports OTG Host Negotiation Protocol (HNP) and </li></ul><ul><li>Session Request Protocol (SRP) </li></ul><ul><li>Multitasking support with virtual segmentation feature and High-speed memory controller </li></ul><ul><li>Generic processor interface to most CPUs, such as Hitachi SH-3 and SH-4, NXP XA,…Etc and PowerPC Reduced Instruction Set Computer (RISC) processors. </li></ul><ul><li>Supports Programmed I/O (PIO) and Direct Memory Access (DMA). </li></ul><ul><li>Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI. </li></ul><ul><li>Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for </li></ul><ul><li>low-power core) </li></ul><ul><li>Hybrid-power mode: VCC(5V0) (can be switched off), VCC(I/O) (permanent) </li></ul><ul><li>Target total current consumption: </li></ul><ul><ul><li>Normal operation; one port in high-speed active: ICC < 100 mA when the internal charge pump is not used </li></ul></ul><ul><ul><li>Suspend mode: ICC(susp) < 150 mA at ambient temperature of +25 °C </li></ul></ul>
  4. 4. OTG and Peripheral Controller-Specific Features <ul><li>OTG controller-specific features : </li></ul><ul><li>OTG transceiver: fully integrated; </li></ul><ul><li>Supports HNP and SRP for OTG dual-role devices </li></ul><ul><li>HNP: status and control registers for software implementation </li></ul><ul><li>SRP: status and control registers for software implementation </li></ul><ul><li>Programmable timers with high resolution (0.01 ms to 80 ms) for HNP and SRP </li></ul><ul><li>Supports external source of VBUS </li></ul><ul><ul><li>Peripheral controller-specific features : </li></ul></ul><ul><li>High-performance USB peripheral controller with integrated Serial Interface Engine (SIE), FIFO memory and transceiver </li></ul><ul><li>Supports auto Hi-Speed USB mode discovery and Original USB fallback capabilities </li></ul><ul><li>Supports high-speed and full-speed on the peripheral controller </li></ul><ul><li>Bus-powered or self-powered capability with suspend mode </li></ul><ul><li>Slave DMA, fully autonomous and supports multiple configurations </li></ul><ul><li>Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT </li></ul><ul><li>endpoint </li></ul><ul><li>Integrated 8 kB memory </li></ul><ul><li>Software-controllable connection to the USB bus, SoftConnect1 </li></ul>
  5. 5. Applications <ul><li>Host/peripheral roles: </li></ul><ul><li>Mobile phone to/from: </li></ul><ul><li>Digital still camera to/from: </li></ul><ul><li>Printer to/from: </li></ul><ul><li>Oscilloscope to/from: </li></ul><ul><li>Personal digital assistant to/from: </li></ul><ul><li>Mobile phone: upload/download files </li></ul><ul><li>MP3 player: upload/download songs </li></ul><ul><li>Scanner: scan pictures </li></ul><ul><li>Mass storage: upload/download files </li></ul><ul><li>Global Positioning System (GPS): obtain directions, mapping information </li></ul><ul><li>Digital still camera: upload pictures </li></ul>
  6. 6. Connection Diagram
  7. 7. Internal Block Diagram
  8. 8. Internal Hub
  9. 9. ISP1761 Clock Scheme
  10. 10. Interrupts The ISP1761 will assert the IRQ according to the source or event in the HcInterrupt register. The main steps to enable the IRQ assertion are: 1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register. 2. Define the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control register. 3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match IRQ settings of the host processor. By default, interrupt is level-triggered and active LOW. 4. Program the individual Interrupt Enable bits in the HcInterruptEnable register. The software will need to clear the Interrupt Status bits in the HcInterrupt register before enabling individual interrupt enable bits. The interrupt for each endpoint can individually be controlled through the associated IEPnRX or IEPnTX bits. All interrupts can globally be disabled through bit GLINTENA in the Mode register
  11. 11. Phase-Locked Loop (PLL) Clock Multiplier The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz clock already existing in the system with a precision better than 50 ppm. This allows the use of a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI). When an external crystal is used, make sure the CLKIN pin is connected to VCC(I/O). The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz.
  12. 12. ISP1761 Power Supply Connection
  13. 13. Overcurrent detection <ul><li>The ISP1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital </li></ul><ul><li>overcurrent detection. </li></ul><ul><li>The range of the overcurrent detection voltage for the ISP1761 is 45 mV to 100 mV </li></ul><ul><li>The main features of this circuit are self reporting, automatic resetting, low-trip time and low cost. </li></ul><ul><li>The port power will automatically be disabled by the ISP1761 on an overcurrent event occurrence, by de-asserting the PSWn_N signal without any software intervention. </li></ul>
  14. 14. Power-On Reset (POR) Clock with respect to the external power-on reset Internal power-on reset timing
  15. 15. Memory Segmentation and Access Block Diagram
  16. 16. OTG Controller A-device State Diagram
  17. 17. Endpoint Description <ul><li>Each USB peripheral is logically composed of several independent endpoints. </li></ul><ul><li>An endpoint acts as a terminus of a communication flow between the USB host and the USB peripheral. </li></ul><ul><li>At design time, each endpoint is assigned a unique endpoint identifier, The combination of the peripheral address, the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced. </li></ul><ul><li>The peripheral controller has 8 kB of internal FIFO memory, which is shared among the enabled USB endpoints. </li></ul><ul><li>The two control endpoints are fixed 64 bytes long. Any of the seven IN and seven OUT endpoints can separately be enabled or disabled. </li></ul><ul><li>The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can individually be configured. </li></ul>
  18. 18. Additional Resource <ul><li>For ordering the ISP1761, please click the part list or </li></ul><ul><li>Call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><ul><li>http://www.stericsson.com/product/222228.jsp#Applications </li></ul></ul>

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