Overview of LPC213x MCUs <ul><li>Source: NXP Semiconductors </li></ul>
Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module provides overview about the LPC213x MCUs </li></ul></ul><ul...
Architectural Overview  <ul><li>Based on a 16/32 bit ARM7TDMI-S CPU </li></ul><ul><li>On-chip Flash memory </li></ul><ul><...
Memory Maps <ul><li>AHB section is 128 x 16KB blocks (2MB) </li></ul><ul><li>VPB section is 128 x 16KB blocks (2MB) </li><...
System Control Block <ul><li>The System Control Block includes several system features and control registers for a number ...
Memory Acceleration Module (MAM) <ul><li>The Memory Accelerator Module is divided into several functional blocks: </li></ul>
Vectored Interrupt Controller (VIC) <ul><li>ARM PrimeCell™ Vectored Interrupt Controller </li></ul><ul><li>32 interrupt re...
General Purpose Input/Output Ports (GPIO) <ul><li>Direction control of individual bits </li></ul><ul><li>Separate control ...
Universal Asynchronous Receiver/Transmitter 0  (UART0) <ul><li>16 byte Receive and Transmit FIFOs </li></ul><ul><li>Regist...
Universal Asynchronous Receiver/Transmitter 1  (UART1) <ul><li>UART1 is identical to UART0, with the addition of a modem i...
I 2 C interfaces I 2 C0 and I 2 C1 <ul><li>Standard I 2 C compliant bus interfaces that may be configured as Master, Slave...
SPI Interface (SPI0) <ul><li>Single complete and independent SPI controller. </li></ul><ul><li>Compliant with Serial Perip...
SSP Controller (SPI1) <ul><li>Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses. </l...
Timer/Counter TIMER0 and TIMER1 <ul><li>A 32-bit Timer/Counter with a programmable 32-bit Prescaler </li></ul><ul><li>Coun...
Pulse Width Modulator (PWM) <ul><li>Seven match registers allow up to 6 single edge controlled or 3 double edge controlled...
Analog-to-Digital Converter (ADC) <ul><li>10 bit successive approximation analog to digital converter (one in LPC2131/2 an...
Digital-to-Analog Converter (DAC) <ul><li>10 bit digital to analog converter </li></ul><ul><li>Resistor string architectur...
Real Time Clock <ul><li>Measures the passage of time to maintain a calendar and clock. </li></ul><ul><li>Ultra Low Power d...
Watchdog Timer <ul><li>Internally resets chip if not periodically reloaded. </li></ul><ul><li>Debug mode. </li></ul><ul><l...
Flash Memory System and Programming <ul><li>In-System Programming: In-System programming (ISP) is programming or reprogram...
EmbeddedICE logic <ul><li>No target resources are required by the software debugger in order to start the debugging sessio...
Embedded Trace Macrocell (ETM) <ul><li>Closely track the instructions that the ARM core is executing. </li></ul><ul><li>1 ...
RealMonitor <ul><li>Allows   user   to   establish   a   debug   session   to   a   currently   running   system   without...
Additional Resource <ul><li>For ordering the LPC213x products, please call our sales hotline </li></ul><ul><li>For additio...
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Overview of LPC213x MCUs

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Overview of LPC213x MCUs

  1. 1. Overview of LPC213x MCUs <ul><li>Source: NXP Semiconductors </li></ul>
  2. 2. Introduction <ul><li>Purpose </li></ul><ul><ul><li>This module provides overview about the LPC213x MCUs </li></ul></ul><ul><li>Outline </li></ul><ul><ul><li>Overview of LPC213x MCUs </li></ul></ul><ul><ul><li>Key features </li></ul></ul><ul><li>Contents </li></ul><ul><ul><li>23 pages </li></ul></ul><ul><li>Duration </li></ul><ul><ul><li>15 Minutes </li></ul></ul>
  3. 3. Architectural Overview <ul><li>Based on a 16/32 bit ARM7TDMI-S CPU </li></ul><ul><li>On-chip Flash memory </li></ul><ul><li>On-chip Static RAM </li></ul><ul><li>Up to 2 10-bit ADC </li></ul><ul><li>10-bit DAC </li></ul><ul><li>Multiple serial interfaces </li></ul><ul><li>Two 32-bit timers </li></ul>
  4. 4. Memory Maps <ul><li>AHB section is 128 x 16KB blocks (2MB) </li></ul><ul><li>VPB section is 128 x 16KB blocks (2MB) </li></ul>Reserved Reserved VPB Peripherals AHB Peripherals 0x FFFF FFFF 0x FFE0 0000 0x FFDF FFFF 0x F000 0000 0x EFFF FFFF 0x E020 0000 0x E01F FFFF 0x E000 0000 4.0G 4.0G - 2MB 3.75G 3.5G +2MB 3.5G
  5. 5. System Control Block <ul><li>The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. </li></ul><ul><li>Crystal Oscillator </li></ul><ul><li>External Interrupt Inputs </li></ul><ul><li>Memory Mapping Control </li></ul><ul><li>PLL </li></ul><ul><li>Power Control </li></ul><ul><li>Reset </li></ul><ul><li>VPB Divider </li></ul><ul><li>Wakeup Timer </li></ul>
  6. 6. Memory Acceleration Module (MAM) <ul><li>The Memory Accelerator Module is divided into several functional blocks: </li></ul>
  7. 7. Vectored Interrupt Controller (VIC) <ul><li>ARM PrimeCell™ Vectored Interrupt Controller </li></ul><ul><li>32 interrupt request inputs </li></ul><ul><li>16 vectored IRQ interrupts </li></ul><ul><li>16 priority levels dynamically assigned to interrupt requests </li></ul><ul><li>Software interrupt generation </li></ul>
  8. 8. General Purpose Input/Output Ports (GPIO) <ul><li>Direction control of individual bits </li></ul><ul><li>Separate control of output set and clear </li></ul><ul><li>All I/O default to inputs after reset </li></ul><ul><li>Applications </li></ul><ul><ul><li>General purpose I/O </li></ul></ul><ul><ul><li>Driving LEDs </li></ul></ul><ul><ul><li>Sensing digital inputs </li></ul></ul><ul><ul><li>Controlling off-chip devices </li></ul></ul>
  9. 9. Universal Asynchronous Receiver/Transmitter 0 (UART0) <ul><li>16 byte Receive and Transmit FIFOs </li></ul><ul><li>Register locations conform to ‘550 industry standard. </li></ul><ul><li>Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. </li></ul><ul><li>Built-in baud rate generator. </li></ul><ul><li>LPC2131/2/4/6/8 UART0 contains mechanism that enables software flow control implementation. </li></ul>
  10. 10. Universal Asynchronous Receiver/Transmitter 1 (UART1) <ul><li>UART1 is identical to UART0, with the addition of a modem interface. </li></ul><ul><li>16 byte Receive and Transmit FIFOs. </li></ul><ul><li>Register locations conform to ‘550 industry standard. </li></ul><ul><li>Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. </li></ul><ul><li>Built-in baud rate generator. </li></ul><ul><li>Standard modem interface signals included (LPC2134/6/8 only). </li></ul><ul><li>LPC2131/2/4/6/8 UART1 provides mechanism that enables implementation of either software or hardware flow control. </li></ul>
  11. 11. I 2 C interfaces I 2 C0 and I 2 C1 <ul><li>Standard I 2 C compliant bus interfaces that may be configured as Master, Slave, or Master/Slave. </li></ul><ul><li>Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. </li></ul><ul><li>Programmable clock to allow adjustment of I 2 C transfer rates. </li></ul><ul><li>Bidirectional data transfer between masters and slaves. </li></ul><ul><li>Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. </li></ul><ul><li>Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. </li></ul><ul><li>The I 2 C-bus may be used for test and diagnostic purposes. </li></ul>
  12. 12. SPI Interface (SPI0) <ul><li>Single complete and independent SPI controller. </li></ul><ul><li>Compliant with Serial Peripheral Interface (SPI) specification. </li></ul><ul><li>Synchronous, Serial, Full Duplex communication. </li></ul><ul><li>Combined SPI master and slave. </li></ul><ul><li>Maximum data bit rate of one eighth of the input clock rate. </li></ul><ul><li>8 to 16 bits per transfer. </li></ul>
  13. 13. SSP Controller (SPI1) <ul><li>Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses. </li></ul><ul><li>Synchronous Serial Communication </li></ul><ul><li>Master or slave operation </li></ul><ul><li>8-frame FIFOs for both transmit and receive. </li></ul><ul><li>4 to 16 bits frame </li></ul>
  14. 14. Timer/Counter TIMER0 and TIMER1 <ul><li>A 32-bit Timer/Counter with a programmable 32-bit Prescaler </li></ul><ul><li>Counter or Timer operation </li></ul><ul><li>Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions </li></ul><ul><li>Four 32-bit match registers that allow: </li></ul><ul><ul><li>Continuous operation with optional interrupt generation on match </li></ul></ul><ul><ul><li>Stop timer on match with optional interrupt generation </li></ul></ul><ul><ul><li>Reset timer on match with optional interrupt generation </li></ul></ul><ul><li>Up to four external outputs corresponding to match registers, with the following capabilities: </li></ul><ul><ul><li>Set low on match </li></ul></ul><ul><ul><li>Set high on match </li></ul></ul><ul><ul><li>Toggle on match </li></ul></ul><ul><ul><li>Do nothing on match </li></ul></ul>
  15. 15. Pulse Width Modulator (PWM) <ul><li>Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. </li></ul><ul><li>An external output for each match register. </li></ul><ul><li>Supports single edge controlled and/or double edge controlled PWM outputs. </li></ul><ul><li>Pulse period and width can be any number of timer counts. </li></ul><ul><li>Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. </li></ul><ul><li>Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. </li></ul><ul><li>May be used as a standard timer if the PWM mode is not enabled. </li></ul><ul><li>A 32-bit Timer/Counter with a programmable 32-bit Prescaler. </li></ul><ul><li>Four 32-bit capture channels take a snapshot of the timer value when an input signal transitions. </li></ul>
  16. 16. Analog-to-Digital Converter (ADC) <ul><li>10 bit successive approximation analog to digital converter (one in LPC2131/2 and two in LPC2134/6/8). </li></ul><ul><li>Input multiplexing among 8 pins. </li></ul><ul><li>Power-down mode. </li></ul><ul><li>Measurement range 0 to 3 V. </li></ul><ul><li>10 bit conversion time ≥ 2.44 μs. </li></ul><ul><li>Burst conversion mode for single or multiple inputs. </li></ul><ul><li>Optional conversion on transition on input pin or Timer Match signal. </li></ul><ul><li>Global Start command for both converters (LPC2134/6/8 only). </li></ul>
  17. 17. Digital-to-Analog Converter (DAC) <ul><li>10 bit digital to analog converter </li></ul><ul><li>Resistor string architecture </li></ul><ul><li>Buffered output </li></ul><ul><li>Power-down mode </li></ul><ul><li>Selectable speed vs. power </li></ul>
  18. 18. Real Time Clock <ul><li>Measures the passage of time to maintain a calendar and clock. </li></ul><ul><li>Ultra Low Power design to support battery powered systems. </li></ul><ul><li>Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. </li></ul><ul><li>Dedicated 32 kHz oscillator or programmable prescaler from VPB clock. </li></ul><ul><li>Dedicated power supply pin can be connected to a battery or to the main 3.3 V. </li></ul>
  19. 19. Watchdog Timer <ul><li>Internally resets chip if not periodically reloaded. </li></ul><ul><li>Debug mode. </li></ul><ul><li>Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. </li></ul><ul><li>Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. </li></ul><ul><li>Flag to indicate Watchdog reset. </li></ul><ul><li>Programmable 32-bit timer with internal pre-scaler. </li></ul><ul><li>Selectable time period from (TPCLK x 256 x 4) to (TPCLK x 232 x 4) in multiples of TPCLK x 4. </li></ul>
  20. 20. Flash Memory System and Programming <ul><li>In-System Programming: In-System programming (ISP) is programming or reprogramming the on-chip flash memory, using the boot loader software and a serial port. This can be done when the part resides in the end-user board. </li></ul><ul><li>In Application Programming: In-Application (IAP) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code. </li></ul>
  21. 21. EmbeddedICE logic <ul><li>No target resources are required by the software debugger in order to start the debugging session. </li></ul><ul><li>Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly to the core. </li></ul><ul><li>Inserts instructions directly in to the ARM7TDMI-S core. </li></ul><ul><li>The ARM7TDMI-S core or the System state can be examined, saved or changed depending on the type of instruction inserted. </li></ul><ul><li>Allows instructions to execute at a slow debug speed or at a fast system speed. </li></ul>
  22. 22. Embedded Trace Macrocell (ETM) <ul><li>Closely track the instructions that the ARM core is executing. </li></ul><ul><li>1 External trigger input </li></ul><ul><li>10 pin interface </li></ul><ul><li>All registers are programmed through JTAG interface. </li></ul><ul><li>Does not consume power when trace is not being used. </li></ul><ul><li>THUMB instruction set support </li></ul>
  23. 23. RealMonitor <ul><li>Allows user to establish a debug session to a currently running system without halting or resetting the system. </li></ul><ul><li>Allows user time-critical interrupt code to continue executing while other user application code is being debugged. </li></ul>
  24. 24. Additional Resource <ul><li>For ordering the LPC213x products, please call our sales hotline </li></ul><ul><li>For additional inquires contact our technical service hotline </li></ul><ul><li>For more product information go to </li></ul><ul><li>http://www.nxp.com/#/homepage/cb=[t=p,p=/50809/45994]|pp=[t=pfp,i=45994 ] </li></ul>

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