10.7mW, 2.1mm2, 0.13µm CMOS GPS radio
David Tester, Senior Member IEEE and Ian Watson
Cherry Orchard North, Kembrey Park
Swindon, Wiltshire, SN2 8UH, UK
Abstract— A fully integrated GPS radio realized in a 0.13µm
CMOS technology from a leading foundry is presented. This
radio forms a key component within a single-die GPS receiver.
The receiver includes the full RF and IF signal chain including
on-chip LNA, direct support for external LNA, mixer, fully
integrated frequency synthesizer, distributed IF gain and
filtering along with multiple ADC’s. Additionally, the macro
includes local on-chip voltage regulation, enabling a direct
connection to a typical consumer 2.4V-4.9V Li-Ion battery.
RF jammer detection, temperature monitoring, automatic trim
for on-chip IF signal filtering, bandgap reference voltage and
crystal oscillator driver functions are also provided. With a
measured front-end noise figure of 3.5dB, a total power
consumption of 10.7mW, receiver gain of 84dB and a total die
area (including I/O pads) of 2.1mm2 this work is the smallest die
area and lowest power GPS radio reported to date.
Location has emerged as core functionality for consumer
devices such as mobile phones and digital cameras.
GPS enabled mobile phones offer navigation capabilities and Figure 1. Integrated GPS Radio
other location based services. GPS enabled digital cameras
equatorial radius of 6,378km in six planes, each inclined by
can location-stamp photographs (often called “geotagging”).
55 degrees with respect to the equator with a semi-major axis
This paper presents performance details of the 10.7mW radio
of 26,562km, at a circular velocity of 3.9km/s and with an
included within a 0.13µm CMOS single-die GPS receiver.
orbital period of 11 hours and 58 minutes.
The GPS radio reported in this paper, as of late 2009,
Each satellite transmits a CDMA signal at 154x the system
represents current state of the art for consumer electronics.
frequency of 10.23MHz (or 1.58GHz). The C/A signal at L1
Intended for embedded use within a digital camera this GPS
is spread using Gold codes . Worst case cross-correlation
radio is also architected and implemented for cellphone use.
between Gold codes used for L1 GPS is 21.6dB.
II. SUMMARY OF THE PAPER Unobstructed receive power is no less than -130dBm over
Section III outlines details of the GPS system. Section IV the satellite lifetime with a spread of 6dB due to satellite age.
describes the receiver architecture. Sections V to VIII Observed power in a typical environment can be 30dB less!
present specific circuit level implementation details for the Each satellite transmits a 37,500 bit navigation message
RF and IF signal paths along with the frequency synthesizer through a 25 frame TDMA protocol. Each frame contains
and support functions of the receiver. Section IX outlines 1,500 bits of data and is comprised of 5 sub-frames each
process and package implementation details for the receiver lasting 6 seconds containing ten 30 bit words. The entire
whilst section X compares the performance of this receiver message provides both satellite (ephemeris) and constellation
with previously reported results and presents conclusions. (almanac) information.
III. SUMMARY OF THE GPS NAVIGATION SYSTEM IV. RECEIVER ARCHITECTURE AND SPECIFICATION
The GPS air interface is defined in . Additional details With a thermal noise floor in the L1 band of -109dBm and
on system design and operation can be found in  and . the received signal power between -130dBm to -160dBm the
GPS satellites orbit at an altitude of 20,163km above the signal sits at least 21dB below the thermal noise floor. The
radio typically provides 80dB of gain, de-spreading provides Gilbert stage. Quadrature LO is generated locally through a
30dB of processing gain and the remaining 30dB to 60dB divide-by-2 stage from the VCO output and is DC coupled to
required to achieve 10dB SNR needed for navigation data the mixer to minimize parasitic capacitance.
decode is achieved via coherent and non-coherent integration. The mixer load provides a fixed RC pole. Load resistance
An overview of the GPS radio and analog support is dependent on mixer bias current. Filter capacitance is
functions is presented in Figure 1. Utilizing a low-IF receiver switched as a result to ensure appropriate corner frequency.
architecture, the radio is directly connected via a SAW filter The resulting passive RC pole provides excellent blocking
to a GPS antenna. rejection and LO leakage suppression.
The radio signal path comprises an RF section and an IF Low-pass filter corner frequency for the mixer can be
adjusted between 5MHz and 6MHz.
section. The RF signal path contains on-chip LNA and mixer
whilst the IF signal path consists of configurable filters, C. Jammer Detect
VGA’s and ADC. The fully integrated frequency synthesizer As described in section IV the GPS signal is buried beneath
includes on-chip VCO running at 2x LO to avoid interfering the thermal noise floor. Energy detected in the front-end
harmonics and ease quadrature generation. corresponds to a jammer which degrades GPS operation. RF
Support circuits for temperature monitoring, bandgap output from the LNA is provided to a blocking level detector
reference voltage generation, linear power supply regulation to determine overload of the front-end and form an AGC loop
are provided along with a serial interface for configuration. around the LNA to reduce gain in the presence of jammers.
The only external components required for the radio are
D. External LNA Bias
antenna, SAW filter, input impedance match for the LNA,
reference TCXO or XTAL for the synthesizer, reference Flexible support for additional gain with an external LNA is
resistor and filter capacitor for the integrated bandgap and provided through provision of an LNA bias. Output current
stability capacitors for the integrated LDO regulation. can be adjusted from 0.4mA and 3.2mA in 0.4mA steps.
Support for optional external LNA is also provided. VI. IF SIGNAL PATH
The 2MHz wide GPS band centered at the L1 frequency is A. Band-Pass Channel Select Poly-Phase Filter
mixed down to 3MHz and quantized to 3b at 16.368MHz
providing 16x sampling compared to the 1.023MHz chip rate. A complex third-order band-pass Butterworth filter further
defines the receiver frequency response. Active stages with
Mixer side-band can be selected to avoid in-band jammers.
cross coupling between quadrature stages provide a poly-
The receiver provides 84dB of distributed gain with the RF
phase imaginary frequency response and hence single side-
section providing 38dB and the IF section providing 46dB.
band selection. The filter can select between lower or upper
V. RF SIGNAL PATH side-bands and so provide a jammer avoidance capability.
The RF signal path comprises an internal LNA and mixer Filter bandwidth is 2MHz, corresponding to the main lobe
with support for an optional external LNA. of the GPS signal and centre frequency is configurable
between 3MHz and 4MHz to support a configurable IF
A. LNA and Pre-Mixer Filter frequency. The first stage of the filter provides post-mixer
The integrated differential LNA path provides 38dB of gain control and offers gain settings of 11.5dB or 21.5dB.
distributed gain at 1.5GHz with a noise figure of 2.4dB. The Filter performance is ensured through automatic calibration.
LNA has multiple gain modes allowing a tradeoff between
B. Variable Gain Amplifier
gain, bias current, noise figure and compression point to
permit power optimized operation of the radio in the presence Output from the poly-phase filter is amplified with a VGA.
of jamming signals. The VGA offers gain configurable between 8dB and 24dB in
Negative feedback is used to form the LNA characteristic 2dB steps, with gain linearity of ±0.7dB and a band-pass
resistive input impedance of 120Ω and enables the use of response between 200kHz and 10MHz.
integrated DC block capacitors between the LNA and V2I C. Anti-Alias Filter
stages. Combined with the natural low-pass roll off of these
To prevent alias folding as a result of the ADC sampling,
two stages this provides a course first-order band-pass
the VGA is followed with an anti-alias filter. Low pass
response to the RF front-end.
frequency for the anti-alias filter can be varied between
Voltage output from the LNA is converted to current input
2.75MHz and 8MHz in 0.75MHz steps.
for both I and Q mixers. This stage has multiple gain modes
allowing further tradeoff between gain and compression. D. ADC
Bias current for the LNA voltage to current converter is set The radio provides support for 3b and 1b quantization at a
through a servo loop from the common mode output voltage sample rate of 16.368MHz with an input signal of ±20mV
of the mixer. and a high pass response to eliminate effects from inter-stage
B. Mixer and Post-Mixer Filter DC offset within the VGA.
The 3b ADC offers a non-linear transform function with
Quadrature output from the LNA is shifted from RF to IF
12mV and 8mV step sizes and a DNL of 0.5LSB.
through the use of I and Q mixers. Each mixer is a balanced
VII. FREQUENCY SYNTHESIZER rails in the absence of a reference voltage. The bandgap is
The frequency synthesizer is formed from a charge-pump implemented with isolated NPN transistors to ensure
based integer-N phase locked loop with integer frequency excellent PSRR to all voltage supplies and substrate. PSRR
division and a fully integrated VCO running at twice the is 90dB at DC and 50dB at 10MHz
desired LO frequency. B. Crystal Oscillator and Temperature Sensor
Operating with a reference comparison frequency of Support for both TCXO and XTAL based frequency
16.368MHz this integer-N loop can step in 511.5kHz units. references is provided with a low power driver which delivers
Lock time for the loop is less than 200µs and phase noise at
full scale output from a standard AT cut crystal with bias
1Mhz offset is -109dBc/Hz. Reference spurs are less than current of 60µA and phase noise of -135dBc at 10kHz offset.
-60dBc and residual FM over 10kHz to 30MHz band is less System temperature is monitored with an integrated sensor.
Capable of monitoring temperature over a -40ºC to +88ºC
A. VCO range with a bias current of 2µA.
Constant current bias is used to provide an LC tank based C. Voltage Regulation, Resistor Trim, POR and PLL
VCO with maximum PSRR and a tuning range of 2200MHz
Direction connection to a 2.4V to 4.9V battery is supported.
to 3340MHz. Implemented through a combination of course Analog, digital and auxiliary voltage domains are provided.
tuning, switching varactors in and out of circuit along with The analog LDO provides output voltage of 1.9V to 2.15V in
fine voltage controlled tuning this offers a corresponding LO
15mV steps operating with quiescent current of 3µA. The
frequency range of 1100MHz to 1670MHz over all corners. digital LDO provides regulated 1.2V output voltage at a
Typical gain for the VCO is 220MHz/V. quiescent current of less than 3µA. The auxiliary LDO
Output from the VCO is buffered for isolation to minimize
provides output voltages of 1.2V, 1.8V, 2.5V or 3.3V and
frequency pulling and reverse injection. operates with a quiescent current of less than 3µA.
B. Loop Divider and Loop Filter An external precision resistor is used to trim an on-chip
The buffered 150mV peak signal from the VCO is divided 100kΩ P+ poly resistor over the ±20% process range,
within the synthesizer and local to the mixers. Divide by two ensuring bias for all blocks operates within 2% of nominal.
within the mixer provides quadrature. Divide by two within Local power-on-reset is generated on-chip to initialize all
the synthesizer generates the target LO frequency for the loop circuits after establishment of power supplies. External POR
dividers. Dividers take small swing differential signal as is also supported should this be needed by the host system.
input and output from the CML divide-by-two is converted to Clocks required by GPS digital signal processing blocks
conventional CMOS levels prior to the main loop divider. downstream of the radio in the signal path are provided.
The synthesizer operates with on-chip loop filter, but also Built around a charge pump PLL with a ring oscillator VCO
supports an external loop filter. The internal loop filter is this block is able to provide multiple general purpose clocks.
composed of 228kΩ in series with 48.8pF, all in parallel with IX. IMPLEMENTATION DETAILS
9.3pF using both MOS and MIM capacitors.
C. PFD and Charge Pump The radio is implemented in a 1P6M standard 0.13µm
The central charge pump bias current can be varied between CMOS process with additional process options for high-Q
3µA and 15µA (in 3µA steps). Central charge pump current inductors, deep N-well isolation and MIM capacitors.
is set with further configurable multiplication factor of 1 to 8. Isolation is achieved with N-well / deep N-well underneath
Phase and frequency detection is performed with a standard and guard rings around all analog blocks. Sensitive circuits
four state PFD based on clock set, pulse reset latches. PFD are provided with isolated voltage rails and care is taken on
up and down request signals are completed with an signals crossing between analog and digital domains. The
acknowledge from the charge pump to exit the fourth state. pad ring is broken to isolate sensitive I/O pads from noise.
This avoids the charge pump dead-band and reduces Volume production utilizes a minimum pin QFN package.
comparison spur levels. System–level evaluation is performed with BGA package
VIII. ANALOG SUPPORT FUNCTIONS option. Figure IV shows the QFN packaged radio.
Operating range is -40ºC to +80ºC and 2.4V to 4.7V.
The global reference voltage for all circuits within the radio
is generated on-chip with a bandgap voltage reference. When Performance results for this work are presented in Table II
operating in active mode the bandgap is powered from a local with results from previously published work for comparison.
LDO (itself powered from the main analog LDO) to The reported GPS radio provides power consumption of
maximize PSRR. Bootstrap of the system is performed by 10.7mW for a die area of 2.1mm2 and exceeds all previous
local secondary supply voltage generation and a dedicated results, establishing a new state of the art.
start-up circuit for the bandgap when in standby mode,
enabling a low power operating mode and allowing the ACKNOWLEDGMENT
voltage supply subsystem to generate all required voltage Contribution from the entire team at Air is acknowledged.
THIS ISSCC MTT ION JSSC ISSCC JSSC ISSCC JSSC JSSC ION
WORK 2009 2009 2008 2007 2006 2006 2005 2005 2004 2002
         
10.7mW 19.5mW 41.4mW 20.4mW 20.5mW 19.8mW 27mW 84mW 19mW 24mW 21.6mW
5.1mA 13mA 23mA 17mA 11.4mA 11mA 17mA 60mA 10.5mA 15mA 7.2mA
SUPPLY 1.6V- 1.5V- 1.6V- 2.7V-
2.1V 1.5V 1.8V 1.2V 1.8V 1.8V 1.4V
VOLTAGE 1.8V 2.5V 2.0V 3.3V
LNA NF 2.4dB 1.8dB 1.6dB
RADIO NF 3.5dB 3.2dB 4.8dB 2.5dB 5dB 5dB 4.8dB 2dB 8.5dB 4dB
RADIO AREA 2.1mm2 2.4mm2 5.2mm2 3.24mm2 3.2mm2 4.1mm2 12.8mm2 2.6mm2 4.6mm2
PROCESS 0.13µm 0.11µm 0.18µm 90nm 0.18µm 0.18µm 0.18µm 90nm 0.18µm 0.18µm
TECHNOLOGY CMOS CMOS CMOS CMOS BiCMOS BiCMOS CMOS CMOS CMOS CMOS BiCMOS
Air MediaTek CoreLogic NXP GloNav RFDomus ST TI PHYCHIPS Sony NemeriX
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