Wafer level chip scale packaging

1. Book review
Wafer-Level Chip-Scale Packaging (Analog and Power Electronics
Packaging), XVII. Springer (2015). 322 pp., ISBN: 978-1-4939-1555-2
(Print) 978-1-4939-1556-9 (Online)
Wafer Level Chip-Scale Packaging by Qu, Shichun, Liu, Yong presents
good technical insights of wafer-level chip scale packaging (WLCSP)
technology, suitable for both industry and academic practitioners. The
authors provide insights on the broad values and fundamentals of
wafer level packaging and technical applications in this book. The
authors summarize the overall trends of wafer-level chip-scale
packaging and highlight the design, assembly processes and chip-scale
package designs with reliability test methods.
The authors reviewed the overview of the demand and challenges
for analog and power WLCSP, in Chapter 1. The main challenges and im-
pact of due to die shrinkage are reviewed. The development of power
WLCSP is explained. Basic concepts of fan-in and fan-out WLCSP,
bumping process flow, design considerations, and reliability assessment
are explained in Chapter 2 and Chapter 3. Chapter 2 covers the overall
WLCSP bumping processes and costing strategy and provides us the
considerations for WLCSP package development. Detailed board level
drop test and temperature cycling stress requirements are discussed
in Chapter 2. It also reveals some of the different approaches for designs
of redistribution layer (RDL). The remainder of this book builds on the
future of fan-out WLCSP technology and trends of development in
Chapter 3.
Chapter 4 presents the stackable packaging solutions involving
WLCSP. The multichip module packages, stacked ide package and
stacked package, wafer level three dimensional integration and embed-
ded WLCSP are covered in this Chapter. In Chapter 4, the authors discuss
various types of achieving package miniaturization through three di-
mensional integrated circuit (IC) integration, stacked die package and
stacked packages, 3 dimensional IC, thru-silicon via (TSV) and embed-
ded WLCSP. It presents the various options and driving forces of package
miniaturization through different stackable packaging solutions and
technologies.
Beyond these stackable packaging solutions and other package min-
iaturization such as power MOSFET WLCSP is covered in Chapter 5. The
authors discuss the details of wafer level discrete power MOSFET pack-
age design considerations. Design considerations such as discrete power
WLCSP design constructions, wafer-Level MOSFET direct drain design,
power VDMOSFET WLCSP with Cu Stud Bumping, 3D power module
with embedded WLCSP are explained in Chapter 5. Design concept of
integration of analog and power solution, are discussed in Chapter 6.
Key topics such as wafer-level power stack die 3D package with TSV,
wafer-level TSV or stack die concept for analog and integration of
power packaging with active and passive chips are provided.
Chapter 7 is all on the critical topics of thermal management, design,
and analysis for WLCSP. This chapter is very helpful for thermal analysis
and thermal modeling of power WLCSP. It focuses on methods of ther-
mal management which covers thermal resistance and measurement
methods, thermal analysis and management for WLCSP and provides
with transient thermal analysis for WLCSP. The electrical simulation
for example electrical simulation for a fan-out molded chip scale pack-
age is discussed in Chapter 8. Chapter 9 explains on the details of assem-
bly processes of WLCSP devices which includes PCB designs, solder
paste selection, component placement, fluxing, solder reflow recipes
and WLCSP underfill. It provides the in-depth critical process parame-
ters to industrial practitioners on WLCSP process development. Lastly,
the authors describe in details on reliability and general testing of
WLCSP semiconductors include WLCSP board level drop test, WLCSP
design for reliability in Chapter 10.
In summary, the book gives wide perspectives on the technical in-
sights of wafer-level chip scale packaging interconnect system and reli-
ability testing in industry while adding very valuable industry insights.
It is a good reference to demonstrate the alternate wafer-level chip
scale packaging, and can serve as a very informative technical reference.
It was a single example of package miniaturization used to demonstrate
many benefits of WLCSP. The book is valuable as a learning tool for
WLCSP and its clear relevance to real-world industry practices make it
useful for both students and reliability practitioners. Valuable as a learn-
ing tool for wafer-level chip scale interconnect technology, its clear rel-
evance to real world industry practices make it useful for both
academics and semiconductor industry practitioners.
Chong Leong Gan
SanDisk Storage Malaysia Sdn. Bhd., Penang, Malaysia
Institute of Nano Electronic Engineering, Universiti Malaysia Perlis,
Malaysia
Corresponding author.
E-mail address: clgan_pgg@yahoo.com.
Uda Hashim
SanDisk Storage Malaysia Sdn. Bhd., Penang, Malaysia
Microelectronics Reliability 55 (2015) 2481
http://dx.doi.org/10.1016/j.microrel.2015.08.007
0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Contents lists available at ScienceDirect
Microelectronics Reliability
journal homepage: www.elsevier.com/locate/mr