IC Design of Power Management Circuits (I)

IC Design of
Power Management Circuits (I)
Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009

Tutorial Content
1. Switching Converters: Fundamentals and Control
2. Switching Converters: IC Design
3. Switching Converters: Stability and Compensation
4. Fundamentals of Bandgap References
5. Development of Integrated Charge Pumps
6. Introduction to Low Dropout Regulators

Ki

2

Part I
Switching Converters:
Fundamentals and Control

Ki

3

Content
Steady State Analysis
Lossless elements
Buck, boost, buck-boost power stages
Volt-second balance
Continuous conduction mode
Discontinuous conduction mode
Ringing suppression
Pseudo-continuous conduction mode
Efficiency
Performance Evaluation Parameters
Control Topologies
PWM voltage mode control
PWM current mode control
Ki

Single-Inductor Multi-Input Multi-Output Converters

4

Linear Regulator has Low Efficiency
Idd

MN
IQ1

IQ2

VREF

Vdd

EA

Vo
IQ3

Io

R1
bVo
R2

C

RL

power converter
Efficiency of linear regulator is not high:

η=

Ki

Po
VI
V
Io
V
= o o = o
< o <1
Pin VddIdd Vdd Io + IQ Vdd

Can one design a power converter with efficiency close to 1?

5

Switches as Lossless Components
A power converter with high efficiency needs lossless components.
Reactive elements: capacitors, inductors
Active elements: switches

L

C

−

store &
relax

store &
relax

PC = 0

Ki

+
Vsw

Isw

PL = 0

+
Vsw

Isw

−

switch open

switch closed

Psw = Vsw×Isw
= Vsw×0
=0

Psw = Vsw×Isw
= 0×Isw
=0

6

Switching Converter: Heuristic Development (1)
Vo = Vdd

Vo
Vdd

RL
t

No regulation

SW1
Vdd

Vo

Vdd

Vo = DVdd

RL
t

duty ratio = D
Ki

Load cannot accept a
pulsating supply voltage
7

Switching Converter: Heuristic Development (2)
Vo

L

SW1
Vdd

C

Vx

Vdd

Ki

Vo

L

SW1
SW2

RL

C

Add a lossless filter to
achieve small ripple voltage,
but …
when switch is off, inductor
current cannot change
instantaneously and cause
spark (volt-second balance).

Vdd

Vo = DVdd

RL

Add a second switch that operates complementarily to arrive at
a functional switching converter.

t

8

Buck, Boost and Buck-Boost Converters (1)
Vx
SW1
Vdd

SW2

Vo

L
C

RL

Buck
Vx

L
Vdd

Vo

SW2
SW1

C

SW1
Vdd

Ki

Vo

SW2

L

C has to be in parallel with RL for
filtering, leaving three ways to place
L, SW1 and SW2 between Vdd and RL.

RL

Boost
Vx

One L and one C gives a second
order switching converter.

Three types of converters:
Step-down: buck
Step-up: boost
Step-up/down: buck-boost

(Boost-buck, or Cuk, is a 4th order
converter)
Buck-boost
C

RL

9

Buck, Boost and Buck-Boost Converters (2)
state 1

Vx
MN
Vdd

L

i
D1

C

state 2

RL

L

Vx
i
MN

state 1

Vo

D1
C

RL

Boost
MN
Vdd

Ki

state 1

SW1 is the controlling switch that
determines the duty ratio D, while SW2
provides a path for the inductor
current i to flow when SW1 is off.

Buck

state 2

Vdd

Vo

Vx

D1

Vo

i

L

state 2

C

RL

Buck-Boost

SW1 can be a power NMOS (MN). If
power PMOS is used, the phase has to
be reversed.
To prevent i from going negative, SW2
is usually implemented by a diode
(D1), but the forward drop gives a low
efficiency.
Note that Vo of buck-boost is negative.
10

I-V Relations of C and L
The I-V characteristics of a capacitor and an inductor are described by

ic = C

dv c
dt

ic

C

+
vc

i

v =L

di
dt

+

L

v

−

−

Approximations are very useful in many calculations:
ic = C

ΔVc
Δt

v =L

Δi
Δt

For sinusoidal steady state, the phasor relations are:

zc =
Ki

vc
1
=
ic
jωC

z =

v
= jω L
i
11

Volt-Second Balance
Switching actions cause ripples for both inductor current (i ) and
capacitor voltage (vc). In the steady state, both quantities return
to the same value after one cycle.
i

+ v

V (S1 )
= m1
L

−

di
dt

⇒ ΔI =

i

ΔI

I

L

v =L

V (S2 )
= −m2
L

V
Δt
L

0A

t1
t2
(or DT) (or D ' T)

Inductor current has to obey volt-second balance (VS balance):
V (S1)×t1 + V (S2)×t2 = 0
⇒

m1t1 = m2t2

or

m1D = m2D’

It is used to compute the conversion ratio M = Vo/Vdd.
Ki

12

Inductor, Input, Switch, Diode and Tail Currents
i

Consider the buck converter:
idd

is

L

Vx
MN

Vdd

i
D1

id

it

Vo

ic

Io

C

RL

Input current idd: current through Vdd

idd

is

Switch current is: i in State 1
Diode current id: i in State 2; even if diode
is implemented by NMOS switch
Tail current it: current through the
combination of C and RL.

id

Capacitor current ic: ac part of tail current
Load current io: averaged tail current

Ki

it

Io

13

Continuous Conduction Mode
The converter is operating in continuous conduction mode (CCM)
if the inductor current is always larger than zero.
Boost converter
(Step-up)

Buck converter
(Step-down)
Vdd

Vo

+V −

S1
S2

m1D = m2D’
⇒ (Vdd-Vo)D = VoD’
⇒ M=

Ki

V0
=D
Vdd

Vdd

Buck-boost converter
(Step-up/down)
Vo

+V −
S1

S2

m1D = m2D’
⇒ VddD = (Vo-Vdd)D’
⇒ M=

V0
1
=
Vdd 1 − D

Vdd

Vo

S1

+
V
−

S2

m1D = m2D’
⇒ VddD = -VoD’
⇒ M=

V0
−D
=
Vdd 1 − D
14

Discontinuous Conduction Mode
When the switching converter is operation in CCM, one switching
cycle has two states S1 and S2. When the load current becomes
smaller and smaller, eventually the inductor current would fall to
zero, and the converter then operates in discontinuous conduction
mode (DCM) with a third state S3. During D3T, all switches are open.
V (S1 )
= m1
L

V (S2 )
= −m2
L
V (S3 )
=0
L

i

ΔI

i =0

DT

D2 T

D3 T

VS balance becomes:
m1D = m2D2
Ki

15

Ringing Suppression
When both switches are open, L,
C and the parasitic capacitor Cx
at Vx form a resonance circuit
that leads to serious ringing.
Vx
Vdd

SW2

i

Cx

SW3

Vx

Vo

L

SW1

We may add a small switch to
short the inductor when SW1
and SW2 are both off [Jung 99].

Vdd
C

RL

SW2

Vo

L

SW1
Cx

C

RL

i
Vdd
Vo

Ki

Vx

Vx

16

Pseudo-Continuous Conduction Mode
By increasing the size of the ringing suppression switch, a switching
converter may work in pseudo-continuous mode (PCCM). It was first
employed in a single-inductor dual-output (SI-DO) converter to
increase the current handling capability [Ma 03b]. When both SW1
and SW2 are open, the freewheel switch SWFW is closed to allow
free-wheeling of i at Ipccm.
SWFW

L

Vx
SW1
Vdd

Vo

i
SW2

C

i
Ipccm

RL
0

Ki

17

Efficiency of Buck Converter
Rs

Idd

Io

L

S1
Vdd

Vo

R

S2
Rd

C

RL

η=

Po
VI
= o o
Pdd VddIdd

For an ideal buck converter working in CCM, the conversion ratio M
is Vo/Vdd = D, and Io:Idd = 1:D, giving η=1. If conduction loss is
accounted for, then Io/Idd is still 1/D, but M is modified as M=ηD,
with
P
1
η= o =
R + DR s + D 'R d
Pdd
1+
RL
Ki

18

Efficiency of 2nd Order Converters
By accounting for conduction losses due to switch, diode and inductor
series resistance (Rs, Rd and R , respectively), the efficiencies of buck,
boost and buck-boost converters are computed as [Ki 98]
1
R + DR s + D 'R d
1+
RL

Buck:

Boost:

ηboost =

Buck-boost:

Ki

ηbuck =

ηbuck −boost =

1
1 R + DR s + D 'R d
1+ 2
RL
D'
1
1 R + DR s + D 'R d
1+ 2
RL
D'
19

Performance Evaluation Parameters
For a good voltage regulator, the output voltage should remain
constant even the input voltage, load current or temperature changes.
Steady state parameters:
Line regulation
Load regulation
Temperature coefficient
Small signal parameters:
Power supply rejection
Output impedance
Transient parameters:
Line transient (settling times)
Load transient (settling times)
Reference tracking time
Ki

20

Line Regulation
Line regulation is the change of Vo w.r.t. the change in Vdd:
line reg. =
=

ΔVo
ΔVdd

in mV / V

ΔVo / Vo
ΔVdd

in % / V

Switching converters are non-linear circuits for large signal changes,
and hand analysis is impossible. It could be obtained by simulation.
In datasheets, line regulation is usually measured.

Ki

21

Power Supply Rejection
For a good switching converter (also for bandgap reference and
linear regulator), the output voltage should be a weak function w.r.t.
the supply voltage. Hence, a small signal parameter, the power
supply rejection, gives good indication of line regulation.
Power supply rejection (PSR) is the small signal change of Vo w.r.t.
the small signal change in Vdd.
vo
v dd

In transfer function form:

PSR =

In dB:

PSR = 20 × log

v dd
vo

Usually |vo/vdd| < 1, but we customarily give a positive PSR in dB.
Note:
Ki

Line reg. ≈ PSR × ΔVdd
22

Load Regulation and Output Impedance
Load regulation is the change of Vo w.r.t. the change in Io:
load reg. =
=

ΔVo
ΔIo

in mV / mA

ΔVo / Vo
ΔIo

in % / mA

In datasheets, load regulation is usually measured.
In the small signal limit, load regulation is the output impedance:
Ro =

Ki

dVo
dIo

in Ω

23

Temperature Coefficient
Temperature coefficient (TC) is the change of a parameter X w.r.t.
the change in T, and is a large signal parameter:
TC =

=

ΔX X(T2 ) − X(T1 )
=
ΔT
T2 − T1

in [X] / o C

ΔX / X
ΔT

in ppm / o C

TC could be positive or negative.

Ki

24

PWM Voltage Mode Control (1)
A regulated switching converter consists of the power stage and
the feedback circuit.
MP

Vo

L

Vg

MN

RL

ck

C
R1
CMP
Q

R

Q

va

EA
A(s)

S

va

bVo
Vref

ramp
Q

R2

va

Q

ramp
ck

Ki

For a buck converter, if an on-chip charge pump is not available,
then the NMOS power switch is replaced by a PMOS power switch.

25

The output voltage Vo is scaled down by the resistor string R1 and
R2. The scale factor is b = R2/(R1+R2).
The scaled output voltage bVo is compared to the reference
voltage Vref to generate a lowpass filtered voltage Va through the
compensator A(s).
At the start of the clock, the SR latch is set and the switch MP is
turned on, starting the duty cycle. A sawtooth waveform (ramp)
synchronized with the clock ramps up.
When the ramp reaches the level of Va (trip point), the SR latch is
reset, terminating the duty cycle.

Ki

When the SR latch is set, i ramps up. When the SR latch is reset,
i ramps down. In the steady state, i returns to the same level at
the start of every clock cycle.

26

PWM Feedback Action

For stability, the control loop has to have negative feedback.
Assume Vo drops suddenly due to change in load or disturbance
⇒ error voltage Verr = (Vref–bVo) becomes larger
⇒ Va = A(f)(Vref–Vo) also becomes larger
⇒ with a higher Va, it takes the ramp longer to reach Va
⇒ duty ratio D is temporarily increased
⇒ more current is dumped into the load
⇒ Vo rises accordingly and eventually settles to the original
value
Note that A(s) is the frequency response of the compensator,
not of the op amp Aop(s).

Ki

27

PWM Current Mode Control
A current mode controlled switching converter is realized by replacing
the fixed voltage ramp with the inductor current ramp.
L

MP

Vo

i

Vdd

RL

MN
C

R1
CMP
Q

R

Q

va

EA
A(s)

S

Vdd

ck

Vref

R2

current
sensor
i /N

va
NR f

Ki

bVo

i Rf

28

Sub-harmonic Oscillation and Slope Compensation
Output of EA Va cannot change in one cycle. If inductor current is
perturbed by an amount of ΔI1, oscillation occurs if
ΔI2
−m2
=
> 1 ⇔ D > 0.5
m1
ΔI1
Ia = Va / R f
D < 0.5

Ia = Va / R f
D > 0.5

−m2

m1

ΔI1

ΔI2

ΔI1

m1

−m2
ΔI2

To prevent oscillation, employ slope compensation by adding a negative
slope to Ia (i.e., Va) to suppress the change in ΔI2.
Ia = Va / R f

−mc

m1

Ki

ΔI1

m − m2
m
ΔI2
= c
< 1 ⇔ mc > 2
mc + m1
2
ΔI1
−m2
ΔI2

29

Current Mode PWM with Compensation Ramp
In practice, the output of EA (Va) should not be tempered, and a
compensation ramp of +mc is added to m1 instead.
L

MP

Vo

i

Vdd

RL

MN
C

R1
CMP
Q

(m1 + mc )R f
va

Ki

EA
A(s)

S

−(m2 − mc )R f

vb

DT

R

Q

va

bVo
Vref

Vdd

R2

i /N
ck

V2I
vb
NR f

ramp from OSC
compensation
ramp

30

Synchronous Rectification
To eliminate loss due to forward diode drop, the power diode is
replaced by a power NMOS MN, and the scheme is known as
synchronous rectification. To eliminate short-circuit loss of MP and
MN, a break-before-make (BBM) buffer is used.
L

MP

Q, VP

i

Vdd

RL

MN
C
VP

VN

BBM
Buffer

Ki

Q

R

Q

S

Additional logic is needed
for DCM operation.

Q
(ck)

VN

φ1

φ2

φ1 =
VP

φ2

Non-overlapping φ1 and φ2

φ1
φ2 = VN

31

Multiple-Output Converters
Consider two boost converters that operate in deep DCM:
L
i1
Vdd

Vo1

S1
S0

C1

i1

R L1

T

2T

T

2T

L
i2
Vdd

Ki

Vo2

S2
S0

i2

R L2
C2

32

Single-Inductor Multiple-Output Converters
Time-multiplexing allows sharing one inductor and diverting the
inductor current to two or more outputs [Ma 03a]:

Vo1

S1

L

C1

i

R L1

i
Vdd

T

S0

Vo2

S2
C2

Ki

2T

R L2

33

SIMO Converter in PCCM
To handle large load currents, raise the inductor current floor to
operate in PCCM. Add a free-wheeling switch (SFW) to short the
inductor when the inductor current reaches Ipccm [Ma 03b].
SFW

Vo1

S1

L

C1

i

R L1

i

T

S0

Vo2

S2
C2

Ki

2T

T

Vdd

2T

i

R L2
Ipccm

34

SI-MIMO Converter
Some applications need two converters in series with reduce efficiency.
Vbat

Vload

Vsrc

Energy-harvesting
source

Boost 1

Rechargeable
battery

Boost 2

Load

Reorganize by using a SI-DIDO converter that needs only one inductor
[Lam 04b], [Lam 07b], [Sze 08].
Vbat

Vbat
Vload

Vsrc

Ki

Energy-harvesting
source

SI-DIDO boost

Load

Rechargeable
battery

35

Development of SI-MO and SI-MIMO Converters
The recent years sees active R&D activities of SI-MO and SI-MIMO
switching converters for low power applications. It is important to
recognize the contribution of the first developers.
The idea of SI-MO converters was first conceived in [Goder 97], and
only boost sub-converters were considered.
An SI-DO converter with buck-boost sub-converters was discussed in
[Ma 97] to demonstrate the switching flow graph modeling method.
SI-DO converters became commercial products [MAX 98, UCC 99].
The concept of SI-MO was reinvented [Li 00, Ma 00, Ma 01, May
01]. [Ma 01] stressed the importance of DCM operation for reducing
cross-regulation. A systematic classification is discussed in [Ki 01].
DCM operation is extended to PCCM operation in [Ma 02].
The concept of SI-MIMO was conceived [Lam 04, Lam 07].
Ki

36

References: Switching Converter Fundamentals
Books:
[Brown 01] M. Brown, Power Supply Cookbook, EDN, 2001.
[Erickson 01] R. W. Erickson and D. Maksimovic, Fundamentals of Power
Electronics, 2nd Edition, Springer Science, 2001.
[Kassakian 91] J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Principle
of Power Electronics, Addison Wesley, 1991.
[Krein 98] P. E. Krein, Elements of Power Electronics, Oxford, 1998.
Papers:
[Jung 99] S. H. Jung et. al., "An integrated CMOS DC-DC converter for
battery-operated systems," IEEE Power Elec. Specialists Conf.,
pp. 43–47, 1999.
[Ki 98]

Ki

W. H. Ki, "Signal flow graph in loop gain analysis of DC-DC PWM
CCM switching converters," IEEE TCAS-1, pp.644-655, June
1998.

37

References: Early Development of SI-MIMO Converters (1)
[Goder 97] D. Goder and H. Santo, “Multiple output regulator with time sequencing,” US
Patent 5,617,015, April 1, 1997.
[Ma 97]

[MAX 98]

"MAX685: Dual-output (positive and negative) DC-DC converter for CCD and
LCD", Maxim Datasheet, 1998.

[UCC 99]

"UCC3941: 1V synchronous boost converter," Datasheet, Unitrode
Semiconductor Products, Jan. 1999.

[Li 00]

T. Li, "Single inductor multiple output boost regulator," US Patent 6,075,295,
June 13, 2000.

[Ma 00]

Ki

Y. H. Ma and K. M. Smedley, "Switching flow-graph nonlinear modeling
method for multistate-switching converters," IEEE Trans. on Power Elec.,
pp.854–861, Sept., 1997.

D. Ma and W. H. Ki, "Single-inductor dual-output integrated boost converter
for portable applications," 4th Hong Kong IEEE Workshop on SMPS, pp. 4251, Nov. 2000.

38

[Ma 01a]

D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "A single-inductor dual-output
integrated DC/DC boost converter for variable voltage scheduling",

IEEE/ACM Asia South Pacific Design Automation Conf., LSI University Design
Contest, pp.19–20, Jan. 2001.
[May 01]

[Ma 01b]

D. Ma, W. H. Ki, P. Mok and C. Y. Tsui, "Single-inductor multiple-output
switching converters with bipolar outputs", IEEE Int'l. Symp. on Circ. and
Syst., pp. III-301 - III-304, Sydney, May 2001.

[Ma 01c]

D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "A 1.8V single-inductor dual-output
switching converter for power reduction techniques," IEEE Symp. on VLSI
Circ., Kyoto, Japan, pp. 137-140, June 2001.

[Ki 01]

W. H. Ki and D. Ma, "Single-inductor multiple-output switching converters",
IEEE Power Elec. Specialists Conf., Vancouver, Canada, pp.226–231, June
2001.

[Ma 02]

Ki

M. W. May, M. R. May and J. E. Willis, "A synchronous dual-output switching
dc-dc converter using multibit noise-shaped switch control," IEEE Int’l SolidState Circ. Conf., pp.358–359, Jan 2001.

D. Ma, W.H. Ki, and C.Y. Tsui, "A pseudo-CCM / DCM SIMO switching
converter with freewheel switching", IEEE Int'l Solid–State Circ. Conf., San
Francisco, pp.390–391+476. Feb. 2002.

39

[Ma 03a]

[Ma 03b]

D. Ma, W. H. Ki and C. Y. Tsui, "A pseudo-CCM/DCM SIMO switching
converter with freewheel switching," IEEE J. of Solid-State Circ., pp. 10071014, June 2003.

[Lam 03]

Y. H. Lam, W. H. Ki, C. Y. Tsui and P. Mok, "Single-inductor dual-input dualoutput switching converter for integrated battery charging and power
regulation," IEEE Int'l. Symp. on Circ. and Syst., Bangkok, Thailand, pp.
III.447-III.450, May 2003.

[Lam 04]

H. Lam, W. H. Ki, C. Y. Tsui and D. Ma, "Integrated 0.9V charge-control
switching converter with self-biased current sensor," IEEE Int'l Midwest
Symp. on Circ. & Sys., pp.II.305–II.308, July 2004.

[Koon 05]

S. C. Koon, Y. H. Lam and W. H. Ki, "Integrated charge-control singleinductor dual-output step-up/step-down converter," IEEE Int'l. Symp. on
Circ. and Syst., Kobe, Japan, pp. 3071-3074, May 2005.

[Lam 07]

Y. H. Lam, W. H. Ki and C. Y. Tsui, "Single-inductor multiple-input multipleoutput switching converter and method of use," US Patent 7,256,568, Aug
14, 2007.

[Ma 09]

Ki

D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "Single-inductor multiple-output
switching converters with time-multiplexing control in discontinuous
conduction mode," IEEE J. of Solid-State Circ., pp. 89-100, Jan. 2003.

D. Ma, W. H. Ki, and C. Y. Tsui, "Single-inductor multiple-output switching
converters in PCCM with freewheel switching," US Patent 7,432,614, Oct. 7,
2008.

40

IC Design of
Power Management Circuits (II)
Wing-Hung Ki
ECE Dept., HKUST
www.ee.ust.hk/~eeki

Part II
IC Design

Ki

2

Content
IC Design: Control Loop
Biasing
RTCT oscillator
Comparators, hysteretic comparator
Operational amplifier
Current sensors
Compensation ramp
IC Design: Power Stage
Power transistor and gate drive
Synchronous rectification
Active diodes

Ki

IC Design: Peripheral Circuits
Under voltage lockout (UVLO)
Over current protection (OCP)
Soft start circuit

3

Foreword

Analog IC design is ENGINEERING.
Analog IC design is ART.
There is no best design but good and reasonable designs.
Design examples shown are suggestions rather than
instructions, and unavoidably opinionated.
Suggestions and corrections are most welcome to make
a more relevant and accurate presentation.

Ki

4

Guidelines for Analog IC Design

(1) Length of transistors are at least 4λ to 8λ for better
matching.
(2) Gate overdrive voltage Vov = (Vgs–Vt) of a transistor
should be at least 150mV for better current mirror
matching.
(3) Use 1% rule as initial point for matching, delay and
losses.

Ki

5

MP

Vo

L

Vg

MN

RL

ck

C
R1
CMP

Q

R

Q

va

EA
A(s)

S

va

bVo

Vref

ramp
Q

R2

va

Q

ramp
ck

Ki


6

L

MP

Vo

i

Vdd

RL

MN
C

R1
CMP
Q

(m1 + mc )R f
va

Ki

EA
A(s)

S

−(m2 − mc )R f
vb

DT

R

Q

va

bVo
Vref

Vdd

R2

i /N
ck

V2I
vb
NR f

ramp from OSC
compensation
ramp

7

Synchronous Rectification
To eliminate loss due to forward diode drop, the power diode is
replaced by a power NMOS MN, and the scheme is known as
synchronous rectification. To eliminate short-circuit loss of MP and
MN, a break-before-make (BBM) buffer is used.
L

MP

Q, VP

i

Vdd

RL

MN
C
VP

VN

BBM
Buffer

Ki

Q

R

Q

S

Additional logic is needed
for DCM operation.

Q
(ck)

VN

φ1

φ2

φ1 =
VP

φ2

Non-overlapping φ1 and φ2

φ1
φ2 = VN

8

Simple Current Source and Current Mirror
The simple current source is supply dependent. If the power
supply would change considerably, for example, from 5V to 12V,
then the simple current source should not be used.
Vdd

Vdd − V1
1
2
⎛W⎞
I1 = μnC ox ⎜ ⎟ ( V1 − Vtn ) =
2
R1
⎝ L ⎠1

R1
I1

I2

V1
M1

Ki

M2

I2 = I1
≈ I1

(W / L)2 (1 + λn Vds2 )
(W / L)1 (1 + λn Vds1 )
(W / L)2
(1 + λn (Vds2 − Vds1 ))
(W / L)1

9

CMOS Widlar Current Source
The self-biased CMOS Widlar current source appears very often in
textbooks. The version with a startup circuit is shown below.
Vdd
long
L 6 M6

M3

V2

M4

I1

I2

V3
M7

M5
wide
W5

startup
Ki

4

R1

:

2
1
⎛W⎞
I2 = μnC ox ⎜ ⎟ ( Vgs2 − Vtn )
2
⎝ L ⎠2

For (W/L)1 = 4(W/L)2 gives
gm1 =

v1i v1o

M1

2
1
⎛W⎞
I1 = μnC ox ⎜ ⎟ ( Vgs1 − I1R1 − Vtn )
2
⎝ L ⎠1

V1

1

M2

2I1
2
=
⇒ gm1R1 = 2
V1 − Vtn R1

A positive loop exists:
−v
−g / g g
−2
TV1 = 1o = m1 m2 m4 =
v1i
1 + gm1R1 gm3
3
10

CMOS Peaking Current Source (1)
The original peaking current source was designed in bipolar
processes. [Gray 01] gives a CMOS sub-threshold version, while
we suggest operating all transistors in the active region [Lo 09].
This current source does not need a start-up circuit.
Vdd
M3

Rb
I1

V3
I2

V − Vtn
dI2
= 0 ⇒ I1R1 = 1
dI1
2

R1
V2

Ki

V − V1
1
2
⎛W⎞
μnC ox ⎜ ⎟ ( V1 − Vtn ) = dd
2
Rb
⎝ L ⎠1

1
2
⎛W⎞
I2 = μnC ox ⎜ ⎟ ( V1 − I1R1 − Vtn )
2
⎝ L ⎠2

V1

M1

I1 =

M2

1 : 4

V2

For I2 = I1, set (W/L)2 = 4(W/L)1.
11

The peaking current source has very good power supply rejection.
v dd
Rb

1 / gm3
v1

v3

R1

Ki

R1 =

V1 − Vtn
1
=
⇒ gm1R1 = 1
2I1
gm1

Small signal analysis gives
v2

gm1 v1

From previous analysis,

v 2 1 − gm1R1
=
=0
v dd 1 + gm1R b
gm2 v 2

v dd − v 3 gm2 1 − gm1R1
=
=0
v dd
gm3 1 + gm1R b

That means the currents generated by current mirroring using V2
and (Vdd–V3) has a very low dependence on the supply voltage.

12

Assuming a 0.25µ CMOS process:
Vtn = 0.8V
µnCox = 50µA/V2
|Vtp| = 0.8V
µpCox = 25µA/V2

λnLn = 0.05µm/V
|λp|Lp = 0.05µm/V

Example: Vdd ranges from 4V to 6V, need I2 = 40μA.
Set ∂I2/∂I1 = 0 at Vdd = 5V with I1(5V) = 40μA. (W/L)2 = 40 gives
Vgs2-Vtn = 200mV, and 1mV change in Vtn causes 1% change in I2
(1% rule):
Vtn = 0.799V
Vtn = 0.800V
Vtn = 0.801V

Ki

⇒
⇒
⇒

Vdd
4V
5V
6V

I1
30μA
40μA
50μA

I2 = 40.4μA
I2 = 40.0μA
I2 = 39.6μA
I2
38.7μA
40.0μA
38.9μA

50μA

I1

40μA

I2

30μA

I1

4V

5V

6V

Vdd

13

Self-Biased Peaking Current Source
A current mirror (M3, M4) can be used to replace the large Rb to
reduce silicon area. The peaking current source becomes self-biased
and needs a startup circuit (may not be favorable).
Vdd
long
L 6 M6

Vb1
Vb2
M7

M5
wide
W5

Ki

startup

M4

M3

I1

V2

I2

R1
V1
M1

M2

1 :

V1

4

14

RTCT Oscillator (1)
The RTCT oscillator generates a ramp that synchronized with the
clock, which fits the requirement of a PWM switching converter.
Vdd

Ich = Vref / R T

Vref

EA

VH

VH

VL
Idch
RT
current
generator

Ki

VC
Mdch

CMP

S

Q

ck
Vm

ramp

T

CMP
CT

VL

T = 1 / fs
R

hysteretic
comparator

15

RTCT Oscillator (2)
The charging current Ich is well-controlled by a bandgap derived
voltage Vref and an accurate 1% (external) resistor RT (1% rule).
Ich charges an accurate 1% (external) capacitor CT slowly from the
lower bound VL to the upper bound VH. The ramp excursion is Vm.
The hysteretic comparator trips when VCT > VH, and ck = 1.
When ck = 1, the NMOS Mdch is turned on, and discharges CT with
a large current Idch that is around 10 times of Ich.
When VCT < VL, the comparator trips again, and ck = 0.
Idch is not well-controlled, but the accuracy of the oscillation
(switching) frequency fs is well-controlled because it is dominated
by the accurate Ich.
Ki

16

Current Regulator / Voltage Mirror
The error amplifier for generating the charging current can be
realized using a differential amplifier stage.
Vdd

Ich =
Vref

Vref
RT
Ib

Ki

Vref
RT

RT

17

Comparators
One-stage comparator

Two-stage comparator
Vdd

Vdd
Vb

Vb

V−

V+

Vo

V−2

V+
V−1
V−2

Low gain
Equal rise and fall times
Add inverters to increase gain
Ki

V−

V+

Vo

Vo

Higher gain
Rise time longer than fall time
A second V- input may be
added to both comparators

18

2-Stage Simple Operational Amplifier
The op amp of the PWM compensator should be ground-sensing
(common mode voltage close to ground).
Vdd
M5

Mb

Rb

V−

M1

M7

M2

Ib
R b2
supply
independent bias

Ki

V+
Cc

M3

M4

Vo
Rz
M6

CL

2-stage op amp

19

Frequency Response of Op Amp
The op amp gain is Aop(s) (but the EA (compensator) gain is A(s)):
A op (s) =

A dc (1 + s / z1 )
(1 + s / p1 )(1 + s / p2 )

|A|

A dc

p1

where

Ki

A dc = gm1 (rds2 || rds 4 ) × gm6 (rds6 || rds7 )
1
z1 =
C c (R z − 1 / gm6 )
1
p1 =
C c gm1 (rds2 || rds 4 )(rds6 || rds7 )
g
p2 = m6
CL
g
ωt = m1
Cc
choose p2 = 3ωt for φm = 70 o

ωt

p2
z1
/A

ω

ω

−90 o
−180

o

φm

20

Current Mirror Amplifier
The simple 2-stage op-amp can be modified to be a 1-stage current
mirror amplifier.
Vdd
Vbp

M0

M7

M8
V−

M5

Rb

4

:1

self-biased
Widlar current source

Ki

A op (s) =

M1

M3

M2

M4

V+

A dc = gm1 (rds6 || rds8 )
Vo

M6

A dc
(1 + s / p1 )

p1 =

1
CL (rds6 || rds8 )

ωt =

gm1
CL

CL

21

Folded Cascode Op Amp (1)
To achieve high DC gain, a folded cascode op amp could be used
(assume μn=2μp).
Vdd

8

R b2

:2 :8
Mb6

Mb4

20μA
Vb4

M1

M2

M10

M7
V−

Rb

10μA

M9

M0

Vb3

Mb3

M8

Mb1 Mb5

Vo

V+

Vb2

M5

M6

Vb1

Mb2

Ib

10μA

M3

M4

Ro

CL

Mb0

1 :4

Ki

:4

supply
independent bias

:1

20μA
folded cascode
gain stage

20μA

22

Folded Cascode Op Amp (2)
The gain function of the folded cascode op amp is:
A op (s) =

A dc
(1 + s / p1 )

where
A dc = gm1R o
p1 =

1
CL R o

with
R o = [gm6rds6 (rds 4 || rds2 )]|| [gm8rds8rds10 ]
and
ωt =

Ki

gm1
CL
23

2-Stage Folded Cascode Op Amp (1)
To achieve high DC gain, a folded cascode op amp followed by an
inverting stage could be used (assume μn=2μp).
Vdd

8

R b2

:2 :8
Mb6

Mb4

20μA

Rb

M0

M9
M7

V−
Mb2

Ib
Mb1 Mb5

10μA

Vb2
Vb1

M1

M2

Ki

:4

:1

supply
independent bias

M12

M10
M8
Rz C
c

V+
M5
M3

M6
M4

Mb0

1 :4

20μA

Vb4
Vb3

Mb3

10μA

20μA
folded cascode
gain stage

20μA

Vo

R o1
CL
M11
20μA
inverting
gain stage

24

2-Stage Folded Cascode Op Amp (2)
The gain function of the folded cascode op amp is:
A op (s) =

A dc (1 + s / z1 )
(1 + s / p1 )(1 + s / p2 )

where
A dc = gm1R o1 × gm11 (rds11 || rds12 )

R o1 = [gm6rds6 (rds 4 || rds2 )]|| [gm8rds8rds10 ]
1
z1 =
C c (R z − 1 / gm11 )
1
p1 =
C c gm1R o1 (rds11 || rds12 )
g
p2 = m11
CL
g
ωt = m1
Cc

Ki

25

V-to-I Conversion for Compensation Ramp
To add a compensation ramp to the inductor current, a V-to-I (V2I)
converter could be used. Two versions are shown below.
Vdd

Vdd

Vin
R
Vin

Ki

V1

Vin
R

Ib

R

Vin
R

(if Vgsn =
| Vgsp |)
V2

Vin

R

26

Power Transistor Design
Switch voltage of an ideal switch is 0V when conducting
⇒ MOS switch should have small Vds when conducting
⇒ MOS switch in triode (linear) region when conducting
⇒ For an NMOS power switch MN,
1
⎛W⎞ ⎡
⎤
Id = μnC ox ⎜ ⎟ ⎢(Vdd − Vtn )Vds − Vds 2 ⎥
2
⎝ L ⎠N ⎣
⎦
Vds
1
RN =
=
Id
μnC ox (W / L)N (Vdd − Vtn )
1% rule: conduction loss of RN is 1% of the load RL
If RL is 10Ω, 1% is 100mΩ. If duty ratio is 0.5, then MN conducts
half of the time, and RN can be 200mΩ.

Ki

27

Buffer Design
To drive a power switch effectively starting from control logic
blocks, buffers (digital inverters) have to be used.
Minimum delay gives a ratio of e (=2.718), but too many stages
are then needed:
- large transistors give large switching loss;
- large buffers give large shoot-through (short-circuit) loss;
- last stage buffer should have a ratio of 25 to 40.

1

Ki

:

4

:

40

:

600

:

30000

28

Eliminate Short-Circuit Loss (1)
For a large inverter, insert a starving resistor Rstarve to limit shootthrough (short-circuit) current, but the most important observation
is at Vp and Vn. For input changes from ‘0’ to ‘1’, Vn drops
immediately, but Vp drops with a delay due to Rstarve.

Vp
Vn

Ki

R starve

Vp
Vn

R starve

29

Eliminate Short-Circuit Loss (2)
Short circuit loss of the last stage (largest) buffer could be eliminated
if driven by a buffer with starving resistor.

(W / L)n
=4

40

:

600

40

:

600

Starving resistor can be replaced by transistors operating in the linear
region. A rule of the thumb design is 1/10 of the inverter transistors.
Ki

30

Power PMOS or Power NMOS?
The PMOS switch may be replaced by an NMOS switch driven from
an on-chip step-up charge pump [Sze 08].
Vdd = 1.2V

MPS
⇒

VPS

Vref +
−

5X
charge
pump

3.8V

MNS

VNS

level
shifter

Example: Vdd = 1.2V, and needs a 50mΩ switch (RPS = RNS = 50mΩ)
P-switch:
N-switch:

Ki

(W/L)PS = 1/(μpCox×(Vdd-|Vtp|)×RPS)
= 500,000μ/0.25μ
(W/L)NS = 1/(μnCox×(3.8-Vtn)×RNS)
= 33,300μ/0.25μ

Charge pump (1pF caps) + auxiliary circuits is about the size of MNS
⇒
P scheme : N scheme = 7.5 : 1

31

Simple P-Current Sensor
On-chip current sensing can be achieved by a small sensing transistor
Mps that is forced to have the same Vd, Vg and Vs as the power
transistor MP using a matched current source [Ki 98].
PVdd 1mA
1
MPs
20 / 2

1A
: 1000
MP
20000 / 2

Q
Q

MSW1
0.999mA
Ms1

to
PWM
CMP

Ki

i R f Ms5
N

Ms2

Ms3

Ms 4

Vo

L
MN

1μA
Rf

AGnd

MSW2

i

Msb

RL
C
PGnd

32

Symmetrical Matching of CMOS Transistors
When a pair of transistors M1 and M2 of the same type are matched,
their W/L ratios are the same, i.e., (W/L)1 = (W/L)2, and in most
cases, W1=W2 and L1=L2. However, their drain currents may not be
the same due to channel length modulation.
If in addition to having the same W/L ratio, M1 and M2 are forced
(by an additional circuit) to have essentially the same drain, gate
and source voltages, then they are called symmetrically matched
(SM) [Lam 04b, Lam 07].
The simple current sensor uses the 4T cell to force Mps to be
symmetrically matched with MP. However, the accuracy is limited by
the 4T cell that itself is not symmetrically matched.

Ki

33

Symmetrically Matched N-Current Sensor
Replace 4T cell by 8T cell with internal cross-biasing such that paired
transistors (M1, M2), (M3, M4), (M5, M6), (M7, M8) are symmetrically
matched, forcing Vy=Vx. Start-up circuit is needed [Lam04b, Lam 07].
M

Vdd
M9

:

1

M6

Isense

:

1
M4

M3

V4

:

M8

V2

M5

M1
Vx

M

V3

V1

M2

M7
Vy

i

Q

MN
1000

Ki

MNs
:

1

34

Concept of Active Diode
The lossy passive diode may be replaced by an active diode, and
eliminate the need to control two switches for synchronous
rectification:
Vx (A)

L

MP

(K)

Vo

(active diode)

RL

MN

Vdd

C

An active diode is simply a power transistor controlled by a (current)
comparator:
A

K

CMP

Ki

A

K

CMP

35

Active Diode Implementation (1)
One implementation of the active diode is discussed in [Man 06],
and is used in a DCM boost converter. The capacitor C is added to
improve transient response.

VL (A)

VH (K)

VH
C

Ki

36

Active Diode Implementation (2)
Another active diode is used in a regulated charge pump [Lam 06].
VH

VL

VH

VL

VH

VH

Vb

Active diodes can be used as maximum voltage selector for biasing
substrates of PMOS power switches in a multiple-output converter.
V1

Ki

Vmax

V2

37

Power Management Peripherals
For a low-voltage system, e.g., Vdd=5V, there is usually only one
trimmed voltage reference.
For a system with Vdd = 15V, there are usually two voltage
references, one trimmed for accuracy, and a second one untrimmed
and could work at very low voltage for start-up, UVLO (under voltage
lockout) and OVP (over voltage protection).
15V

5V
VBG(untrim)

untrim
BGR

UVLO

OVP

+
_

VREF
trimmed
BGR

functional
blocks

linear regulator

Ki

38

UVLO Comparator

Vdd
Vbp
VH
Vin
VL
VoH
VoL

Ki

39

Soft Start Circuit
Consider the buck converter. When Vo=0, EA drives Va to Vdd, and
D=1. SW1 is always on, causing large in-rush current. The soft start
circuit uses a very tiny current to charge a large CSS, such that VSS
rises very slowly, limiting the duty ratio.
Vdd

ramp

soft
start

Va
VSS

CMP

R Q
ck

R1
M1

M2

S Q
VSS

M2 is in sub-threshold region, sourcing
a current in the range of nA.
Ki

Vbn

CSS

40

I/O Connections
Different types of ESD (electrostatic discharge) diodes.

Vdd

I/O

I/O

GND

Schottky
diodes
Ki

large
diodes

diodeconnected
transistors
41

Continual Fraction Expansion
Consider the continual fraction expansion of π:
π = 3.14159265359
1
≈3+
7.0625133
1
≈3+
7 + (1 / 15.99659)
1
≈3+
7 + (1 / [15 + (1 / 1.0034)])

Now,
3+

1
7

1
7 + (1 / 15)
1
3+
7 + (1 / 16)
3+

Ki

22
= 3.14285714286
7
333
= 3.14150943396
=
106
355
= 3.14159292035
=
113
=

42

Resistor String using Unit Resistors
In an analog circuit array (compared with a digital gate array), all
components are fixed except for the metal layers for
interconnection. Resistors are thus formed using unit resistors.
For example, if the unit resistor is 9.5kΩ and R1=10.8kΩ is needed.
Use continual fraction expansion:
R1
10.8
=
= 1.136842
R unit
9.5
1
=1+
7.3077
1
=1+
7 + (1 / 3.25)
1
=1+
7 + (1 /[3 + (1 / 4)])

Ki

43

Parallel/Series Connection of Resistors
For Runit = 9.5kΩ
[1+(1/7)]×Runit = 1.14286×Runit = 10.86kΩ
8 Runit
[1+(1/[7+(1/3)])]×Runit = 1.13636×Runit = 10.8kΩ
11 Runit
[1+(1/[7+(1/[3+(1/4)])])]×Runit = 1.13684×Runit = 10.8kΩ 15 Runit
Use 11 Runit (instead of 15 Runit) is accurate enough and save
components. The structure is:
R1
1
=1+
1
R unit
7+
3

Ki

⇒

R unit
R1

44

IC References: Books/Theses
Books / Book Chapters / Thesis:
[Gilbert 96]

B. Gilbert, "Monolithic voltage and current references: Theme and Variations," in
[Huijsing 96], 1996.

[Gray 01]

P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated
Circuits, 4th Ed., Wiley, 2001.

[Huijsing 96] J. H. Huijsing, R. van de Plassche and W. Sansen, Analog Circuit Design, Kulwer,
1996.
[Johns 97]
[Lam 08]

Y. H. Lam, Differential Common-Gate Techniques for High Performance Power
Management Integrated Circuits, PhD Thesis, HKUST, Jan. 14, 2008.

[Meijer 96]

G. Meijer, "Concepts for bandgap references and voltage measurement systems," in
[Huijsing 96], 1996.

[Razavi 01]

B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.

[R-Mora 02]

G. A. Rincon-Mora, Voltage References, IEEE Press, 2002.

[Sansen 06]

W. Sansen, Analog Design Essentials, Springer, 2006.

[Sze 81]

Ki

D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.

S. M. Sze, Physics of Semiconductor Devices, 2nd Ed., Wiley, 1981.

45

IC References: Current Sources
Current Sources and Circuits:
[Frederiksen 72] T. M. Frederiksen, "Constant current source," US Patent 3,659,121, Apr. 25,
1972.
[Lam 07]
[Lo 09]

A. Lo, W. H. Ki and W. H. Mow, “A 20MHz switched-current sample-and-hold
circuit for current mode analog iterative decoders,” IEEE Int’l Symp. on IC, pp.
283-286, 2009.

[Kessel 71]

T. van Kessel and R. van der Plaasche, "Integrated linear basic circuits," Philips
Tech. Rev., pp.1-12, 1971.

[Smith 68]

K. C. Smith and A. Sedra, "The current conveyor: a new circuit building block,"
Proc. of the IEEE., pp.1368-1369, 1968.

[Widlar 65]

Ki

Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and
applications therefor," US Patent 7,215,187, May 8, 2007.

R. J. Widlar, "Some circuit design techniques for linear integrated circuits," IEEE
Trans. Circ. Theory, pp.586-590, 1965.

46

IC References: Current Sensors and Active Diodes
On-Chip Current Sensors:
[Ki 98]

W. H. Ki, "Current sensing technique using MOS transistors scaling with matched
bipolar current sources," U.S. Patent 5,757,174, May 26, 1998.

[Lam 04a]

H. Lam, W. H. Ki and D. Ma, "Loop gain analysis and development of high-speed
high-accuracy current sensors for switching converters," IEEE Int'l. Symp. on Circ.
& Sys., pp.V.828–V.831, May 2004.

[Lam 04b]

H. Lam, W. H. Ki, C. Y. Tsui and D. Ma, "Integrated 0.9V charge-control switching
converter with self-biased current sensor," IEEE Int'l Midwest Symp. on Circ. & Sys.,
pp.II.305–II.308, July 2004.

[Lam 07]

Y. H. Lam, W. H. Ki and C. Y. Tsui, "Symmetrically matched voltage mirrors and
applications therefor," US Patent 7,215,187, May 8, 2007.

Active Diodes:
[Lam 06]

[Man 06]

Ki

Y. H. Lam, W. H. Ki and C. Y. Tsui, "An integrated 1.8V to 3.3V regulated voltage
doubler using active diodes and dual-loop voltage follower for switch-capacitive
load," VLSI Symp. on Tech. & Circ., pp.104-105, June 2006.
T. Y. Man, P. Mok and M. Chan, "A CMOS-control rectifier for discontinuousconduction mode switching DC-DC converters," IEEE Int'l Solid-State Circ. Conf.,
pp.358-359, Jan. 2006.

47

IC Design of
Power Management Circuits (III)
Wing-Hung Ki
ECE Dept., HKUST
www.ee.ust.hk/~eeki

Part III
Stability and Compensation

Ki

2

Content
Stability and Compensation
Nyquist criteria
System loop gain
Phase margin vs transient response
Type I, II, III compensators
Compensation for voltage mode control
Compensation for current mode control

Ki

3

Feedback Systems
Consider the feedback system:

in

F(s)

out

G(s)
Note that F(s) and G(s) are ratios of polynomials in s, that is,
F(s) =

nF (s)
dF (s)

G(s) =

nG (s)
dG (s)

The closed loop transfer function is
H(s) =

out
F(s)
F(s)
=
=
in 1 + F(s)G(s) 1 + T(s)

and the loop gain is
T(s) = F(s)G(s) =
Ki

n(s)
d(s)

4

Stability Criteria
Local stability: all poles of T(s) (= all roots of d(s)) are in LHP
System stability:
∗
all poles of H(s) are in LHP
⇒
all zeros of (1+T(s)) are in LHP
⇒
all roots of (n(s)+d(s)) are in LHP
If all functional blocks satisfy local stability, the Nyquist criterion for
system stability is:
∗
Nyquist plot of 1+T(s) does not encircle (0,0)
⇒
Nyquist plot of T(s) does not encircle (-1,0)
If all functional blocks satisfies local stability, the Bode plot criteria
for system stability is:
phase margin φm>0o and gain margin GM>0dB
Ki

5

1st Order Loop Gain Function
T(s) =

Bode Plots

To

|T|

s
1+
p1

To

Nyquist Plot
p1

Im

ωUGF

ω

stable
unit circle

−∞
0
−1
ω = +∞

To

1
-45

o

0−
Re
ω = 0+

To / 2

/A

ω
−45o
−90 o

ωUGF
p1

Ki

6

2nd Order Loop Gain Function
T(s) =

Bode Plots

To
⎛
s ⎞⎛
s ⎞
⎜1 + p ⎟ ⎜1 + p ⎟
⎝
1 ⎠⎝
2 ⎠

|T|

To
p1
p2

Nyquist Plot

ωUGF

Im

ω

stable
/A

−1

φm
ωUGF

0

To

Re

ω
−90 o
−180

Ki

o

φm

7

3rd Order Loop Gain Function
T(s) =

Bode Plots

To

|T|

⎛
s ⎞⎛
s ⎞⎛
s ⎞
⎜1 + p ⎟ ⎜1 + p ⎟ ⎜1 + p ⎟
⎝
1 ⎠⎝
2 ⎠⎝
3 ⎠

To

p1
p2
p3

Nyquist Plot

ωUGF

Im

unstable

ωUGF

(encirclement
of -1)

φm

−1

ω

0

/A
To

Re

ω
−90 o
−180o

Ki

−270o

φm < 0

8

Observations on Loop Gain Function
•

1st order systems are unconditional stable.

•

2nd order systems are stable, but a high damping factor would
cause large overshoot and excessive ringing before settling to
the steady state.

•

For 3rd order systems, if the 3rd pole p3 is less than 10X of the
unity gain frequency ωUGF, the system is unstable.

Hence, for a stable system, the loop gain function could be
approximated by a 2nd order loop gain function with the 2nd pole p2
usually larger than ωUGF to achieve small overshoot.

Ki

9

Loop Gain Function and Transient Response
The transient response of a feedback system is given by
F(s) ⎞
⎛1
⎛1
⎞
v o (s) = L−1 ⎜ × H(s) ⎟ = L−1 ⎜ ×
⎟
⎝s
⎠
⎝ s 1 + T(s) ⎠
where L-1(⋅) is the inverse Laplace transform of (⋅).
The exact transient response is affected by F(s), however, if only
T(s) is considered, we may consider the modified feedback system:
in

F(s)

out

in'

T(s)
1

G(s)
H(s) =
Ki

F(s)
1 + T(s)

out '

H'(s) =

T(s)
1 + T(s)

10

Compensator Considerations
For a loop gain function approximated by a 2-pole function:
T(s) =

To
1
≈
⎛
s ⎞⎛
s ⎞
s ⎛
s ⎞
1 + ⎟ ⎜1 + ⎟
1+ ⎟
⎜
p1 ⎠ ⎝
p2 ⎠ ωUGF ⎜
p2 ⎠
⎝
⎝

The closed loop function (with unity gain
feedback) is
T(s)
1
H'(s) =
=
1 + T(s)
s
s2
1+
+
ωUGF ωUGFp2

Ki

Write H'(s) in standard 2nd order form:
1
ωo = ωUGFp2
H'(s) =
2
1 s
s
1+
+ 2
ωUGF
Q ωo ωo
Q=
p2

|T|

p1

ωUGF
p2

/T

−90 o
−180

o

φm

11

Relationship between p2/ωUGF and φm
k

p2
ωUGF

Q

ωUGF
1
=
p2
k

overshoot
e

−

π
2

4Q −1

phase margin

φm = tan−1

1.316

0.275

30 o

1

1

0.163

45o

3 = 1.73

0.76

0.064

60 o

0.605 ≈ 0.6

0.01

70 o

1 / 3 = 0.577

2.73 ≈ 3

Ki

p2
ωUGF

Note that φm=60o gives an overshoot of 6.4%, and the 1% settling
time (tset) would be very long. By setting p2=3ωUGF, then φm=70o,
and the overshoot is only 1%.

12

Type I Compensator (0Z1P)
The simplest Type I compensator is an integrator with ωUGF = 1/C1R1.
C1
R1

|A|

Vin

Vout

Vref

Vout
1
= − A(s) = −
Vin
sC1R1
Assume Aop(s) is first order with
ωt >> 1/C1R1:

A op

1
≈
A op (s) =
1 + s / ω1 s / ωt
1
⇒ A(s) ≈
sC1R1 (1 + s / ωt )
Ki

ωUGF =

1
C1R1

ω

ωt

/A

ω
−90 o
−180o

13

Type I Compensator (0Z1P)
Type I compensator can be implemented using transconductance
amplifier (OTA). OTA has a very high output resistance ro and
cannot drive resistive loads.
|A|

Vin
Vref

gm

Vout
ro

Using OTA may save one IC pin.
Ki

ωUGF =

Co

Vout
gmro
= − A(s) = −
Vin
1 + sC oro

gmro 1 / C oro

gm
Co

ω

/A

ω
−90 o

14

Type II Compensator (1Z2P)
Type II compensator consists of a pole-zero pair with ωz<ωp, and a
maximum phase boosting of 90o is possible.
R2

|A|

C2

1
C2R 2

C1

ωUGF =
1 / C1R1

R1
Vin
Vref

Vout

Vout
1 + sC2R 2
=−
Vin
s(C1 + C 2 )R1 [1 + s(C1 || C 2 )R 2 ]
A(s) ≈

Ki

(1 + sC2R 2 )
sC2R1 (1 + sC1R 2 )

1
C1R 2

(C1 << C2 )

1 / C2R1

ω

/A

ω
90 o phase
boosting
−90 o

15

Type II Compensator (1Z1P)
Type II compensator can also be implemented using OTA.
|A|
Vin
Vref

gm

1
C2R 2

Vout
ro

R2
C2

Vout
g r (1 + sC2R 2 )
= − A(s) = − m o
Vin
1 + sC2 (ro + R 2 )
A(s) ≈
Ki

gmro (1 + sC2R 2 )
(1 + sC2ro )

gmro

1
C2ro

ωUGF

g
= m
C2

ω

/A

ω
−90 o

16

Type III Compensator (2Z3P)
Type III compensator consists of two pole-zero pairs, and phase
boosting of 180o is possible to compensate for complex poles.
R2
R3

Vin

C3

R1

Vref

|A|

C2

1
C2R 2

C1

Vout

1
C2R1

/A
Vout
(1 + sC 2R 2 )[1 + sC3 (R1 + R 3 )]
=−
+90 o
Vin
s(C1 + C2 )R1 (1 + sC1 || C2R 2 )(1 + sC3R 3 )

(1 + sC2R 2 )(1 + sC 3R1 )
A(s) ≈
sC2R1 (1 + sC1R 2 )(1 + sC 3R 3 )
Ki

(C1 <<C2 , R1>>R 3 )

1
C3R1

1
1
C1R 2 C3R 3

ωUGF
1
=
C1R 3

180o
boosting

ω

ω

−90 o

17

PWM Voltage Mode Control
MP

Vo

L

Vg

MN

RL

ck

C
R1
CMP
Q

R

Q

va

EA
A(s)

S

va

bVo
Vref

ramp
Q

R2

va

Q

ramp
ck

Ki


18

Loop Gains of Voltage Mode CCM Converters
The system loop gain is T(s) = A(s)×H(s), where A(s) is the frequency
response of the EA (compensator). Loop gains of voltage mode PWM
CCM converters with trailing-edge modulation are compiled. Parasitic
resistances except ESR are excluded [Ki 98].
Buck:

Boost:

T(s) = A(s) ×

bVo 1 + sCR esr
.
sL
DVm
+ s 2LC
1+
RL

bVo [1 − sL / (D '2 R L )]
T(s) = A(s) ×
.
D ' Vm
sL
s 2LC
+
1+ 2
D ' R L D '2

b | Vo | [1 − sDL / (D '2 R L )]
.
Buck-boost: T(s) = A(s) ×
DD ' Vm
sL
s 2LC
+
1+ 2
D ' R L D '2
Ki

19

Voltage Mode Compensation (1)
Example: Consider a buck converter with the following parameters:
Vdd=4.2V, Vo=1.8V (D=0.429), Vm=0.5V, b=0.667
L=2μH, C=3.3μF, RL=1.8Ω (Io=1A), Resr=100mΩ, fs=1MHz
The system loop gain is given by
T(s) = A(s) ⋅

5.6 × [1 + s /(3M)]
A(s) × 5.6 × [1 + s /(3M)]
=
1
s
s2
1 s
s2
+
+ 2
1+
1+
2
2.3 390k (390k)
Q ωo ωo

The system loop gain consists of a pair of complex poles, and one
strategy is to use dominant pole compensation.
For a buck converter, the complex pole frequency ωo/2π is 10 to 30
times lower than the switching frequency fs.
Ki

20

80
60

Dominant pole compensation

1330 = 62.5dB
A(s) =

1330
1 + s /10

40
20
0dB

390k
H(s) =

5.6 ⇒ 15dB

0.1

1

10

100

1k

10k

100k 1M

5.6 × (1 + s / 3M)
1
s
s2
1+
+
2.3 390k (390k)2
ω
10M

3M
0o

−90

o

ω
/ A(s)

/ H(s)

−180o

Ki

−270o

21

80

7500 = 77.5dB
T(s) =

60

7500 × (1 + s / 3M)
⎛
1
s
s2 ⎞
(1 + s /10) ⎜1 +
+
⎟
2.3 390k 390k 2 ⎠
⎝

40

ωUGF
= 75k

20
0dB

0o

−90 o
−180

Ki

o

−270o

390k

ω
0.1

1

10

100

1k

10k 100k

1M

10M

ω
/ T(s)

3M

φm =
90 o

/ H(s)

22

Stability inferred from Line and Load Transients
Measuring loop gain could be difficult, and for some circuits, and
especially integrated circuits, due to loading effect and that loopbreaking points may not be accessible, stability is inferred by
simulating or measuring the line transient and/or load transient.
If the circuit is stable and has adequate phase margin, line and load
transients will show first order responses.
If the circuit is stable but has a phase margin less than 70o, line and
load transients will show minor ringing.
If the circuit is unstable, line and load transient will show serious
ringing/oscillation.

Ki

23

L

MP

Vo

i

Vdd

RL

MN
C

R1
CMP
Q

(m1 + mc )R f
va

Ki

EA
A(s)

S

−(m2 − mc )R f
vb

DT

R

Q

va

bVo
Vref

Vdd

R2

i /N
ck

V2I
vb
NR f

ramp from OSC
compensation
ramp

24

Loop Gain of Current Mode Buck Converter (1)
The loop gain of a current-mode CCM buck converter with trailingedge modulation is shown below. Others can be found in [Ki 98].
Buck:

1
1
(1 + sCR esr )
CR f n1D ' T
T(s) = A(s) ×
⎛ 1
1 ⎞
1 1 ⎛ 1 (n1D '− D)T ⎞
2
+
+
+
s + s⎜
⎟
CR L n1D ' T ⎟ n1D ' T C ⎜ R L
L
⎝
⎠
⎝
⎠
b×

mc
m
2 −D
, mc > 2 ⇒ n1 >
m1
2
2D '
2L
and R L <
D' T
with n1 = 1 +

The two poles are in general real.

Ki

25

Loop Gain of Current Mode Buck Converter (2)
If the poles are real and far apart, the denominator could be
simplified.
Buck:

R L || R a
1 + s / ωz
.
Rf
⎛
s ⎞⎛
s ⎞
1+
1+
⎜
ωa ⎟ ⎜
ωt1 ⎟
⎝
⎠⎝
⎠
m
L
Ra =
n1 = 1 + c
(n1D '− D)T
m1

T(s) = A(s) × b.

ωz =

1
CR c

ωa =

1
C(R L || R a )

ωt1 =

1
n1D ' T

For two real poles that are farther apart, pole-zero compensation
could be used to extend the bandwidth.
Ki

26

Current Mode Compensation (1)
Example: Consider a current mode buck converter with the same
parameters as those of the voltage mode converter for comparison.
Vdd = 4.2V, Vo = 1.8V (D = 0.429), b = 0.667, fs = 1MHz, Rf = 1Ω
L = 2μH, C = 3.3μF, RL = 1.8Ω (Io=1A), Resr = 100mΩ, mc = m2
⇒ n1=1.75, 1/n1D’T ≈ 1/1μ
The system loop gain is given by
T(s) = A(s) ×

Ki

0.8(1 + s / 3M)
s ⎞⎛
s ⎞
⎛
1+
1+
⎜
⎟⎜
⎟
290k ⎠ ⎝
880k ⎠
⎝

27

We may assume the poles are far apart and use the simplified
equation, and we have
n1=1.75, Ra=3.5Ω, ωz=3M rad/s, ωa=250k rad/s, ωt1=1M rad/s
The system loop gain is then given by
T(s) = A(s) ×

0.8(1 + s / 3M)
s ⎞⎛
s ⎞
⎛
1+
1+
⎜
⎟⎜
⎟
250k ⎠ ⎝
1M ⎠
⎝

Instead of a pair of complex poles as in voltage mode control, two
separate poles are obtained, and both dominant-pole compensation
and pole-zero compensation could be employed.

Ki

28

80
10000
A(s) =
(1 + s /10)

60

Dominant pole compensation

40
20

250k

0dB

0.8 ⇒ −2dB

H(s)

ω
1M

−20

0o
−90

Ki

o

−180o

3M

ω
1

10

100

1k

10k

100k

1M

10M

/ H(s)

29

80

8000 ⇒ 78dB
T(s) =

60

8000 × (1 + s / 3M)
(1 + s /10)(1 + s / 250k)(1 + s /1M)

40
20

ωUGF
= 80k

0dB

1

10

100

1k

250k
1M
10k 100k

ω
10M

−20

1M
0

o

−90 o
−180

Ki

o

φm
= 70 o

ω

/ T(s)

30

Pole-zero cancellation

60
A(s) =

40

(1 + s / 250k)
(s / 375k)(1 + s / 3M)
375k
250k 3M

20
0dB

ω
1

−20

10

100

1k

10k
H(s)

100k

1M

ω

0o
−90

o

10M

/ A(s)
/ H(s)

−180o

Ki

31

Bandwidth increased by 4 times
to 300k rad/s

60

T(s) =

40

1
(s / 300k)(1 + s /1M)

20
ωUGF = 300k

0dB

1

10

100

1k

10k

100k

−90

−180o

Ki

10M

ω

0o
o

1M

ω

/ T(s)
φm
= 70 o

32

References: Switching Converter Compensation
[Brown 01] M. Brown, Power Supply Cookbook, EDN, 2001.
[Ki 98]

[Ma 03a]

D. Ma, W. H. Ki, C. Y. Tsui and P. Mok, "Single-inductor multiple-output
switching converters with time-multiplexing control in discontinuous
conduction mode", IEEE J. of Solid-State Circ., pp.89-100, Jan. 2003.

[Ma 03b]

Ki

W. H. Ki, "Signal flow graph in loop gain analysis of DC-DC PWM CCM
switching converters," IEEE Trans. on Circ. and Syst. 1, pp.644-655, June
1998.

D. Ma, W. H. Ki and C. Y. Tsui, "A pseudo-CCM / DCM SIMO switching
converter with freewheel switching," IEEE J. of Solid-State Circ., pp.10071014, June 2003.

33

Voltage Mode Converters: Loop Gain Function
In discussing fast-transient converters, one important parameter
is the loop bandwidth.
The loop gain function of the buck converter with voltage mode
control operating in CCM ignoring ESR is given by [Ki 98]
T(s) = A(s) ×

bVo
.
DVm

1
1+

sL
+ s 2LC
RL

The resonance frequency ωo and the pole-Q are
ωo

=

1
LC

Q

=R

C
L

The converter enters DCM at
R L(BCM) =

Ki

2L
D'T

⇒

QBCM =

2 1
D ' ωo T

35

Voltage Mode Converters: Bandwidth Limitation
For voltage mode buck, the ripple voltage is given by

ΔVo
Vo

=

D' 1
8 LCfs 2

If ΔVo/Vo=0.01 and D=0.5, then the complex pole pair is at

ωo
and

= 0.4fs

QBCM

=

2 1
= 10
D ' ωo T

⇒

fo

=

ωo fs
≈
2π 16

To have adequate gain margin GM, say, 6dB, the unity gain
bandwidth fUGF has to be reduced by 10×2=20 times:
fUGF

=

1
f
f
× s = s
20 16 320

If fs=1MHz, then fUGF is at around fs/320 = 3.125kHz.
Ki

36

VM Buck: Loop Gain Function with Rδ
The unity gain frequency fUGF of fs/320 is too low. Fortunately (or
unfortunately), the converter inevitably has parasitic resistors
such as RESR, Rℓ (inductor series resistor), Rs (switch resistance)
and Rd (diode resistance), and the loop gain function is [Ki 98]
T(s)

≈ A(s) ×

where
Rδ

bVo
.
DVm

1

⎛ L
⎞ 2
1+ s⎜
+ CR δ ⎟ + s LC
⎝ RL
⎠

≈ R ESR + R + DR s + D'R d

This Rδ is at least 200mΩ, thus reducing QBCM to around 3. With
GM to be 6dB, fUGF is reduced by 3×2=6 times, and
fUGF
Ki

=

1 fs
f
×
≈ s
6 16 100

If fs=1MHz, then fUGF is at around fs/100 = 10kHz.

37

VM Buck: Dominant Pole Compensation
|T|
60dB

To

ωp (dominant pole)
-20dB/dec

40dB
20dB

100X

ωUGF ωo

ωs
ω

0dB
GM = 6dB
-60dB/dec

/T
0o

−90 o
−180 o
Ki

−270 o

ω

o

−45 / dec
φm

-180o×Q/dec
38

Current Mode Converters: Loop Gain Function
The loop gain function of the buck converter with current mode
control operating in CCM ignoring ESR is given by [Ki 98]

1
1
CR f n1D ' T
T(s) =
⎛ 1
1 ⎞
1 1 ⎛ 1 (n1D '− D)T ⎞
+
+
s2 + s ⎜
⎟ n D' T C ⎜R +
⎟
CR L n1D ' T ⎠
L
⎝
⎝ L
⎠
1
A(s)b ×

with
n1 = 1 +

and

mc
m
2−D
, mc > 2 ⇒ n1 >
m1
2
2D '

R L(BCM) = 2L
D'T

In general, the two poles are real, as discussed next.
Ki

39

Current Mode Converters: Bandwidth Limitation
To compute the upper limit of fUGF w.r.t. fs, we simplify the
current mode case as follows. Let D=0.5 and choose n1=2 such
that sub-harmonic oscillation could be suppressed even for
D=0.667. The loop gain function at heavy load is
T(s)

≈ A(s)b

RL
1
R f (1 + sCR L )(1 + sT)

At RL(BCM)=2L/D’T,
TBCM (s) ≈ A(s)b

Ki

R L(BCM)
Rf

1
(1 + s8T)(1 + sT)

Pole-zero cancellation at ω1=1/CRL should be done at the highest
load current Iomax (smallest load resistance). To achieve φm of 70o,
fUGF should be 3 times lower than f2, and fUGF ≈ fs/20. Hence, a
current mode converter could have a unity gain frequency 5 times
higher than its voltage mode counterpart.

40

IC Design of Power Management Circuits (I)

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