Electronic Workshop Lab Journal Online Classes

1. AMITY SCHOOL OF
ENGINEERING AND TECHNOLOGY (ASET)
Dept. of Electronics and Communication Engineering (ECE)
ELECTRONIC WORKSHOP
Laboratory Journal
COURSE: ECE2308 Electronics Workshop

2. CERTIFICATE
AMITY UNIVERSITY MAHARASHTRA
Established vide Maharashtra Act No. 13 of 2014, of Government of Maharashtra, and
recognized under Section 2(f) of UGC Act 1956
This is to certify that Ms/Mr._____Siddharth
Chhetri_______________________ Enrollment
No.__A70405119003_____________ of Class B.Tech. ECE, Semester
3_ has satisfactorily completed the practical course prescribed by Amity
University Mumbai during academic year 2020-2021 .
Sign of Faculty I/C
Name:
Sign of Faculty I/C
Name:
Sign of Dept. Coordinator
Name:
Department Seal

3. INDEX
Name of Student: Siddharth Chhetri
Enrolment No.:A70405119003
Course Code and Name: ECE2308 Electronic Workshop
Name of Course Instructor: Mr M C Vijaykumar Nadini
Sr
No
Title of Experiment Date of
Performance
Date of
Submission
Page
No
Sign and
Remarks
1 To study CRO 05/08/20 06/08/20
2 Lissajous figure for
T, Frequency, phase
measurement.
02/09/20 03/09/20
3 To study 09/09/20 10/09/20

4. transformer.
4 To implement 2-bit
parallel adder.
11/09/20 12/09/20
5 To know the
concept of Half and
Full subtractor.
17/09/20 18/09/20
6 To implement 2-bit
parallel subtractor.
18/09/20 19/09/20
7 To implement 2-bit
adder-subtractor.
23/09/20 20/09/20
8 To perform parity
tester.
24/09/20 21/09/20
9 To implement
multiplexer.
25/09/20 22/09/20
10 To implement
demultiplexer.
30/09/20 23/09/20
11 To implement 2×1
mux using NAND
gates.
01/10/20 02/10/20
12 To implement 1:2
demux using NOR
gates.
07/10/20 08/10/20
13 To implement 2:4
decoder using 1:4
demux and a
function.
08/10/20 09/10/20
14 Conversion of
Decimal to BCD
encoder.
09/10/20 10/10/20
15 Conversion of BCD
to Decimal decoder.
15/10/20 16/10/20

5. 16 Implement SR latch
using NAND and
NOR gates.
16/10/20 17/10/20
17 Implement
combinational
circuit for traffic
control.
21/10/20 22/10/20
18 Combinational
circuit for given
word problem.
22/10/20 23/10/20
19 SR Latch to SR and
D flip flop
conversion.
28/10/20 29/10/20
20 BCD to Excess-3
code conversion.
29/10/20 30/10/20
21 Study of frequency
response of CE
transistor amplifier.
05/11/20 06/11/20
22 Implement DC
regulated power
supply.
11/11/20 12/11/20
Overall Grade and Remarks:
Name and Sign of Faculty:

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12. Date
Expt. No. 30
Page No.
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17. Date
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Expt. No.
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20. EXPERIMENT 5
Aim:- To perform 2-bit parallel adder.
Apparatus:- OrCAD software.
Procedure:
1. Draw the circuit for 2 bit adder using logic gates and other components
2. The circuit is given as:
3. Make the stimulation as per requirement.
4. Give the input for addition :- A1A0 +B1B0.
5. Run the stimulation and see the result.
Result:
Here, it shows the stimulation for: 11+10

21. Output is 101 denoted by CY.S2Y.S1Y

22. EXPERIMENT-6
Aim:- To know the concept of Half and Full Subtractor.
Apparatus:- OrCAD software.
Procedure:
1. Draw the circuit for half subtractor using suitable logic gates. Here for two bits A and B , the sum
is given by A XOR B and borrow is given by Ā.B.
2. The circuit is given as:
3. Draw the logic diagram for Full subtractor. Here for two bits A and B, there will be a propagation
of borrow from previous operation.
4. Circuit for full subtractor:-
5. Run the stimulation to check the working.
6. Give the input as A and B.(A-B)
Result:
Half subtractor-

23. Here A=1 and B =0
Therefore subtraction, U18A:Y= 1
Borrow, U17A:Y= 0
Full subtractor-
Here Ain=1, Bin= 0 and Cin (which will propagate)= 1
U12B:Y=0 , U15A:Y= 1

24. EXPERIMENT-7
Aim:- To perform 2-bit parallel subtractor.
Apparatus:- OrCAD Software.
Procedure:-
1. Make the circuit for the 2 bit parallel subtractor using logic components.
2. Here, two 2- bit inputs are subtracted using concept of full and half subtractor.
The propagation of borrow takes places here.
3. The circuit for 2-bit parallel subtractor is given as:
4. Make and run the stimulation.
Result:-
Here the two inputs are in11in10 and in21in20 and outputs is BorrowB D1A D0B
The combination in the stimulus is 10-01 and output is 001

26. EXPERIMENT-8
Aim:-To perform 2-bit parallel adder-subtractor.
Apparatus:- OrCAD Software.
Procedure:-
1. Make the circuit using logic components.
2. Here, both operation, addition and subtractions, takes place according to the control
value given at input side. Here control is given by K=0/1.
When K=0, the circuit perform addition. And when K=1, the circuit performs subtraction.
And in the circuit, XOR gates works as buffer when K=0 and inverter when K=1.
3. The circuit is given as:
4. Make and run the stimulation.
Result:
Here the inputs are A1A0 and B1B0 and output is CfB:Y S1A:Y S0B:Y.
For addition ( when k=0), the combination is 01+01 and output is 010.
For subtraction (when k=1), the combination is: 11-10 and the output is 101.

28. EXPERIMENT-9
Aim:- To perform parity tester.
Apparatus:- OrCAD Software.
Procedure:-
1. Make the circuit for parity tester using logic components
2. The parity generating technique is one of the most widely used error detection
techniques for the data transmission. In digital systems, when binary data is transmitted
and processed , data may be subjected to noise so that such noise can alter 0s (of data
bits) to 1s and 1s to 0s.
3. The circuit for parity tester is given by:
4. Make and run the stimulation.
Result:
Here the inputs are STM1,STM2,STM3, STM4 and output is U1C:Y. The combination in inputs
are 01 and 01 and output is 0.

30. Experiment 10
Aim:-To perform function of Multiplexer.
Apparatus:- OrCAD software.
Procedure:-
1. Make the circuit or multiplexer using logic gates.
2. The Multiplexer is provided with ‘n’ number of inputs and give
only one input.
Select line is given by m, n=2^m
Select line decides which output will be preferred.
3. The circuit is given as:
4. Make the stimulation and run the stimulus.
Result:-
Here S0, S1 and G are select lines and enable line respectively.
D0,D1,D2,D3 are the inputs.
U8a:Y is the output

31. In this stimulus for S0 =1 and S1=0 and G=0, D1 is given as output

32. Experiment 11
Aim:- To perform function of Demultiplexer.
Apparatus:- OrCAD software.
Procedure:-
1. Make the circuit for Demultiplexer using logic gates.
2. The demultiplexer is provided with one input and give n outputs.
Select line is given from m, n=2^m.
3. The circuit is given as:
4. Make the stimulation and run it.
Result:-
Here select0, select1 are the select lines and ‘I’ is the single input.
I0, I1, I2, I3 are the corresponding outputs.

33. In this stimulus for select0=0 , select1=1 , output is given by I2=1.

34. Experiment-12
Aim:- To perform 2:1 Mux using NAND gates.
Apparatus:- OrCAD Software.
Procedure:-
1. Make 2:1 mux using only NAND gates.
2. Here, only using NAND gate we can invert the select line.
3. The circuit is given as;
4. Make and run the stimulation.
Result:
Here dstm1 and dstm3 are the two inputs and ‘s’ is the select line.U13D:Y is the output pin.

35. EXPERIMENT 13
Aim:- To perform 1:2 Demultiplexer using NOR gate.
Apparatus:- OrCAD Software.
Procedure:-
1. Make the circuit foe 1:2 demux replacing NAND gates with NOR gates.
2. Here we have one input and 2 output with one select line.
3. Circuit is given as:
4. Make and run the stimulation.
Result:-
Here D is input and S is select line and Y0 and Y1 are the output.

37. EXPERIMENT 14
Aim:- (i) To perform 2-4 decoder using 1;4 demultiplexer.
(ii) To show output of the expression using multiplexer: F(A,B)={0,1,3}
Apparatus:- OrCAD Software.
Procedure:-
1. Decoder function same as demultiplexer as here the input is ‘n’ and outputs are
‘2^n’. Here the input are the two select lines and D act as enable input (active high).
Y1,Y2,Y3,Y4 are the outputs.
D S1 S0 Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
2. The circuit is given as:
3. The truth table for expression F(A,B)={0,1,3}.
A (select
line)
B (input) F o/p
(B)
0 0 1 1
0 1 1
1 0 0 B
1 1 1
4. The circuit for the expression given as:

38. Result:-
Stimulus for 2-4 decoder using 1:4 multiplexer.
Stimulus for expression.

40. EXPERIMENT 15
Aim:- Perform Decimal to BCD encoder.
Apparatus:- OrCAD Software.
Procedure:-
1. BCD is 4-bit binary code representation of decimal digit. BCD code uses four bits to
represent the 10 decimal digits 0f 0-9.
2. Truth table for decimal to binary encoder.
INPUT OUTPUT
9 8 7 6 5 4 3 2 1 0 A B C D
0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 1 0
0 0 0 0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 0 1 0 0 0 0 0 0 0 1 1 0
0 0 1 0 0 0 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0 0 0 1 0 0 1
3. The circuit diagram is given as:-
4. Make and run the simulation .
Result:-

41. The following simulation are for:- 1 (0001) , 3 (0011) , 7 (0111)

42. EXPERIMENT 16
Aim:- Perform BCD to decimal decoder.
Apparatus:- OrCAD Software.
Procedure:-
1. Make the circuit of the decoder using suitable gates and truth table.
2. Truth table for BCD to Decimal decoder is:-
INPUT OUTPUT
A B C D 0 1 2 3 4 5 6 7 8 9
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1
3. The circuit is given as:-
4. Make and run the simulation.
Result:-
The following simulation is for:- 0010 (2) , 0100 (4) , 1000 (8)

44. EXPERIMENT 17
Aim:- The show function of SR latch using NAND and NOR gates.
Apparatus:- OrCAD Software.
Procedure:-
1. A latch is a circuit that has two stable states and can be used to store state information.
2. Truth table for SR latch with NAND gates.
S (set) R (reset) Q (output)
0 0 Invalid state
0 1 1 (set)
1 0 0 (reset)
1 1 No change
3. Truth table for SR latch with NOR gates.
S (set) R (reset) Q (output)
0 0 No change
0 1 0 (reset)
1 0 1(set)
1 1 Invalid state
4. The circuit diagram is given as:
NOR gates-

45. NAND gates-
5. make and run the stimulation.
Result:-
NAND SR latch-
Not allowed state
Set State
Reset state

46. No change state
NOR SR latch-
Invalid state
Reset state
Set state
No change state

47. EXPERIMENT 18
Aim:- Implement combinational circuit for traffic control.
Apparatus:- OrCAD Software.
Procedure:-
1. Design a combinational logic circuit to control the traffic display such that based on the
output of the sensor and microcontroller, only one light should be ON at a time. No two
lights should be ON simultaneously.
2. The truth table is:
R Y G Output
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
3. The circuit is given as:
4. Make and run the simulation.
Result:-
The following stimulus is for – (001) , (011) and ( 101)

48. R=0, Y=0, G=1 and o/p=1
R=0, Y=1, G=1 and o/p=0
R=1, Y=0, G=1 and o/p=0

49. EXPERIMENT 19
Aim:- Design and running combinational circuit for given word problem.
Apparatus:- OrCAD Software.
Procedure:-
1. Word problem- In farm management system, four water pumps with a fixed capacity
are used. The capacity of one pump is not sufficient to water the farm properly. Hence,
it is necessary that more than one water pump should be ON at a time.
2. The truth table for the problem where A , B C and D are four pumps.
A B C D Output
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
3. The circuit is given by-

50. 4. Make and run the stimulation.
Result:-
The output is for the following combination- 0111 , 1000, 0101

51. EXPERIMENT 20
Aim:- Convert SR latch int SR flip flop and D flip flop.
Apparatus:-OrCAD Software.
Procedure:-
1. Make the circuit using SR latch and additional gates.
2. Truth table for SR Flip flop.
Clock S R Q Q’
0 x x No
change
No
change
1 0 0 No
change
No
change
1 0 1 0 1
1 1 0 1 0
1 1 1 invalid invalid
3. The Circuit pf SR flip flop is:-
4. The truth table for D flip flop-
Clock D Q Q’
0 x Q Q’
1 0 0 1
1 1 1 0
5. The circuit of D flip flop is:-

52. 6. Make and run the simulation.
Result:-
For SR Flip flop
U1C:Y is Q and U1D:Y is Q’
For D flip flop
U1C:Y is Q and U1D:Y is Q’

53. EXPERIMENT 21
Aim:- To convert BCD to Excess-3 code.
Apparatus:- OrCAD software.
Procedure:-
1. To convert BCD to excess-3, we have to add 0011 (3) to the BCD code.
2. Truth table for BCD to excess-3.
BCD Excess-3
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
3. The circuit is given as:-

54. 4. Make and run the simulation.
Result:-
The simulation is for 0101 to 1000
And 1001 to 1100

55. EXPERIMENT 22
Aim:- To study the frequency response of Common emitter transistor amplifier.
Apparatus:- OrCAD Software
Theory: The CE amplifier is three basic single stage bipolar junction transistor and use as voltage
amplifier. The input of this amplifier is taken from base terminal and output is collected from
collector terminal. The emitter terminal is common for both the terminals.
Voltage gain =V out/V in
Bandwidth= f2-f1
Procedure:-
1. Make the circuit connection as per the circuit diagram.
2. The circuit is given by
3. Set the input voltage AC= 2V and o/p voltage DC=10V.
4. Make and run the stimulation.
Result:-

56. Av= 34 dB
Bandwidth= 30 MHz - 82 Hz

57. EXPERIMENT 23
Aim :- To implement DC regulated power supply.
Apparatus:- OrCAD Software.
Theory- Bridge rectifier is an alternating current to direct current converter that rectifies the
mains AC input to DC output.
A regulated power supply converts unregulated AC to constant DC. It is used to ensure that
output remains constant even if input changes.
Procedure:-
1. Make the circuit as per the circuit diagram.
2. The circuit is given by:
3. Make and run the stimulation.
Result:-
Across filter-

58. Across the rectifier-
Across Zener diode-