3. TABLE III. FUNCTIONAL CHARACTERIZATION OF R-ULGS GATE
WITH MULTIPLE MISSING CELL DEFECTS.
Observation r-ULG r-ULG-II
No of defected cell→ 1 2 1 2
Output F1 F2 F1 F2 F1 F2 F1 F2
No of defective pattern 8 8 28 28 8 8 28 28
Occurrence of wire function 2 - 15 - - - 2 1
Wire function percentage 25% - 53.57% - - - 7.14% 3.57%
Occurrence of INV function - 2 - 14 - - 1 2
INV function percentage - 25% - 50% - - 3.57% 7.14%
Occurrence of Maj function 6 - 13 - 8 - 24 -
Maj function percentage 75% - 46.42% - 100% - 85.71% -
Occurrence of Minority function - 6 - 12 - 8 - 24
Minority function percentage - 75% - 42.85% - 100% - 85.71%
Occurrence of Undefined function - - - 2 - - 1 1
Undefined function percentage - - - 7.14% - - 3.57% 3.57%
TABLE IV. ADDITIONAL SINGLE CELL DEPOSITION DEFECT OF
R-ULG
Cell Cell r-ULG Output
Position Type F1 F2
P
× Maj(ABC) ABC
+ Maj(ABC) ABC
Q
× Maj(ABC) ABC
+ Maj(ABC) ABC
R
× Maj(ABC) ABC
+ C C
S
× Maj(ABC) ABC
+ Maj(ABC) ABC
III. DEFECT CHARACTERIZATION OF R-ULG
The different cell deposition defects (miss-
ing/displacement/extra deposition of cells) of the r -
ULG gate are investigated here. The defective function of
the proposed r-ULG under single and double cell deposition
(missing/additional) is reported in Table III. The results of
Table III shows that the proposed universal logic: (i) based
on r-ULG shows 75% fault tolerance and (ii) based on r-
ULG-II shows 100% fault tolerance under single cell missing
deposition. It is evident from Table II that the proposed r-ULG
achieves enviable improvement in fault tolerance (85%), area,
cell count and delay. The defective behaviour at the gate
outputs, due to extra cell deposition, is analysed in tables IV
The following observations can be made from the simu-
lation results: (1) In almost all cases, our proposed r-ULG
with undeposited cells (as defects) behaves in the following
two ways: wire functions or MV/MV-like functions. (2) Unde-
posited cell defects occurring in corner cells (cells 5, 7) change
the logic function of the r-ULG to the wire. In all other cases
of single cell missing defect, have no effect on output and thus
confirming the 75% defect tolerant design. In r-ULG-II, due
to introduction of second clock zone it has no influence on
cell missing defect and thus confirms 100% defect tolerant.
(3) In the simulations using the coherence vector engine, the
polarization level never experiences a significant drop under
cell missing defect. In all simulated occurrences, the magnitude
of the maximum polarization is above 0.9 eV (Fig. III). Note
that by definition, the MV-like function set does not include
the MV function.
It can be observed that under one cell missing defect,
the probability of having the correct majority function at the
outputs is 75% for the r-ULG and 100% for the r-ULG-II
whereas the existing fault tolerant QCA logic gates achieve
only 15% success. Again, in double cell missing defect the
proposed r-ULG logics achieve 42-85% tolerance, whereas
existing universal logic gates show 0% tolerance. Even with
multiple undeposited cells, in most cases the proposed r-ULG
produces a stable logic function: either the wire function, or the
majority-like function which are very useful for logic design.
1
2
3
4
5 6
7 8
A
B
C
F2
F1
P
Q
R S
(a) Layout of r-ULG with cell
deposition location
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1 2 3 4
AveragePolarization
# Cell Deposition
MV
MV-like
Wire
Undefined
Total
(b) Average polarization of r-ULG un-
der cell deposition
IV. SIMULATION SETUP
All the designs have been verified using QCADesigner
version 2.0.3 [9] with all default parameter specifications.
V. CONCLUSION
This paper addresses the reliability issues of
majority/minority-based computational structures synthesizing
a 100% fault tolerant universal logic in QCA (r-ULG-II)
having two complementary outputs (F1=F2). Two fault-
tolerant/reliable universal logic gate r-ULG are explored
which possess enviable 75% fault tolerance using single
clock-zone and 100% fault tolerance using multiple clock-
zone under single missing and additional cell defect. A
detailed simulation-based analysis and a characterization of
QCA defects have affirmed the reliability of the proposed
r-ULG against the manufacturing-process variations.
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561574576
![Towards Designing Reliable Universal QCA Logic
in the Presence of Cell Deposition Defect
Bibhash Sen ∗, Rajdeep K. Nath∗, Rijoy Mukherjee∗, Yashraj Sahu† and Biplab K Sikdar‡
∗NIT Durgapur,W.B, India, bibhash.sen@cse.nitdgp.ac.in, †SUIIT Sambalpur, Odisha, India
‡IIEST Shibpur, WB, India, biplab@cs.iiests.ac.in
Abstract—This work targets design of a reliable universal
logic gate in Quantum-dot cellular automata (r-ULG with the
single clock zone, r-ULG-II with multiple clock zone) with hybrid
cell orientations that realizes majority and minority functions
simultaneously with high fault tolerance. The characterization of
the defective behaviour of r-ULGs under different cell deposition
defects is investigated. The outcomes indicate that the proposed
r-ULG provide 75% fault tolerance under single clock zone and
100% under two clock zone.
Keywords—Quantum-dot cellular Automata (QCA), Fault toler-
ant logic, QCA defects, Reliability and Universal logic gate.
I. INTRODUCTION
Quantum-dot cellular automata (QCA) have emerged as
one of the promising new technologies for future generation
ICs to overcome the limitation of CMOS [1], [2]. A QCA
cell consists of four quantum dots positioned at the corners
of a square (Fig. 1(a)) and contains two free electrons [1].
Timing in QCA is accomplished by the cascaded clocking of
four distinct and periodic phases [3] as shown in Fig. 1(f).
The basic structure in QCA is the 3-input majority voter,
MV (A, B, C) = AB + BC + CA (Fig. 1(c)).
Due to the functional incompleteness of majority logic, an
additional inverter is mandatory for majority gate to constitute
the universal function [4]. The importance of the universal
logic in QCA is already highlighted in [4], [5].Till today
different tiles are recognised as the well known fault tolerant
architecture in QCA [6]. Several attempts are already made to
realize fault tolerant structure around QCA logic [4], [7].
In this context, we attempt to design fault tolerant universal
QCA logic that can ensure highly fault tolerant QCA designs.
The major contributions of this work around reliable QCA
architecture can be summarized as follows: (i) A reliable
universal logic gate (r-ULG) is designed towards the reli-
able QCA system. (ii) To maximize the fault tolerance, an
alternative layout of r-ULG with multiple clock zone is also
proposed, referred as r-ULG-II. (iii) Detail characterization of
functional properties of the proposed r-ULG is described. (iv)
The proposed r-ULG achieves a high degree of reliability over
different cell deposition defects.
II. DESIGN OF RELIABLE UNIVERSAL QCA LOGIC
In this paper, a new reliable universal logic gate (r-ULG) is
synthesized coupling a 2×2 tile of rotated cells (called ‘driver
tile’) with non-rotated cells as shown in Fig. 2(a). It uses only
its inherent positional value of output cell in ‘driver tile’ for
inversion logic without disparate additional inverter logic gate.
00
0
11
1 00
0
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1
00001111
00
0000
11
1111
0011
0
00
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11
00001111
00
0000
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1111
0011
0011
00
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111100
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1111
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000000
111111
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111100
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1
0
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000
111
0
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1
00
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1111
00
0000
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111100
00
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11
0
00
1
110
0
1
1
00
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1111
000011110
00
1
11
0011 0
00
1
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0011
0000
00
1111
110000
00
1111
11
00
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100
0
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0000
00
1111
1100
0
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0011
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0
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FMaj
C
B
A
F = AB + BC + CA
A
C
B F
(c)
Input
T/4 T/2 3T/4 T
Outpu
Hold Relese
Switch
Relax
A
OutputInput
A’
A’
A
(d)
Quantum
well
Junction
Tunnel
Tunnelling
Potential
(a)
’+’ Cell
’X’ Cell
B
B
A A
Localised Electron
Binary ’0’
P = −1
Binary ’1’
P = +1
(f)(e)
(b)
45degreeorientation
90−degreeorientati
Fig. 1. QCA basics: (a) Structure of a QCA cell (b) QCA cell with two
polarization (c) Majority voter (d) Inverter (e) Wire-crossing (f) Clocking
C
A
B
F2
F1
(a)
C
A
B
F2
F1
(b)
Fig. 2. QCA cell layout of universal logic using (a) r-ULG (b) r-ULG-II
Hence, maximize the throughput (majority and minority) the
logic circuit. The r-ULG structure simultaneously realizes 3-
input majority voter (MV) and minority voter (MIN) in its two
outputs F1 and F2 (Fig. 2). The output F1 = AB +BC +CA
and F2 = AB + BC + CA. To extend the fault tolerance
capability of proposed r-ULG, an alternative structure using
two clock zones, referred to as r-ULG-II, is also established
as shown in Fig. 2(b).
The universal characterization of its output is shown in
Table I. The QCA-implementation of the proposed r-ULG (Fig.
2) has a cell count of 12 covering an area of 0.01 μm2
.
TABLE I. CHARACTERIZATION OF UNIVERSAL FUNCTIONALITY OF
R-ULG
Inputs Outputs Function
A B C F1 F2 Type
A 0 C AND NAND Universal
A 1 C OR NOR Universal
A φ φ A A
Inverter & Wireφ B φ B B
φ φ C C C
A 0 0 0 1
Constants
A 1 1 1 0
φ=Don’t care value
TABLE II. PERFORMANCE OF R-ULG
Design # MV/MIN # INV Clock Area Fault
gate gate zone (μm2
) tolerance
CMVMIN [8] 01 01 01 0.01 15%
r-ULG (Fig.2(a)) 01 00 01 0.01 75%
r-ULG-II (Fig.2(b)) 01 00 02 0.01 100%
fault tolerance improvement 85%
2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems
978-1-4673-8700-2/16 $31.00 © 2016 IEEE
DOI 10.1109/VLSID.2016.32
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2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems
978-1-4673-8700-2/16 $31.00 © 2016 IEEE
DOI 10.1109/VLSID.2016.32
573
2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems
978-1-4673-8700-2/16 $31.00 © 2016 IEEE
DOI 10.1109/VLSID.2016.32
575](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)