FULL ENJOY Call Girls In Mahipalpur Delhi Contact Us 8377877756
CS304PC:Computer Organization and Architecture Session 6 Instruction cycle.pptx
1. CS307PC:Computer Organization
and Architecture (R18 II(I sem))
Department of computer science and engineering
(AI/ML)
Session 6
by
Asst.Prof.M.Gokilavani
VITS
11/25/2022 Department of CSE (AI/ML) 1
2. TEXT BOOK:
• 1. Computer System Architecture – M. Moris Mano, Third Edition,
Pearson/PHI.
REFERENCES:
• Computer Organization – Car Hamacher, Zvonks Vranesic, Safea
Zaky, Vth Edition, McGraw Hill.
• Computer Organization and Architecture – William Stallings Sixth
Edition, Pearson/PHI.
• Structured Computer Organization – Andrew S. Tanenbaum, 4th
Edition, PHI/Pearson.
11/25/2022 Department of CSE (AI/ML) 2
3. UNIT - I
11/25/2022 Department of CSE (AI/ML) 3
Digital Computers: Introduction, Block diagram of Digital Computer,
Definition of Computer Organization, Computer Design and Computer
Architecture.
Register Transfer Language and Micro operations: Register Transfer
language, Register Transfer, Bus and memory transfers, Arithmetic
Micro operations, logic micro operations, shift micro operations,
Arithmetic logic shift unit.
Basic Computer Organization and Design: Instruction codes,
Computer Registers Computer instructions, Timing and Control,
Instruction cycle, Memory Reference Instructions, Input – Output and
Interrupt.
4. Topics covered in session 6
• Basic Computer Organization and Design
• Instruction codes
• Computer Registers Computer instructions
• Timing and Control
• Instruction cycle
• Memory Reference Instructions
• Input – Output and Interrupt
11/25/2022 Department of CSE (AI/ML) 4
5. Instruction cycle
• The program executed in the computer by going through a cycle for each
instruction.
• The process of fetching, decoding and executing the instruction is called
instruction cycle.
• In basic computer each instruction cycle consists of the following phases:
• Fetch an instruction from memory.
• Decode instruction
• Read effective address if the instruction has indirect address.
• Execute the instruction
• After an instruction is executed, the cycle starts again at step 1, for the next
instruction.
• Note: Every different processor has its own (different) instruction cycle
11/25/2022 Department of CSE (AI/ML) 5
7. Fetch and Decode
• SC is cleared to 0. It is incremented by one so that timing signal goes through
T0,T1 and so on.
• PC is loaded with the address of the first instruction.
• Micro operation are listed below:
11/25/2022 Department of CSE (AI/ML) 7
8. Determine the type of instruction
• Decoder output D7 equals to 1 if instruction is register reference or
input/output reference.(opcode 111)
• Decoder output D7 equals to o if the instruction is memory
reference.(opcode )
• Control then inspects the first bit. If D7=0 & I=1 it is memory
reference with indirect address. If D7=0 and I=0 it is memory
reference with direct address.
• If D7=1 and I=0 it is register reference instruction.
• If D7=1 and I=1 it is input/output reference instruction.
11/25/2022 Department of CSE (AI/ML) 8
9. Execute the Instruction
• Three instruction types are divided into four paths.
• The operation related to timing signal T3 are :
11/25/2022 Department of CSE (AI/ML) 9
12. Input output and Interrupt
• A computer serves no useful purpose unless it communicates with the external
environment.
• Instruction and data stored in memory must come from some input device.
• Computational results must be transmitted to the user through some output device.
11/25/2022 Department of CSE (AI/ML) 12
14. Input output Configuration
• Input Register(INPR) consist of eight bits and hold alphanumeric input
information.
• The one bit input flag(FGI) is control flip flop. It is 1 when information is
available in INPR and cleared to 0 when information is accepted by computer.
• The output register(OUTR) works in similar manner.
• When computer found FGO is 1, the information from AC is transferred to
OUTR and FGO is cleared to 0.
• The output device receives the information and set FGO to 1.
11/25/2022 Department of CSE (AI/ML) 14
16. Input and output instructions
11/25/2022 Department of CSE (AI/ML) 16
17. Program interrupt
• The speed of the peripheral devices are very slow in comparison to that of the
computer.
• So during i/o operation computer will waste time while checking the flag instead
of doing some useful tasks.
• One solution for this problem is that computer won’t check the flag continuously
but get interrupted whenever the flag is set.
• Computer than deviates from what it was doing and take care of the i/o operation.
11/25/2022 Department of CSE (AI/ML) 17
20. Interrupt Cycle
• The interrupt handled by the program can be explained with the help of flow chart.
• When R=0, computer goes through an instruction cycle.
• During execute phase IEN is checked if it is 1, control checks for flags if both are
zero next instruction is executed.
• If either flag is 1 when IEN is 1, R is set to 1 and it goes through the interrupt
cycle.
• In interrupt cycle address in PC is stored in some location so that it can be found
later.
• Here we choose memory location at address 0 to store the return address.
11/25/2022 Department of CSE (AI/ML) 20
21. Topics to be covered in next session 7
• Micro programmed control
11/25/2022 Department of CSE (AI/ML) 21
Thank you!!!