Presentation by Cathal McCabe (Xilinx) from one of our Advisory Board Members.

1. © Copyright 2018 Xilinx
Cathal McCabe, Xilinx University Program
Vision processing

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Agenda
˃ Machine vision
˃ Zynq/Zynq Ultrascale
˃ SDSoC
˃ Libraries
˃ PYNQ
˃ Reduced precision
˃ XUP
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“Machine Vision Market Size to Gain USD 15.46
Billion by 2022 Growing at 8.18% CAGR”
˃ Key areas that can benefit
most from machine vision
Food & beverage
Automotive
Healthcare
˃ Requirements
High speed
Low latency
Low Power
Reliability
˃ =Heterogeneous
architectures
>> 3 *Market Research Future (MRFR) 2017

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Slowing to 3% per year
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Computing performance increase
*John Hennessy and David Patterson, Computer Architecture: A Quantitative Approach, 6/e. 2018

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Zynq-7000 Architeture
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Zynq® UltraScale+ MPSoC System Features
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Scaling the Productivity with Technology
Advancement
Performance / Watt & ‘Any to Any’ Connectivity
EaseofDevelopment
CPU
Zynq SoC &
MPSoC
GPU
ARM SoCs
& DSPs
Zynq SoC &
MPSoC
HLS
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9. © Copyright 2018 Xilinx
˃ ASSP-like programming experience
˃ Full system optimizing compiler
˃ System-level profiling
˃ Expert use model for platform developers
and system architects
The SDSoC Development Environment
C/C++ Development
System-level Profiling
Specify C/C++Functions
for Acceleration
Full system
Optimizing Compiler
Rapid
System Level
Performance
Estimation
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˃ Eliminates manual design of SW drivers and HW connectivity
˃ Automatically calls HLS to generate IPs
˃ Enables reuse of optimized HDL IP Blocks as C-callable libraries
˃ ‘One-click’ function acceleration in Programmable Logic
˃ Rapid system performance and area what-if analysis
SDSoC: Design Flow
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PL
PS
IP
Application
Driver
Datamover
PS-PL interface
IP’s

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˃ Optimized libraries for faster
programming
˃ Available from Xilinx and ecosystem
partners
https://www.xilinx.com/products/design-tools/software-zone/sdsoc.html#libraries
Libraries & Design Examples
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Python Productivity for Zynq

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Frameworks
& Libraries
Development tools
Platforms
HDMI
MIPI
USB3
Machine Learning

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DeePhi Solution Stack for Deep Learning
Core API
Driver
Runtime
Loader
Profiler
Models
Framework
Tools & IP
AI HW Platforms
Compression
Pruning Quantization
Compilation
Compiler Assembler
Face detection Pose estimation Video analytics Lane detection Object detection Segmentation
Z7020 Board Z7020 SOM ZU2 SOM ZU2/3 Card ZU9 Card ZCU102 ZCU104 Ultra96
Darknet

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Python Productivity for Zynq

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*https://xkcd.com/353/

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PYNQ Python Productivity on Zynq
Hardware
Engineers
Embedded software
Engineers
New users are not always hardware designers,
or embedded systems designers
Domain Experts
Software Engineers
Enables more people to program Xilinx
processing platforms, more productively
PYNQ also enables more rapid development for
h/w designers and embedded s/w engineers
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Framework for Zynq, Zynq UltraScale+
APIs
Drivers
Bitstreams
Linux kernel
Python
FPGA
Overlay
fpga_manager sysgpio uio devmem
dma
axi_intc
Apps
Jupyter/
IPython
numpy opencvscikit-learnmatplotlib
PYNQ notebooks
XLNK
xlnk
GPIOPL Interrupt libcma.soMMIO
PYNQ libs
PYNQ IPs
PYNQ overlays
User designs
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Software-style Packaging & Distribution of Designs
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Enabled by new hybrid packages
xDNN, A. Sirasao et al OpenCV, K. Denolf et alIIoT, C. Fritsch et alQNN, M. Blott et al

20. © Copyright 2018 Xilinx
Machine Learning on Xilinx FPGAs with FINN
˃ Experimental framework from Xilinx
Research Labs
˃ Explore low precision deep neural
network inference on FPGAs
˃ FINN Framework
Tool flow for rapid design generation
Templated Vivado HLS library of
streaming components
Ultra low-latency and high performance
with dataflow
Many end-to-end example designs
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https://xilinx.github.io/FINN/

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Summary
˃Zynq architecture ideal for machine vision
˃SDSoC for automated algorithm to hardware
˃Libraries
˃PYNQ
˃Reduced precision DNN

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˃ Vivado
˃ SDSoC
˃ SDAccel
Zynq
MPSoC
Ultrascale
Academic
boards
Workshops
Partnership
program
Teaching
Research
enablement
Technical
Support
Conferences
Design
Contests
Special
Events
http://www.xilinx.com/university

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Adaptable.
Intelligent.