Regarding subjective assignment 2 for Academic writing online course in swayam platform

1. Verilog Programs for Basic Logic Gates
G.R.Sri Sudharsna
Application number:83987459e5b211e988f4d7398acf509e

2. ACKNOWLEDGEMENT
This presentation has been submitted regarding the
subjective assignment 2 in ACADEMIC WRITING online course at
SWAYAM platform

3. AND GATE
module and1(a,b,y); a y
input a,b; b
output y;
assign y=a & b;
endmodule

4. OR GATE
module or1(a,b,y);
input a,b;
output y;
assign y=a | b;
endmodule

5. NOR GATE
module nor1(a,b,q);
input a,b;
output q;
assign q= ~(a | b);
endmodule

6. NAND GATE
module nand1(a,b,z);
input a,b;
output z;
assign z= ~(a & b);
endmodule

7. EX-OR GATE
module exor1(a,b,z);
input a,b;
output z;
assign z= a ^ b;
endmodule

8. EX-NOR GATE
module exnor1(a,b,y);
input a,b;
output y;
assign y= ~(a ^ b);
endmodule

9. NOT GATE
module not1(a,y);
input a;
output y;
assign y= ~a;
endmodule

10. THANK YOU!!!!