The document discusses don't care conditions in digital logic and how to implement Boolean functions using NAND gates. It defines don't care conditions as input combinations that are unspecified in a function. Don't care conditions are indicated with an 'X' in truth tables. Boolean functions can be simplified by treating don't care terms as 0 or 1. NAND gates can be used to implement any Boolean function since NAND is a universal gate. Multilevel logic functions are converted to NAND by replacing AND and OR gates with NAND gates using appropriate graphic symbols and inserting inverters to compensate for bubbles in the diagram.

1. Lecture No 16 : Don’t Care Conditions, NAND Implementation
Digital Logic and Design
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2. Don’t Care Conditions
 So far, we have always assumed that all combinations of
the input values are necessary in our expressions.
 Sometimes there are unspecified combinations within a
function.
 For example, four bit binary has six combinations that are not
used.
 Functions that have unspecified outputs for some input
combinations are called incompletely specified functions.
 These are called don’t care conditions because in most
applications, we do not care what the specification of the
combination is.
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3. Indicating Don’t Care Conditions
 A don’t care condition cannot be specified with a 1 because it
would require the function to always be 1 for the combination.
 Likewise, a don’t care condition cannot be specified with a 0
because it would require the function to always be 0 for the
combination.
 To specify don’t care conditions in a map, we use the letter ‘X’.
 When we choose adjacent squares to simplify the map, the don’t care
minterms can be assumed to be 0 or 1, whichever leads to the simplest
expression.
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4. Simplify With Don’t Care Conditions
 Simplify the Boolean function: F (w,x,y,z) = ∑(1,3,5,9,13)
 It has don’t-care conditions: d(w,x,y,z) = ∑(0,2,7)
F1 = w’x’+y’z = ∑(0, 1, 2, 3, 5, 9, 13)
F2 = w’z+y’z = ∑(1, 3, 5, 7, 9, 13)
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5. Example 3-9
 Simplify the Boolean function: F (w,x,y,z) = ∑(1,3,7,11,15)
 It has don’t-care conditions: d(w,x,y,z) = ∑(0,2,5)
F = ∑(0,1,2,3,7,11,15) ; F = ∑(1,3,5,7,11,15)
Either of two are acceptable
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6. More Examples with Don’t Care
F=A’C’D+B+AC
0
AB
x x
1
00 01
00
01
CD
0
x 1
0
1
1
10
1
x 0
1
1
1
10
1
1 1
x
0
AB
x x
1
00 01
00
01
CD
0
x 1
0
1
1
10
1
x 0
1
1
1
10
1
1 1
x
F=A’B’C’D+ABC’+BC+AC
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7. NAND and NOR Implementations
Digital circuits are frequently constructed with NAND and
NOR implementations:
they are easier to make
they are used in all IC digital logic families
Because of their use, rules have been developed that allow
us to convert Boolean functions using AND, OR and NOT into
the equivalent NAND and NOR logic diagrams.
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8. NAND Circuits
The NAND gate is a universal gate that can be used to
construct any gate, therefore being able to replace all AND
and OR gates.
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9. NAND Notation
A convenient method for creating a NAND circuit is to obtain
the simplified Boolean function in terms of Boolean operators
and then convert the function to NAND logic.
To facilitate the conversion to NAND logic we define
equivalent alternative symbols as shown below for NAND
gate
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10. Two-Level Implementation
The implementation of Boolean functions with NAND gates
requires that the function be in sum of products form.
F = AB + CD
All three diagrams are equivalent
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11. Two-Level Implementation
F = AB+CD+E
F = ((AB)' (CD)' E')' =AB+CD+E
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12. Example 3-10
Implement F(x,y,z)= (1,2,3,4,5,7) with NAND gates
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13. 2-Level NAND Rules
Given a Boolean function, follow these rules to obtain the
NAND logic diagram:
Simplify the function and express it in sum of products
Draw a NAND gate for each product term of the expression that has at least
two literals. This is group of first level gates
Draw a single gate using the AND-invert or the invert-OR graphic symbol in
the second level, with inputs coming from outputs of first level gates
A term with a single literal requires an inverter in the first level, unless the
single literal is already complemented
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14. The general procedure for converting a multi-level AND-OR
diagram into an all-NAND diagram is as follows:
Convert all AND gates to NAND gates with AND-invert graphic symbols
Convert all OR gates to NAND gates with invert-OR graphic symbols
Check all the bubbles in the diagram
Every bubble that is not compensated by another along the same line will
require the insertion of an inverter or complement the input literal
Multilevel NAND Circuits
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15. Multilevel NAND Example
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16. Multilevel NAND Example
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17. end of Lecture
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