This document is a schematic listing for a computer system that includes 44 pages. It provides schematics for components like the T2080 DDR3L memory interface, system power converter, Ethernet ports, USB interfaces, and other components. The document has gone through 5 revisions with changes to components like adding a second DDR3L interface and Ethernet card. It includes the project name, dates, designers, and is copyrighted from 2018-2020.
Repurposing LNG terminals for Hydrogen Ammonia: Feasibility and Cost Saving
Electrical Schematic Open Hardware PowerPC Notebook motherboard v. 0.5
1. 1
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A A
B B
C C
D D
Version Control
Version
V0.1
Date
2018/12
Modifications
First release of Schematics
Page Description
1 SCHEMATIC PAGE LISTING
2
3
SYSTEM BLOCK DIAGRAM
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5
6
7
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T2080 FIRST BANK DDR3L INTERFACE
31
32
T2080 IFC INTERFACE
T2080 NOR and NAND FLASH INTERFACE
T2080 SPI FLASH and SDHC INTERFACE
T2080 SYSTEM LOGIC INTERFACE
T2080 ETHERNET and SERDES INTERFACE
T2080 USB INTERFACE
33
ACB_0001_0
SYSTEM POWER INPUT
T2080 CORE POWER CONVERTOR
SYSTEM CLOCK GENERATORs (cont.)
MECHANICALs
SYSTEM POWER CONVERTORs
CPLD WRAPPER AND IO EXPANDER
CHANGE LIST
SYSTEM POWER CONVERTORs (cont.)
SYSTEM CLOCK GENERATORs
RGMII ETHERNET PORT 1
KEYBOARD INTERFACE
KB_LED_AND_LED
T2080 DUART and I2C DEVICE INTERFACE
T2080 GROUND
T2080 POWER SUPPLY (cont.)
T2080 POWER SUPPLY
ETHERNET PORT CONNECTOR
SATA3 CONTROLLER
SATA3 CONNECTORS
USB3 CONTROLLER CONNECTORS
USB3 CONTROLLER
PCIE CONNECTORS
PCIE BRIDGE
3G LTE MODEM
PCIE BRIDGE POWER
MXM PCIE
MXM VIDEO OUT
I2C WRAPPER
AUDIO CMEDIA
AUDIO CONNECTORS
MAIN POWER
BATTERY CHARGER
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V0.2 2019/09 Second release of Schematics
T2080 SECOND BANK DDR3L INTERFACE
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43
USB_HUB V0.3 2020/04 Third release of Schematics
44
ETHERNET CARD
V0.5
2020/05 Fourth release of Schematics
2020/06
V0.4
Fifth release of Schematics
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PAGE LISTING
0 B1 44
Wednesday, June 17, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PAGE LISTING
0 B1 44
Wednesday, June 17, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
PAGE LISTING
0 B1 44
Wednesday, June 17, 2020
<Variant Name>
2. 1
1
2
2
3
3
4
4
5
5
A A
B B
C C
D D
SYSTEM BLOCK DIAGRAM
ACB_0001_0Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
BLOCK DIAGRAM
0 A02 44
Wednesday, June 17, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
BLOCK DIAGRAM
0 A02 44
Wednesday, June 17, 2020
<Variant Name>
Project
Creation Date Last modify date
Designed by: Controlled by: approved by:
PCB Code BOM file
Sheet of REV.
Format
Copyright (C) 2018-2020, Power Progress Community, Hardware Licensee is CERN Open Hardware Licence v1.2
Page title
BLOCK DIAGRAM
0 A02 44
Wednesday, June 17, 2020
<Variant Name>