pec_en-A1.ppt

Power Electronics Controller
PEC
TRAINING

Chapter 1: The « PEC » racks (structures PIB900x for “IGBT” or “Thyristors” PIB)
Chapter 2: The « backwards » boards
Chapter 3: The CPU board
Chapter 4: The controller board for PIB : PIB100X
Chapter 5: Measuring boards PIB10x
Chapter 6: The firing boards (pulse boards PIB3xx)
Chapter 7: The interface boards Inputs / outputs
Chapter 8: The COUNTING interface boards (for encoders)
Chapter 9: The network boards
Summary

Chapter 1:
The « PEC » racks structures
(PIB900x for “IGBT” or “Thyristors” PIB)

Rack constituent elements
The PEC racks are bought from “ KNURR”. They mainly include:
 1 x 110/220V 1-phase power unit that supplies the +5V/-12V/+12V service voltages.
 1 fan.
 1 rack control module equipped with buttons and indicator lights.
 2 separate areas : 1 x “6U” high area and 1 “3U” high area to mount the boards on slides.
These 2 areas are fitted with backplanes designed for the exchange of signals between the
boards and the provision of power supplies.
“6U” area: It accommodates the usual VME-standard boards and the PIB-standard boards specific
to the PEC (except the PIB3xx firing boards.) All these boards have the following size: Height = 6U
& Pitch = 4TE (20.32mm). To enable the exchanges, the “6U” area is fitted with a VME backplane
and one or more PIB901x backplane boards (these boards are plugged at the REAR of the mother
VME board: P2 connectors of the PIB901x mounted behind the J2 connectors of the VME
backplane.) Remark on VME Backplane: the bus is comprised of 2 rows of connectors: P1 (on top)
which includes 16 data bits and 24 address bits; P2 (at bottom) which includes 16 data bits and 8
address bits. P2 is therefore required to run with 32 bits.
“3U” area: It accommodates the firing PIB3xx board or boards (interface pulses.) Size: Height = 3U
& Pitch = 6TE (30.48mm.) To enable the exchanges, the «3U» area is fitted with one or more
PIB902 backplane boards.

3 sizes of racks
3 sizes of PEC microrack frames are available:
 PIB900 rack:
– Dimensions: L (482mm19‘’) * H (133mm3U) * P (400mm)
– Number of VME bus slots available on J1/J2 VME Backplane («6U» area): 5 slots
identified “01/05/09/13/17”, mounted horizontally.
– Number of pairs of PIB901/902 backplanes (each PIB902 enables 3 x PIB3xx (3U size)
boards to be mounted vertically: 1.
 PIB910 rack:
– Number of VME bus slots available on J1/J2 VME Backplane («6U» area):
12 slots identified “01/05/09/13/17...”, mounted vertically.
– Number of pairs of PIB901/902 backplanes (each PIB902 enables 3 x PIB3xx boards
(3U size) to be mounted vertically): 1 or 2.
 PIB920 rack:
– Number of VME bus slots available on J1/J2 VME Backplane («6U» area):
20 slots identified “01 / 05 / 09 / 13 / 17 / 21 / 25 / 29 / 33 / 37 / 41 / 45 / 49 / 53 / 57 /
61 / 65 / 69 / 73 / 77...”, mounted vertically.
– Number of pairs of PIB901/902 backplanes (each PIB902 enables 3 x PIV3xx boards
(3U size) to be mounted vertically): 3 or 4.

GENERAL
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
M/A
Reset
-12V
5V
VMVME
7750
BIO
232
DIZ
232
PIB
101A
PIB
101
PIB
100C
1 5 9 13 17 21 25 29 33 37 41 45 61 64 70 76 82
PIB
303B
PIB
303B
61 64 70 76 82
PROCESS CPU PIB CPU
SEQUENTIAL TREATMENT
SPEED REGULATION
TORQUE & CURRENT CONTROL
MOTOR FIELD REGULATION
FIRING BOARDS
CONTROL
PROTECTION
SUPERVISING
PIB BOARDS ELECTROTECHNICAL
MEASUREMENTS INPUT
( U, I, N,….)
DIGITAL &
ANALOGICAL
PROCESS I/O
3 FIRING
BOARDS

PIB900 rack: 3 VERSIONS
 PIB900A: 1 PIB901A + 1 PIB902
5 Slots for PIBxxx boards (used in «Marine»
configurations for remote control )
 PIB900B: 1 PIB901B + 1 PIB902
1 Slot for cpu VMIC and 4 slots for PIBxxx boards
(ambient T°: 25°C)
 PIB900C: PIB900B + reinforced Ventilation (ambient T°: 50°C)
 PIB900D: 1 PIB901D + 1PIB902 + reinforced Ventilation (ambient
T°: 50°C)
3 Slots for PIBxxx et 2 Slots for VMIC et process boards
THIS VERSION IS NOT STANDARDIZED
Supplier: KNURR

HARDWARE STRUCTURES
PIB900 rack

Outil complet ,centralisateur et adaptable
PIB900 Rack (small size)
Front view

Top view

PIB900 rack characteristics
--> PIB900D ( with CPU board type VMIC )
Input Voltage
Input frequency
Input current
Output Power
Output voltages
Isolating voltage
EMC environnement
Service temperature
Voltage Switch At the rear of the rack
during
&
for
for
for
V rms Between input and outputs
CEI normalized Tests type:
( with CPU board type VMIC )
( with CPU board type VMIC )
( with standard PIB board type)
& during

PIB910 rack
HARDWARE STRUCTURE

PIB910 rack : 3 VERSIONS
 34012087 : 1 PIB901A + 1 PIB902
5 Slots for PIBxxx and 7 Slots for VMIC and process
boards ( Config. Limited to 1 PIB100 & 3 firing boards )
ex.: DC motor control or Synchrodrive (synchronous)
 34012088 : 2 PIB901A + 2 PIB902
10 Slots for PIBxxx & 2 Slots for VMIC and process
boards ( Config. with 2 PIB100 & 6 firing boards )
Ex: VDM6000 Stand Alone
 34012095 : 34012087 with fan dirty filter
 : 34012088 with fan dirty filter
Supplier : APW

PIB910 RACK : Description 1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
M/A
Reset
-12V
5V
VMVME
7750
BIO
232
DIZ
232
PIB
101A
PIB
101
PIB
100C
1 5 9 13 17 21 25 29 33 37 41 45 61 64 70 76 82
PIB
303B
PIB
303B
61 64 70 76 82
PROCESS CPU PIB CPU
SEQUENTIAL TREATMENT
SPEED REGULATION
TORQUE & CURRENT CONTROL
MOTOR FIELD REGULATION
FIRING BOARDS
CONTROL
PROTECTION
SUPERVISING
PIB BOARDS ELECTROTECHNICAL
MEASUREMENTS INPUT
( U, I, N,….)
DIGITAL &
ANALOGICAL
PROCESS I/O
3 FIRING
BOARDS

PIB910 Rack : Description 2

PIB910 rack : characteristics
 Power : 250 W
 Input voltage : 85 - 264 VAC / 120 - 370 VDC
 Input frequency : 47 - 440 Hz
 Output voltages : +5 VDC 35 A ( Min 3 A ) Ripple 50mV
+12 VDC 10 A ( Min 0 A ) Ripple 120mV
-12 VDC 6 A ( Min 0 A ) Ripple 120mV
 Service temperature : 0 - 40 °C with fan dirty filter
0 - 50 °C without fan dirty filter
ASTEC power supply

8 Slots SCHROFF rack
8 Slots SCHROFF rack
This rack is yet used for SYNCHRODRIVE configuration , but it could be
also used for DC DRIVE applications.
It is equiped with backward board type PIB903 ou PIB904.
- PIB903 is connected back to VME J2 bus like a PIB901X.
-PIB904 is screwed instead of J2 bus .
- PIB903 & PIB904 make the link between CPU PIB100x and PIB10X et
PIB31X
This rack is used when firing boards are 6U sized . ( Ex: PIB314 PIB315
ou PIB310 )

PIB920 Rack (large size)
Example 1 : 4 «backward» pairs - Overview

Example 2 : 3 «backwards» pairs - Front view

Example 2: 3 «backwards» pairs - Rear view

Example 2: 3 «backwards» pairs - Side view

Chapter 2:
The « backplanes » boards

The PIB901x backplane board
(PIB901/901A/901B/901C)
 Essential in power therefore “PEC” applications. It is plugged at the back of the J2 connectors
of a mother VME board.
 It enables one PIB100x board (PIB controller) and from 1 to 4 PIB10x (measurement board) to
be mounted.
 2 functions:
- Ensure the connection of the PIB bus between the PIB100x controller and 1 or more
PIB10x peripheral boards thanks to the P2-x connectors.
- Ensure the link of the pulses and feedback between the PIB100x controller and the
PIB30x pulse boards fastened to the PIB902 backplane (P1 connector, 64 contacts of
PIB901 linked to P1 connector, 64 contacts of PIB902.)
 3 versions:
- PIB 901: basic version; no P2-2 link to PULSE PIB BUS.
- PIB 901A: same as PIB 901, but with a P2-2 link to PULSE PIB BUS
- PIB 901B: same as PIB 901A, but with a P2-5 link not mounted.
The P2-1 connector, located at upper part of the PIB901x, is reserved for mounting the PIB100x
board horizontally (The P2-2 connector also enables a PIB100x to be mounted in case the
backplane board is either a PIB901A or a PIB901B: actually, in these versions, the P2-2 connector
has a link to the PULSE PIB BUS.)

Backplanes boards : PIB901x
- PIB901C : like PIB901 but without P2-5 & P2-4 provided
- PIB901D : like PIB901A but without P2-5 et P2-4 provided
: Basic version. P2-2 not linked with BUS PIB PULSES(1)
: Idem PIB901 but with P2-2 linked with BUS PIB PULSES(1)
: Idem PIB901A but without P2-5 privided (2)

Backplanes boards : PIB901x

The PIB902 backplane board
 Each PIB902 type backplane board enables three PIB3xx firing boards (pulse boards) to be
mounted (“IGBT” or “Thyristor” type.)
 The PIB902 backplane or backplane are plugged at the BACK of the rack, within the “3U”
area. This type of board is supplied with +5V and +12V from the rack through power supply
connectors.
 2 functions:
- Ensure the transmission of the +5V and +-12V low level power supplies via
3 connectors issued from the “power pack” unit of the rack.
- Ensure the exchanges of signals between the boards.
 The PIB902 backplane boards are designed to accommodate the pulse control
interface boards (mounted vertically), via 3 connectors (P2-1, P2-2, P2-3) with
32 contacts (connection from 1 to 3 x PIB30x boards.)
 Each PIB902 backplane is always associated with a PIB901 backplane (via 1
x P1 connector with 64 contacts to fasten a cable for the exchange of signals with
PIB901x), so that the “pulse and pulse feedback” boards be in relation with
the PIB100x controller board which generates the pulses
(36 pulses maximum per PIB100x board.)

Backplanes boards : PIB902

PIB902 makes the link between the PIB100x and the 3 CDP PIB3xx ( pulses emission and
status feedback )

SUPPLY CONNECTIONS :
RED
BLACK
BLACK
YELLOW

VMIVME
7 7 5 0
RST
S
V
G
A
M
/
K
C
O
M
1:2
M
E
Z
Z
A
N
I
N
E
C
A
R
D
L
A
N
1
VMIVME 7750-RACK1-N01-V.101A (7750A01A.DOC)
P5
J3
J1
J2
COMPACTFLASHTM
E13
R P I B
L
A
N
1
J9
E12
E3
E5 E6
E17
E10
E9
E2
CPU PROCESS - VMIC 7750

Ethernet Ports
Ethernet staus led’s :
Green : 100 Mbps network
Yellow : 10 Mbps network
SysFail Led
Power On Led
Hard drive acces Led
Network trafic Led
USB Ports
Serial links
Com1 & Com2
keyboard connection
Screen connection
PROCESS CPU - VMIC 7750

 GENERAL CHARACTERISTICS
Processor : 1.2 GHz
– DRAM Memory : 64Mbytes
– SRAM Memory : 32Kbytes
– Flash Memory : 64Mb
– VME bus connectors
– Ethernet link
– VX WORXS operating system
PROCESS CPU - VMIC 7750

SYS.INI
Processor number 1
Boot window 5
GMT offset (mn) 0
Summer time support Y
CPU frequency 0 . 0 0 0 0 0
Adresse IP 2 0 6 . 6 . 3 . 3 4
Adresse GATEWAY
Network mask 2 5 5 . 2 5 5 . 0 . 0
Second Adresse IP
Second Adresse GATEWAY
Second Network mask 2 5 5 . 2 5 5 . 0 . 0
Tick value (µs) 1 0 0 0
HPCI_reboot allowed N
Automatic forcing validation N
TCP no delay option Y
Ethernet Mbps 1 0
VME arbitration fair mode Y
Internal exchange DRAM Y
MT80 support for external memory N
External exchange memory VME Adresse 0 x 0 , 0
Bypass the SRAM usage for saved memory Y
VERSIONS SYSTEME
HARDWARE VMIC 7 7 5 0 - 7 3 4
SYSTEM HPCI 2 . 1 . 1 2
VMIC : Configuration

 If using Keyboard and screen connected in front of VMIC CPU
VMIC : configuration menu
Default starting mode will be used - Enter to modify
...
HPC0 start mode - You can use any combination of
following values:
[0x00] --> Default start mode
[0x01] --> modify sys parameters
[0x02] --> format sav
[0x04] --> Don't load driver
[0x08] --> Don't detect PMC board
[0x10] --> Don't detect 80MT MVME216
Enter the start mode 0x"…

VMIC : configuration menu
If using P80i :
Right Click on « controller » , Select « info » menu then choose « HPCI config »
Right-click on parameter to change then select « modify » , modify value , then finaly click on
« HPCi update » button

VMIC : execution tasks
Execution of user application program in the VMIC:
Task « on event » activated by
PIB100 interruption bit each Tsynch (
ex:0.4 ms )
Task synchronised on T00 task
( ex: 4 ms )
20 ms Periodic Task
100 ms Periodic Task
1 Cpu
1 Ressource
4 Tasks

VMIC : Tasks priority
‘debug’ system zone
‘fast services’ system zone
‘slow services’ system zone
Priority
Périod
Fast tasks
Normal tasks
Slow tasks
PRIORITY AUTOMATIC CALCULATION
High Service needs
suspending of
application execution
( ex : Target access with
TELNET )
TCP/IP access
Slow Services :
ex : application loader
( loads user application
in the target )
10
40
60
130
160
254
10 ms 1 s 10 s

VMIC : Tasks Configuration
Fast task T00
1= Maximum manual priority On event
Menu « task properties » T00 then « Advanced »

VMIC : Tasks Configuration
Fast task T00 : interruption coding
IT vector Description
IT generating board address
Theoretical cycle duration indicator
LSB 8 bits :
0 -> VME Interruption
1 -> ICV196
2 -> SCN307 or PIB100 (PEC)
3 -> CIB (PEC Marine)
Next 8 bits : interruption level ( IRQ 3 )
Next 8 bits : interruption vector (from 1 to 255)

VMIC : Task Configuration
On event
T01 task :
20= manual priority for fast task

T01 task : Synchronisation to T00 task
Task name to be synchronised with
T00 cycles/T01 cycles ratio

Task T02
Automatic priority T cycle : 20 ms Periodic task

Currently, task priority use is :
T00 : Tc = 0.4 ms Manual priority 1
T01 : Tc = 4 ms Manual priority 5
T02 : Tc = 20 ms Manual priority 8
T03 : Tc = 100 ms Automatic priority
So, fast tasks have a higher priority level than the
signal recorder ( « pertu » ) which priority level is
9.

VMIC : Task monitoring
PIB
PIB_LINK_FLT
Wdog
control
Toggle
PIB Toggle monitoring
( made by module
I2_B100 )
VMIC
Toggle
monitoring
VMIC
&
VME_LINK_FLT
Toggle VMIC
&
Frequency relay
Drive trip
T00 task is monitored by PIB100 board
1

VMIC : Task monitoring
Tasks are monitored by Wdog activation in each task

VMIC : Tasks diagnosis
Running periodic tasks
Waiting event tasks
Menu « Info » in the « ressource »

VMIC : Tasks diagnosis
Menu « Info » in « controller »
CPU load

VMIC : drivers diagnosis
- Select only necessary drivers
- Do not load active drivers ( ex :EGD , N80 , E900 ) if
they are not used , because they can trouble application
tasks .
ν = selected Drivers

VMIC : Used drivers selection
To reach
menu :
Right-Click
on
«controller»
«Properties
»
«Advanced
»
Select the
drivers to
be loaded
Right-click
on the
driver or not

VMIC : version diagnosis
Version of module
librairies installed in
P80 ( PC)
Version of
librairies installed
in target VMIC
Version of engine
installed in P80
(PC)
Version of engine
installed in target
VMIC
Version of VXWorks
loaded in ( VMIC )
Version of
drivers
installed in P80
(PC)
Version of
drivers installed
in target VMIC

VMIC : flash memory erasing
Menu « Info » in « Cpu »
« Script Erase » command is used to erase applications and drivers in target flash
memory ( flash memory is used as an equivalent of a hard disk …)
Reboot PEC rack is required to validate the script erase operation ( 10 seconds before
rack supply again )
Then load again applications and drivers with the « Load & Restart » command ,
launched at « controller » level.

Chapter 4:
The controller board for PIB : PIB100X

 The PIB100x board is the controller board for “IGBT” or “Thyristor” PIB. It is plugged into a
PIB901x backplane board (2 boards maximum can be plugged according to the backplane
version.)
 The function of the controller board for PIB is to control and protect the IGBT or Thyristor
bridges. Among others, the PIB100x board generates pulses (36 pulses maximum per
PIB100x.) Remark: each PIB3xx firing board can supply 12 pulses maximum. There are 3 x
PIB3xx pulse boards maximum for each pair of PIB902-PIB901x backplane. The PIB100x
board also manages the PIB10x measurement boards.
 3 interfaces are available on the PIB100x board:
- ancillary signal Interface (user dialogue)
- upper level interface: using optical CIB line (if PIB100A/F) via ‘CIBlink’ connector or using
VME bus (if PIB100C/E) via P1 connector.
- Peripheral board interface = interface via P2-x connectors with measurement and pulse
boards. P2 connector: 36 lines can be configured.
 PIB100A/C: only 2 combinations are possible: {3*6pulses+3*6feedback}or
{3*12pulses}.).
 PIB100E/F: each block of 6 lines can be configured, hence a large choice of
combinations. Warning: the choice depends on the type of pulse boards used: PIB30x
or PIB31x).
The controller board for PIB: PIB100x
(PIB100A/C/E/F)

PIB100 : General description
PIB100 status
7-segment
display
programmable
test Points T1 & T2
CAN BUS Connection
(future)
Optical fiber for pulses repeat
sending (THYR) or for pulses
blocking on slaves PIB100 (
IGBT )
RS232 link to connect to a
local PC ( Hyperterminal or
FlashIt )
Optical link to communicate
with a CIB (« marine »
configuration)
This links is available on
PIB100A and PIB100F only
VME Interface (
Version >or = V1A )
CPU with clock
40MHz
Board address
jumpers
Strap S11 allows
programmation of
CPU and 2 FLEX
circuits
«Trans» FLEX for
exchanges to VME
bus or optical link
( CIB )
«Pulse» FLEX for
commands and
pulses to firing boards
Connection for
( Max++2) EPLD
programming
0
1

PIB100A : Original Version equipped with an optical link for communication
with CIB board ( Used in « Marine » projects )
PIB100F : Version equipped with an optical link for communication with CIB
board and also equipped with a 2.5 x more powerful FLEX pulse
for monitoring ( firing boards pulse feedback status (Used in
« Marine » projects )
PIB100C : Original Version without optical link ( Used in « Metal » &
« General Drive» projects )
PIB100E : Version without optical link and also equipped with a 2.5 x more
powerful FLEX pulse for monitoring ( firing boards pulse feedback
status ( Used in « General Drive » projects )

PIB100 : Hardware configuration
Les cavaliers S3 à S10 définissent l’adresse XX de la PIB.
La PIB 100C maître doit avoir impérativement l’adresse 0xFF en
hexadécimal (S3 à S9 à 1). C’est elle qui envoie les ITs de
synchronisation pour la tache rapide de la VMIC. ( L’IT utilisée est le
signal IRQ3 )
S10
S9
S8
S7
S6
S5
S4
S3
S11
0 1
S2 S1
1
0
Remarques :
 les switchs S1 et S2 ne doivent pas être connectés Ils sont utilisés
uniquement dans la configuration PIB CIB.
Bit de programmation du Softs de la PIB 100C
0 : permet la programmation des soft via la RS232
VME address of PIB100 : FEBXXyyy
10
PIB100 XX address is configured with S3 to S10 jumpers
PIB100C master board must be addressed 0xFF ( S3 to S10 are set on )
Remember VMIC fast task is synchronized on interruption signal generated by PIB100
( used signal is IRQ 3)
S11 =0 allows PIB100 program load ( via RS232 )
S1 & S2 are used only for CIB configuration

PIB100 : Software configuration
Composant V e r s i o n d e
d é v e l o p p e m e n t
V e r s i o n l u e
a v e c
h yp e r t e r m i n a l
V e r s i o n
l u e à l a
P 8 0
Micro 1 i t h yr i s t o r 1 9
Flex pulse U11 1 g t h yr i s t o r 1 7
Flex trans U09 1 a t h yr i s t o r 1 1
Epld U30 U 3 0 _ v 1 a D 9 0 0 2 : 1 1 x x
For each type , there are 4 pieces ( because there are 4 programmable components ) :
Example for a «Thyristor PIB100 » :
Components programmed with FLASHIT
via PC serial port of PIB100
Components programmed with Max++2
via Jtag port of PIB100
Currently
used
Versions
PIB100C
Thyristor
3 types of software can be loaded in PIB100 board :
- IGBT Inverter Soft
- IGBT AEM Soft
- Thyristor Soft
Device Development
version
version read with
hyperTerminal
version read
with P80

PIB100 : Software versions checking
Using P80 to check versions of the 2 FLEXS and CPU
20 : Type of PIB100 CPU software :
10 for IGBT Inverter
20 for Thyristor
30 for IGBT AEM
17 : CPU software version
11 : Version soft FLEX Trans U09
17 : Version soft FLEX Pulse U11
Expected versions Installed versions

PIB100 : Software versions checking
EPLD U30 version control is made with a PC using hyperterminal.
The PC is connected to PIB100 RS232 port
Ex:
To Read address D9002 , enter L D9002
Screen result is L D9002 11XX
11 --> Version V1A
XX --> Address matching jumpers S3 to S10 of PIB100 (
example : « FF » )

PIB100 : Error display
Fault list of PIB100 Thyristor

SENS :VMIC -> PIB TRAME :Initialisation BLOC PRINCIPAL : BLOC MATERIEL :
Mapping
Nom
bit 15 bit14 bit13 bit12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Entête Numéro de trame Numéro de version Indice de modification
Configuration Matériel rack PIB3xx-3 PIB3xx-2 PIB3xx-1
PIB101A
-2
PIB101A
-1
PIB101-2 PIB101-1 VME
Adresse Strap 10 Strap 9 Strap 8 Strap 7 Strap 6 Strap 5 Strap 4 Strap 3
Configuration Logiciel
Version Logiciel Système Numéro de version Indice de modification
Version Logiciel Flex Numéro version U09 (Transmission) Indice modification U09 (Transmission) Numéro version U11(Pulses) Indice modification U11 (Pulses)
T synchro /T prot Rapport période synchro / période rapide (T protection)
T synchro Période d’échantillonnage de synchronisation (n x 0,4µs)
Words exchange from VMIC to PIB100 when system initialisation
Words exchange from PIB100 to VMIC when system initialisation
SENS :PIB -> VMIC TRAME :Initialisation BLOC PRINCIPAL : BLOC MATERIEL :
Mapping
Nom
bit 15 bit14 bit13 bit12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Entête Numéro de trame Numéro de version Indice de modification
Configuration Matériel rack PIB3xx-3 PIB3xx-2 PIB3xx-1
PIB101A
-2
PIB101A
-1
PIB101-2 PIB101-1 VME
Adresse Strap 10 Strap 9 Strap 8 Strap 7 Strap 6 Strap 5 Strap 4 Strap 3
Configuration Logiciel Type
Version Logiciel Système Numéro de version Indice de modification
Version Logiciel Flex Numéro version U09 (Transmission) Indice modification U09 (Transmission) Numéro version U11(Pulses) Indice modification U11 (Pulses)
T synchro /T prot Rapport période synchro / période rapide (T protection)
DTSYN Ecart entre synchro et mesure (µs)
PIB100 : System Initialisation

PIB100 : parameter checking at
System initialisation
VMIC « expected » system parameters PIB100 « read » system parameters
Must match

VMIC : PEC rack start up
When supplying :
1: VMIC is starting ( boards drivers uploading, user applications loading from FLASH memory,
periodic tasks T20 & T30 starting ) . During this phase , « 2 » is displayed in front of PIB100 .
2: « InitUserDef » VMIC function block is activated to load system parameters from VMIC to PIB100
( soft version, PEC rack hardware config, VMIC fast task T00 period, PIB100 fast task period)
3: PIB100 controls received parameters and compare them to hardware configuration. If conformity
is good , then PIB100 begin running mode and displays « T » or « d » . In case of bad
configuration , PIB100 display toggles between « 2 » and « 3 » .
4: PIB100 begin to emit interruption bits on VME bus to activate VMIC fast task T00 ( 0.4ms) .
5: VMIC task T01 is activated by T00 according defined parameters ( to obtain 4ms )

Chapter 5:
Measuring boards PIB10x

 The function of these boards is to control and protection IGBT or thyristor bridges. These
boards are plugged into PIB901x backplane boards knowing that one PIB100x board
manages two PIB101 or PIB101A boards maximum. The “PIB101 or PIB101A” measurement
interface boards (current, voltage, relaying) can indifferently be used in the NETWORK
BRIDGE, the BRAKING CHOPPER, the DC BUS of the MACHINE BRIDGE or the
EXCITATION.
- PIB101: 8 isolated analog inputs are processed (1 internal processing is performed);
1 analog output; 8 logic inputs; 4 logic outputs (control and protection of thyristor or
IGBT bridges.)
- PIB101A: 8 isolated analog inputs not processed; 1 analog output; 8 logic inputs; 4
logic outputs (control and protection of thyristor or IGBT bridges.)
The PIB10x measurement boards
(PIB101 ou PIB101A)

 PIB101 I/O WITH ANALOGICAL CALCULATION FOR
FLUX OF IGBT AND THYRISTORS INVERTERS
 PIB101A I/O ONLY
 PIB101B IDEM 101A + HARD OVERCURRENT
DETECTION
 PIB101C I/O WITH ANALOGICAL CALCULATION FOR
FLUX ON SYNCHRODRIVE ( THYRISTOR )
PIB101 BOARD
- PEC: GENERAL DESCRIPTION -
LOGICAL & ANALOGICAL INTERFACE

PIB101 N°1 PIB101 N°2
E0 IL0 IL8
E1 IL1 IL9
E2 IL2 IL10
E3 IL3 IL11
Fonctions
dédiées si
le défaut
associé est
validé
E4 IL4 IL12
E5 IL5 IL13
E6 IL6
Fonctions
dédiées si
le défaut
associé est
validé
IL14
E7 IL7 Libre IL15
Libre
PIB101 N°1 PIB101 N°2
S0 OL0 Wdog
PEC
OL4 Libre
S1 OL1 Libre OL5 Libre
S2 OL2 Libre OL6 Libre
S3 OL3 Fonction
dédiée si
le défaut
associé est
validé
OL7 Fonction
dédiée si
le défaut
associé est
validé
PIB101 N°1 PIB101 N°2
SA OA0 Libre OA1 Libre
Analog inputs
impedance adaptation
jumpers
3 input phases test
points . ( used for phase
synchronisation
referencing )
T10 :Current
feedback test point
ID1 or ID3
T16 : Current
feedback test point
ID2 or ID4
T15 : test point for
phase synchro.
reference
S9 :Board
configuration Switch
:
PIB101N°1: S9 à 0
PIB101N°2: S9 à 1
See PIB100 software
technical documentation
for details .
1
2
12
1
2
16
Vh
Vf
Vh
Iß2
9
17

PIB101 : Hardware and software
Configuration
U70
EPLD U70 :
V1D Version
Verify label on
component or
Verify version with
hyperterminal :
Read address DB00C
for PIB101 N°1 and
address DB02C for
PIB101 N°2
Read value must be
XX14
S9 : configuration
Switch of board :
PIB101N°1: S9 = 0
PIB101N°2: S9 = 1
Analogical inputs
jumpers:
No jumper :
2 Kohm impedance for
+/- 10V inputs
With jumper : 500 Ohm
impédance for
+/- 20 mA inputs
Vh
Iβ2

PIB101 : Technical characteristics
8 isolated analogical inputs (10V or 20mA <--> +/- 2047 pts)
Analogical inputs are grouped by 4 inputs with a common 0 Volt
for each group .
1 Not isolated analogical input (10V <--> +/- 2047 pts).
8 logical decoupled inputs (+24V) with a common 0 Volt.
4 decoupled logical outputs (+24V)
SL2 and SL3 are volt free
SL0 and SL1 have a common 0 Volt
In case of PIB100 Wdog fault all outputs are reset to 0

PIB101 : measurement treatments
iu
iw
iu2
iw2
Traitement des
courants
(cf. 4.1.1)
iv
ih
i
i
i
i
Détection de
surintensité
(cf. 4.2)
OC
i
i
Traitement des
tensions
(cf. 4.1.2)
vu
vv
vw
vh
e
e
Elaboration des flux
(cf. 4.1.3)


Filtrage et sélection
(cf. 4.1.4)
Filtrage et sélection
(cf. 4.1.4)
i2
/vf
i2
/eh
vf
e
e
vf
i
ih
i
Instantaneous
overcurrent
detection
current
treatment
Selection
and filtering
Selection
and filtering
Flux
calculations
Voltage
calculations

PIB101 : Current treatment
T17

PIB101 : Current treatment
: SIV=0
: SIV=1
VDM6000 Synchrodrive ordrive continu

PIB101 : voltage treatment
Generator convention is used for e.m.f.
Involving this kind of relation :
K is the derivator time constant

R , L are used for Synchrodrive applications type
M is used for synchrodrive applications where double star coiled motor is used .( 2 coils by phase 30 °shifted )
For DC motor drives , R and L could be used for « gap filling »function of PIB101 ( to hide voltage holes caused by U ,
V , W voltage measurement during short cicuits period of thyristor commutations
CAUTION ! « gap filling » is active only when CT are directly connected to PIB101 Iu and Iw inputs .
In case of PEC DC drive, CT are first connected to an adaptation circuit ( SCA602A ) and « gap filling » cannot be
used!
PIB101 : voltage treatment
K is the derivator time constant

PIB101 : Flux treatment
The 2 bits VSEP (validation selection
E’) & SEPR(selection E’ reverse) are
used to choose the sign of E’ image
according to rotation direction :
. VSEP= 0  no compensation
. VSEP= 1 et SEPR= 0  forward
. VSEP= 1 et SEPR= 1  reverse
This selection allows to consider
motor rotation direction into Flux
calculations for synchrodrives
Available values for
PIB101.
Values for PIB101C are
not the same .
Integration T.C.
Anti-derivation T.C.

PIB101 : Flux treatment
( Integrator transfer Function )
-anti-derive system (A.D.) is
selected by 2 bits EAD et MAD :
. EAD = 1  anti-derive in use
. MAD = 1  memory anti-derive
(with EAD = 1)
( Case of PEC drive for DC motor )
=0
unused
Static gain :
Cutting frequency of this 1st order filter is :
used
High cutting frequency :
Low cutting frequency :

PIB101 :Signal Commutation
Homopolar signal selection ,
current or voltage depending on
user application .
User application set the status of
SVH ( / SIH )
For DC drive PEC , SVH =1
Pairs of measured signals EH/Iα2
and Vf/Iβ2 are multiplexed before
conversion. Signals are
alternatively read at the same
address, so PIB100x reads and
sorts measurement signals .
PIB100 controls multiplexing of
signals by cyclic action on SEH ,
SIA, SVF et SIB switch.
T9
T17
Gives a Proper frequency of
And a muffling coefficient of

PIB101 : Hard. overcurrent detect.
Hardware OC detection is only made with the 2 first current measurements of PIB101
( ID1 et ID3 ). The 2 others ( ID2 et ID4 ) have no OC detection .
For this reason, Hardware OC detection is not used for Synchrodrive or DC motor PEC

SOFT PIB100 : Current signals
commutation
According to the kind of current signal (continuous or alternate ) Switch SID et SID2 are
set by the user application program.
If SID or SID2 = 0, the alternate current measurement « Ibeta » can be used.
If SID or SID2 = 1, the continuous current measurement « Id » can be used.
For DC motor PEC or Synchrodrive applications , SID et SID2 are set to 1
1st
current
mesure
of
PIB101:
ID1 or
ID3
2nd
current
mesure
of
PIB101:
ID2
orID4
Current
«direct»
measure
1
Current
«direct»
measure
2

SOFT PIB100 : offset Measurement
16
échantillons
16
échantillons
valeur
moyenne
valeur
moyenne
...
...
moyenne glissante
offset
Validation Order of
offset mesure for
each ana input
Validation of
offset mesure:
1 for each ana
input
CAUTION! : offset measuring
produces a lot of load for PIB100
CPU. Then this function is only
available for 2nd génération of
PIB100 ( PIB100E/F) or on
PIB100C with IGBT software
Offset measurement on a
«thyristor» PIB100C type can
generate an « over-flow : o » fault .
Module I2_B101
Module O2_B100
Sliping average
Samples Samples
Average Average
Average

PIB101C : Technical characteristics
Idem PIB101 for general characteristics
Only integrator characteristics are changing for flux
calculation :
- PIB101: gain -1 to 47 Hz with T.C. equal to
23x256/ Fc ( 1< Fc < 255 )
- PIB101C: gain -1 to 234 Hz with T.C. equal to
23x256/ Fc ( 1< Fc < 255 )

PIB101A : General description
PIB101A N°1 PIB101A N°2
E0 IL16 IL24
E1 IL17 IL25
E2 IL18 IL26
E3 IL19 IL27
E4 IL20 IL28
E5 IL21 IL29
E6 IL22 IL30
E7 IL23
Libre
IL31
Libre
S0 OL8 OL12
S1 OL9 OL13
S2 OL10 OL14
S3 OL11
Libre
OL15
Libre
SA OA2 Libre OA3 Libre
Analogical inputs
impedance
adaptation jumpers:
S9 : configuration
Switch :
PIB101AN°1: S9 à 0
PIB101AN°2: S9 à 1

PIB101A : Hardware and software
configuration
EPLD U70 :
V1C Version
Verify label on
component or
Verify version with
hyperterminal :
Read address ????
for PIB101A N°1 and
address ????? for
PIB101A N°2
Read value must be
XX13
S9 : configuration
Switch :
PIB101A N°1: S9 =0
PIB101A N°2: S9 =1
Analogical inputs
jumpers:
No jumper :
2 Kohm impedance for
+/- 10V inputs
With jumper : 500 Ohm
impédance for
+/- 20 mA inputs
U70
1 0

PIB101A : Technical characteristics
8 isolated analogical inputs (10V or 20mA <--> +/- 2047 pts)
Analogical inputs are grouped by 4 inputs with a common 0 Volt
for each group .
1 Not isolated analogical output (10V <--> +/- 2047 pts).

PIB101B : Technical characteristics
isolated analogical inputs (10V or 20mA <--> +/- 2047 pts) Analogical
inputs are grouped by 4 inputs with a common 0 Volt for each group .
1 Not isolated analogical output (10V <--> +/- 2047 pts).
1 analogical « OC » detection made on inputs IA3 , IA4 , IA6 in such a
way that OC = 1 when [ IA1 or IA3 or IA4 ] become greater than 2XSeuil
Imax ( Imax < 4095 )

Chapter 6:
The firing boards
(pulse boards PIB3xx)

 These are Gate Drive control interface boards for IGBT or Thyristors. These boards are
plugged into one or more PIB902 backplane boards at the rate of 3 pulse boards maximum
per PIB902. The PIB902 makes always a pair with a PIB901x backplane board via a 64-wire
cable. A PIB3xx pulse board manages a maximum of 12 pulses. The PIB3xx pulse boards
features a “3U” format (height) and a pitch of «6TE». They are mounted vertically.
 Function: The board ensures the optical adaptation of the pulses and feedback between the
PIB100x and the power component control DRIVERS.
- There are pulse boards for thyristor PIB and IGBT PIB.
- The pulses can be electrical (copper media) or optical (fiber media.)
- The boards can be fitted with feedback
 Refer to the table below for choosing the PIB3xx.
 The exchange with the PIB100x is made via P2 connector fitted with 36 lines which can be
configured as input or output, by block of 6 lines (6 blocks.)
- PIB30x: accept 2 combinations only: {3*6pulses+3*6feedback}or {3*12pulses}.
- PIB31x: allow all combinations (ex: 12 outputs and 24 inputs.)
The PIB3xx pulse boards
(PIB301/301A/301B/302/302A/303A/303B/304A/305B...)

 The different types of 3U PIB pulse boards are as follows:
6 pulses
with supply 24VDC
6 pulses
without supply
12 pulses
without supply
12 electrical emissions Nonexistent board Nonexistent board PIB301B replaced by
PIB305B : IGBT & Thyristors
6 electrical emissions &
6 electrical feedbacks
PIB301 : IGBT & Thyristors PIB301A : IGBT & Thyristors Nonexistent board
6 electrical emissions &
6 optical feedbacks
PIB302 : not developped PIB302A : not developped Nonexistent board
12 optical Emissions Nonexistent board Nonexistent board PIB303B : Thyristors. Will be
developped on demand
6 optical Emissions &
6 optical feedbacks
Nonexistent board PIB303A : Thyristors
PIB304A : IGBT
Nonexistent board
The «3U» PIB3xx pulse boards

 6U boards
PIB310 : 8 optical emission + 8 optical feedback for thyristor (silice fiber)
PIB315B : 24 optical emission for thyristor
PIB314B : 12 optical emission + 12 optical feedback for IGBT ( plastic fiber )
PIB314C : 18 optical emission + 18 optical feedback for IGBT (plastic fiber )
PIB313x : 18 optical emission + 18 optical feedback for Thyristor (silice fiber) ( future )
The «6U» PIB3xx pulse boards

 Remarks:
- The names with no index (PIB301 and PIB 302) correspond to the boards with
24VDC/1A power supply (the 24VDC supply is generated from the « low level » power
supplies of the rack.)
- The names with no index or with « A » index correspond to the boards with
6 emissions.
- The names with « B » index correspond to the boards with 12 emissions.
- Only one board with power supply can be mounted in the PIB rack. This board must be
plugged into the first slot.
FEEDBACKS :
 The pulse feedback information, issued from the power component drivers, is received by the
PIB3xx before being transmitted to the PIB100x.
 They enable to know if the pulses have been properly transmitted between the PIB100x and
the drivers.
PIB3xx pulse boards

PIB305B : General description
PIB100 generates 2x6 pulses which are sent to PIB305B via P1 connector and
PIB901x,PIB902 backplane boards . Each pulse is transmited to J1 ( bridge 1 ) and J2 (
bridge 2 ) front connectors after amplification ( 12v supplied) then LC filter for output
protection.
Firing output
pulses :
12 V / 1 A max
(for 1 pulse)

S9 = 0
CDP1 and CDP2
S9 = 1
CDP2 and CDP3

-Emitters = type Agilent
HFBR1414T
-connection = optical cable
(ref. FT2G0024, FT2G0056
ou FT2G0057) with 2 metalic
ST connectors :
-fiber HCS 200/230 – HCP
-External diameter 1,5mm ±
0,2
-Protection covering 0 kevlar,
0 halogen
Carte Fille PIB 602
T
P1
+ 5V
0V
6Pulses
bridge1
PIB100x
Pu3-1
Pu4-1
6Pulses
bridge2
PIB100x
Amp. Pu1-1
Pu2-1
Pu5-1
Pu6-1
T
T
T
T
T
T
Pu3-2
Pu4-2
Amp. Pu1-2
Pu2-2
Pu5-2
Pu6-2
T
T
T
T
T
E2-1
E2-2
E2-3
E2-4
E2-5
E2-6
E1-1
E1-2
E1-3
E1-4
E1-5
E1-6
Caution: FUTURE
Plastic fiber 62,5 125
with metallic ST
connector

Chapter 7:
The interface boards
Input / output

 The “ ICV ” boards : builder = “ ADAS ”
- ICV196: 96 logic I/O (12 groups of 8 CHANNELS, programmable as I or O)
- ICV150: 32 differential analog inputs, or 64 single analog inputs
- ICV100...
 The “ MI ” boards: builder = “ Midi Ingénierie ”
- MI16IAO : 16 analog outputs
 The “ xxx 232 ” boards: builder = “ EAC ” (Germany)
- DEP232: Board with 32 logic inputs
- DAP232: Board with 32 logic outputs
- ADU232: Board with 16 analog inputs
- DAU232: Board with 16 analog outputs
- BIO232: Board with 16 logic inputs and 16 logic outputs (mixed)
- ADA232: Board with 8 analog inputs and 8 analog outputs (mixed)
The Input / Output boards

EAC boards
DAP232
Digital 32 OUT
DEP232
Digital 32 IN

EAC boards
DAU232
Analog 16 OUT
ADU232
Analog 16 IN

EAC boards
BIO232
Dig. 16IN + 16OUT
ADA232
An. 8IN + 8OUT

Chapter 8:
The COUNTING interface boards
(for encoders)

 The “ ICV ” boards: builder = “ ADAS (Ex JS) ”
- ICV306: 6 counting channels / PG axes (for INCREMENT coders)
 The “ MI ” boards: builder = “ Midi Ingénierie ”
- MI6AX : 6 counters / 6 PG axes
 The “ xxx 232 ” boards: builder = “ EAC ” (Germany)
- DIZ232: Counting board for INCREMENTAL encoder (8 counters)
- SSI232: Encoder board for ABSOLUTE encorder - gray or binary code - enables the
connection of 4 SSI interface encoders (Synchronous Serial Interface)
The COUNTING interface boards

MIDI board
DIZ232
Counter, 8IN

P.G. interface adaptation board SCN675

AEC board
SSI232
Encoder i/f, 4IN

 CAN232: CAN bus board
 VLIO : board for Optobus network, in optical fiber. Dedicated to variable speed drives.
 VLIO11 and 21: screw connector
 VLIO41: socket connector
 GSM100 & HE700GEN200: boards for N80 network (dedicated to PLCs)
 IBSVME6H: boards for Interbus-S network
The network boards

Interbus S
Phoenix Contact
Interbus S G4 range :
Serial bus :
 operates as data ring (go/return
lines in 1 cable)
 twisted-pair or optic fibre cable
 bus length up to 13 km
 full-duplex communication
 data rate: 500 kbaud
 up to 4096 I/O bits
 wide range of analogue and
digital input/output modules
remote bus
(max 13km)
controller board
in VME sub-rack
local bus, up to 8 I/O modules
IBS VME6H SC/I-T
term’n
module
bus tree, up
to 16 levels
term’n
module
term’n
module
term’n
module
term’n
module
segmen
t (max
400m)
Interbus S

CAN bus
CAN bus range :
Serial bus, multi-master ability :
 CANopen comms. protocol
 data rates : 10 kbaud to 1 Mbaud
 bus length :
 max. 5000m at 10 kbaud
 max. 25m at 1 Mbaud
 many intermediate options
 CAN232.1 has 4 CAN ports
 up to 110 nodes per port
CAN bus
controller board
in VME sub-rack
CAN
232.1
up to 110 nodes
can be connected
to the bus on each
of the 4 ports

Profibus
Sutherland-Schultz Tech (SST)
Profibus range :
Serial bus :
 vendor independent and open
fieldbus
 data rates : 9.6kbaud to 12Mbaud
 length depends on baud rate :
 19.2 kbaud : max 1200m
 12 Mbaud : max 100m
 many intermediate options
 up to 127 stations
 exchange up to 244 bytes per
station and per direction
controller board
in VME sub-rack
5136-PFB-VME
Profibus
I/O modules (up to 244 bytes)
bus
i/face
bus
i/face
bus
i/face
up to 127 stations on the network

N80 bus
Horner Electric
N80 bus range :
Serial bus :
 daisy-chain token passing bus
 data rates : 38.4/76.8/153.6
kbaud
 bus length :
 max 2500m at 38.4 kbaud
 each device can manage up to
128 bytes for I/O data
 wide range of analogue and
digital input/output modules
dual channel
controller board
in VME sub-rack
ALSPA N80 bus
Bus Interface Units (BIU) :
 max 16 at 38.4 kbaud
 max 32 at 76.8 or 153.6 kbaud
HE700 GEN200
I/O modules (up to 128 bytes)
bus
i/face
bus
i/face
bus
i/face

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