Chip specification

Final Project
System on Chip Specification
TramelBlaze, UART & MIB
CECS 460: System on Chip Design
Paul Valenzuela
018469189
Submitted On:
May 12, 2020
COLLEGE OF ENGINEERING
Department of Computer Engineering and Computer Science

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Paul Valenzuela
Date:
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Document Name:
Final Specification
This document contains information proprietary to the CSULB
student that created the file – any reuse without adequate approval and
documentation is prohibited.
In submitting this file for class work at CSULB I am confirming that this is
my work and the work of no one else.
In the event, other sources are utilized I will document
which portion of code and who is the author.
In submitting this project, I acknowledge that plagiarism in student
project work is subject to dismissal from the class.
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TABLE OF CONTENTS
I. INTRODUCTION.................................................................................................................................... 6
I.1 PURPOSE ............................................................................................................................................. 6
II. EXTERNAL DOCUMENTS.................................................................................................................. 7
II.1 TRAMELBLAZE ................................................................................................................................ 7
II.1.1 Detailed Block Diagram ............................................................................................................... 7
II.1.2 Data Transmission........................................................................................................................ 8
II.1.3 Instructions ................................................................................................................................... 9
II.1.4 Software Design.......................................................................................................................... 10
II.2 NEXYS A7 ........................................................................................................................................ 11
II.2.1 Hardware.................................................................................................................................... 11
II.2.2 Input / Output.............................................................................................................................. 12
II.2.3 UART Configuration................................................................................................................... 12
III. REQUIREMENTS............................................................................................................................... 13
III.1 INTERFACE......................................................................................................................................... 13
III.2 PHYSICAL .......................................................................................................................................... 14
IV. TOP LEVEL DESIGN......................................................................................................................... 15
IV.1 DESCRIPTION..................................................................................................................................... 15
IV.2 TOP LEVEL DIAGRAM........................................................................................................................ 15
IV.3 DETAILED LEVEL DIAGRAM.............................................................................................................. 16
IV.4 DATA FLOW DESCRIPTION ................................................................................................................ 17
IV.5 INPUT / OUTPUT................................................................................................................................. 17
IV.6 PIN ASSIGNMENT............................................................................................................................... 18
IV.7 ELECTRICAL CHARACTERISTICS........................................................................................................ 18
IV.8 CLOCK .............................................................................................................................................. 18
IV.9 RESET................................................................................................................................................ 18
IV.10 SOFTWARE....................................................................................................................................... 19
V. EXTERNALLY DEVELOPED BLOCKS .......................................................................................... 30
V.1AISO................................................................................................................................................... 30
V.1.1 Description.................................................................................................................................. 30
V.1.2 Top Level Diagram...................................................................................................................... 30
V.1.3 Input / Output.............................................................................................................................. 30
V.1.4 Register Map ............................................................................................................................... 30
V.2 TRAMELBLAZE................................................................................................................................... 31
V.2.1 Description.................................................................................................................................. 31
V.2.2 Top Level Diagram...................................................................................................................... 31
V.2.3 Input / Output.............................................................................................................................. 31
V.2.4 Register Map ............................................................................................................................... 31
VI. INTERNALLY DEVELOPED BLOCKS.......................................................................................... 32
VI.1 MEMORY BLOCK INTERFACE ............................................................................................................ 32
VI.1.1 Description................................................................................................................................. 32
VI.1.2 Top Level Diagram .................................................................................................................... 32
VI.1.3 Input / Output............................................................................................................................. 33
VI.1.5 Register Map.............................................................................................................................. 33
VI.1.5 State Machine ............................................................................................................................ 34
VI.2 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER............................................................ 35
VI.2.1 Description................................................................................................................................. 35
VI.2.3 Detailed Level Diagram............................................................................................................. 36
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VI.2.4 Input / Output............................................................................................................................. 37
VI.3 TRANSMIT ENGINE ............................................................................................................................ 38
VI.3.1 Description................................................................................................................................. 38
VI.3.4 Verification ................................................................................................................................ 39
VI.3.5 Input / Output............................................................................................................................. 40
VI.3.6 Register Map.............................................................................................................................. 40
VI.4 TRANSMIT SHIFT REGISTER............................................................................................................... 41
VI.4.1 Description................................................................................................................................. 41
VI.4.3 Input / Output............................................................................................................................. 41
VI.5 TRANSMIT BIT10 BIT9 DECODER ...................................................................................................... 42
VI.5.1 Description................................................................................................................................. 42
VI.5.3 Input / Output............................................................................................................................. 42
VI.5.4 Logic Table ................................................................................................................................ 42
VI.6 TRANSMIT CONTROLLER................................................................................................................... 43
VI.6.1 Description................................................................................................................................. 43
VI.6.3 Input / Output............................................................................................................................. 43
VI.7 TRANSMIT BIT COUNTER................................................................................................................... 44
VI.7.1 Description................................................................................................................................. 44
VI.7.3 Input / Output............................................................................................................................. 44
VI.8 TRANSMIT BIT TIME COUNTER.......................................................................................................... 45
VI.8.1 Description................................................................................................................................. 45
VI.8.3 Input / Output............................................................................................................................. 45
VI.9 RECEIVE ENGINE ............................................................................................................................... 46
VI.9.1 Description................................................................................................................................. 46
VI.9.4 Verification ................................................................................................................................ 47
VI.9.5 Input / Output............................................................................................................................. 48
VI.9.6 Register Map.............................................................................................................................. 48
VI.10 RECEIVE SHIFT REGISTER................................................................................................................ 49
VI.10.1 Description............................................................................................................................... 49
VI.10.2 Top Level Diagram .................................................................................................................. 49
VI.10.3 Input / Output........................................................................................................................... 49
VI.11 RECEIVE STATE MACHINE............................................................................................................... 50
VI.11.1 Description............................................................................................................................... 50
VI.11.3 State Transition Diagram......................................................................................................... 50
VI.11.4 Input / Output........................................................................................................................... 50
VI.12 RECEIVE CONTROLLER.................................................................................................................... 51
VI.12.1 Description............................................................................................................................... 51
VI.12.3 Input / Output........................................................................................................................... 51
VI.13 RECEIVE BIT COUNTER ................................................................................................................... 52
VI.13.1 Description............................................................................................................................... 52
VI.13.3 Input / Output........................................................................................................................... 52
VI.13.4 Logic Table .............................................................................................................................. 52
VI.14 RECEIVE BIT TIME COUNTER .......................................................................................................... 53
VI.14.1 Description............................................................................................................................... 53
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VI.14.3 Input / Output........................................................................................................................... 53
VI.15 BAUD RATE DECODER..................................................................................................................... 54
VI.15.1 Description............................................................................................................................... 54
VI.15.3 Input / Output........................................................................................................................... 54
VI.15.3 Register Map............................................................................................................................ 54
VI.16 POSITIVE EDGE DETECT .................................................................................................................. 55
VI.16.1 Description............................................................................................................................... 55
VI.16.3 Input / Output........................................................................................................................... 55
VI.16.4 Register Map............................................................................................................................ 55
VI.17 RS FLOP .......................................................................................................................................... 56
VI.17.1 Description............................................................................................................................... 56
VI.17.3 Input / Output........................................................................................................................... 56
VI.17.4 Register Map............................................................................................................................ 56
VI.18 READ ADDRESS DECODE................................................................................................................. 57
VI.18.1 Description............................................................................................................................... 57
VI.18.3 Input / Output........................................................................................................................... 57
VI.18.4 Register Map............................................................................................................................ 57
VI.19 WRITE ADDRESS DECODE ............................................................................................................... 58
VI.19.1 Description............................................................................................................................... 58
VI.19.3 Input / Output........................................................................................................................... 58
VI.19.4 Register Map............................................................................................................................ 58
VII. CHIP LEVEL VERIFICATION....................................................................................................... 59
VII.1 TRANSMIT ENGINE........................................................................................................................... 59
VII.2 UART ENGINE................................................................................................................................. 60
VIII. APPENDIX........................................................................................................................................ 62
VIII.1 AISO.............................................................................................................................................. 62
VIII.2 TRAMELBLAZE-TOP ....................................................................................................................... 63
VIII.3 UART............................................................................................................................................. 65
VIII.4 UART DECODE .............................................................................................................................. 67
VIII.5 TRANSMIT ENGINE.......................................................................................................................... 68
VIII.6 RECEIVE ENGINE ............................................................................................................................ 71
VIII.7 ADDRESS DECODE .......................................................................................................................... 75
VIII.8 POSITIVE EDGE DETECT.................................................................................................................. 76
VIII.9 RS FLOP.......................................................................................................................................... 77
VIII.10 SEVEN SEGMENT DISPLAY DRIVER............................................................................................... 78
VIII.11 ANODE SHIFT REGISTER ............................................................................................................... 79
VIII.12 ROTATOR...................................................................................................................................... 80
VIII.13 SELECT 2 BIT ................................................................................................................................ 81
VIII.14 MULTIPLEXOR 4 TO 1.................................................................................................................... 82
VIII.15 HEX DECODER.............................................................................................................................. 83
VIII.16 TRAMELBLAZE ............................................................................................................................. 95
VIII.17 MEMORY INTERFACE BLOCK...................................................................................................... 103
VIII.18 TOP LEVEL MODULE................................................................................................................... 107
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I. Introduction
The Chip Specification document explains the Universal Asynchronous Receiver Transmitter (UART)
data transmission module and Memory Interface Block (MIB) memory manager module as used in a terminal
communication project. The transmit engine and receive engine work together to communicate the SOPC with
the terminal. ASCII values are output to the terminal, and sent from the terminal to be interpreted by the
TramelBlaze. These engines combined form the UART engine. In addition, A Memory Interface Block gives
the TramelBlaze the ability to access Micron Memory from the Nexys A7.
I.1 Purpose
This project was essential in understanding how the Transmit and Receive engine of UART
data transmission worked. This meant input can be put into the terminal and data was output back
out and displayed on the terminal. In addition, this project was the first time a Memory
Interface Block was used to manage the memory addresses and data that communicated with
the Micron Memory. This document will go in depth about what each module within the project does.
This includes top level diagrams, a description, details on the I/O ports, logic tables, and
register map tables. A chip level test is then added at the end to indicate that the project
fulfilled all requirements.
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II. External Documents
II.1 TramelBlaze
II.1.1 Detailed Block Diagram
These documents explain the architecture, instruction set, and logic of the TramelBlaze and its interfaces. It
helped to create the design of the project and the Programmable Read-Only Memory (PROM) within the design.
The TramelBlaze is a 16-Bit PicoBlaze emulator. The PicoBlaze is an embedded 8-bit RISC microcontroller. The
PicoBlaze had similar logic, architecture, and instruction set to the TramelBlaze. The PicoBlaze documentation provided the
basis for our TramelBlaze programming and usage.
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II.1.2 Data Transmission:
Memory:
The TramelBlaze is able to run using 4 different types of memory.
1. 512 x 16 Scratch RAM - This is where interpreted data is stored
2. 128 x 16 Stack RAM - Holds temporary data storage that behaves as a FILO buffer
3. 4096 x 16 TB ROM - Instructions are stored in the TramelBlaze ROM
4. 16 x 16 Register Array
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II.1.3 TramelBlaze Instructions:
An essential part of learning to program
The TramelBlaze is understanding the
Instructions that can be performed on
The scratch RAM memory, and the registers.
These diagrams demonstrate
how to send and grab data from the
TramelBlaze. It also shows each operation
and how to perform them on the registers.
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II.1.4 Software Design
Trambler Directives
 Assembler directives are “instructions” added to the assembly language program that are intended to communicate with the
assembler – they are not instructions to be converted into machine language instructions
 ADDRESS – default address is 000. This directive changes where the instructions are placed in the range 000…FFF
 EQU – Equate a label with a constant value to be substituted prior to final assembly
 END – End of the source
Source Code Organization
 TramelBlaze code should be organized into six main portions:
 Declarations – define all constants and string substitutions
 Initialization – all setup required before enabling interrupts and entering main loop
 Main Loop – routine where the processor spends most of its time. Cycling is achieved by JUMP at the end
of the loop
 Service Routines – all of the routines needed to implement the functionality of the software (typically
executed with interrupt enables.
 Interrupt Service Routine (ISR) – routine invoked when interrupt occurs. Best to minimize time spent in
ISE with interrupts disabled.
 Vector to ISE found at FFE/FFF
Top Level Design
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II.2 Nexys A7
II.2.1 Hardware
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II.2.2 Input/Output
This figure shows the switch, LED,
Button, and Seven Segment Display
connections of the Nexys A7. This shows
the pin names and how to
connect them to the top module
through the constraint file
II.2.3 Nexys A7 UART Configuration
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III. Requirements
III.1 Interface Requirements
This project uses three components: the TramelBlaze, the UART Engine, and the Memory Interface Block.
These components are instantiated within the top module. The MIB takes characters from the Receive Engine of the UART,
and places them in Micron Memory. Once a special character is received, a certain value is transmitted to the terminal. For
example, ‘*’ causes hometown transmission. To accomplish this, the TramelBlaze takes the ASCII values stored in Micron
Memory and outputs the values to the terminal using the Transmit Engine. Before any input can be received by the Transmit
Engine however, a banner displaying ‘WELCOME CECS !’ is transmitted to the terminal.
Since UART Protocol is being used, Baud Rate is an essential part of data communication. All components
involved need to operate at the same bit transmitting/receiving frequency. The switches of the Nexys A7 control the Baud
Rate and UART Parity values.
Baud Switches Baud Rate Bit Time Nexys A7 Count
0000 300 0.0033333333 3333333
0001 1200 0.000833333 83333
0010 2400 0.000041667 41667
0011 4800 0.000208333 20833
0100 9600 0.000104167 10417
0101 19200 5.20833E-05 5208
0110 38400 2.60417E-05 2604
0111 57600 1.73611E-05 1736
1000 115200 8.68056E-06 868
1001 230400 4.34028E-06 434
1010 460800 2.17014E-06 217
1011 921600 1.08507E-06 109
This logic table describes how switches[3:1] are in charge of the number of bits and the parity bit. Switch[3] decides
whether the data is 8 or 7 bits. Switch[2] is in charge of if there is a parity bit. Switch[1] manages either even
or odd parity.
Switches[3:1] Data Size (Bits) Parity
000 7 None
001 7 None
010 7 Even
011 7 Odd
100 8 None
101 8 None
110 8 Even
111 8 Odd
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III.2 Physical Requirements
This table demonstrates how the switches are the input values for BAUD[3:0], eight, pen, ohel.
Eight: This input signal connects to switch[3] and indicates whether or not the data being
transmitted is 8 bits wide. ‘1’ for yes, ‘0’ for no.
PEN: This input signal connects to switch[2] and indicates whether or not the data has parity
enabled. ‘1’ for yes, ‘0’ for no.
OHEL: This input signal connects to switch[1] and indicates what kind of parity the data has.
‘1’ means odd parity, ‘0’ means even.
BTNU BTND BTNC BTNL BTNR
Reset N/A N/A N/A N/A
Only one button is used in this design to connect to the AISO block. When this button is pressed,
a global reset is sent to the AISO block. The output of the AISO block is then sent to all flops in the
design.
LEDS[7] LEDS[6] LEDS[5] LEDS[4] LEDS[3] LEDS[2] LEDS[1] LEDS[0]
The LEDs are used to walk a ‘1’ through them from LSB to MSB. The walking LED effect
demonstrates that the system is running.
Switches[7] Switches[6] Switches[5] Switches[4] Switches[3] Switches[2] Switches[1] Switches[0]
Baud[3] Baud[2] Baud[1] Baud[0] Eight PEN OHEL N/A
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IV. Top Level Design
IV.1 Description
The top level module connects all the modules together. This is done by instantiating the AISO ,
TramelBlaze Top, UART, Seven Segment Display, RS Flop, and two Address Decoders. The inputs/outputs are
connected to the FPGA.
IV.2 Top Level Diagram
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IV.3 Detailed Level Diagram
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IV.4 Data Flow Description
This project required that the user was able to interact with the terminal using the UART processor.
This project is important because it fully incorporated the UART design. The program
will display the banner “WELCOME CECS !” and then it will wait for the user input from the terminal. If the
terminal notices an input, it will check which character has been input. If it detects “*”, a hometown will be
printed. If it detects “@”, the terminal will print the amount of characters stored from previous inputs. If a
<backspace> is detected, a backspace occurs. Lastly if <cr> is detected, a new prompt is printed. In addition,
a ‘1’ is walked through the LEDs to indicate that the program is running. This project was also the first
time a Memory Interface Block was used to manage the memory addresses and data that communicated
with the Micron Memory. The TramelBlaze will be able to grab data from the terminal and place
those characters into a location in the memory
IV.5 Input/Output
Signal Size I/O Connection
clk 1 Input 100MHz Oscillator
reset 1 Input AISO
switches 7 Input Nexys A7 Switches[7:0]
TX 1 Output Nexys A7 Transmit USB
RX 1 Input Nexys A7 Receive USB
memoryAddress 23 Output Micron Memory
currentStatus 8 Output Micron Memory
cCE 1 Output Micron Memory
cWE 1 Output Micron Memory
cOE 1 Output Micron Memory
cADV 1 Output Micron Memory
CRE 1 Output Micron Memory
cUB 1 Output Micron Memory
cLB 1 Output Micron Memory
MIBInOut 16 Output Micron Memory
anode 8 Output Nexys A7 Anode
cathode 8 Output Nexys A7 Cathode
LEDs 8 Output Nexys A7 LED[7:0]
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IV.6 Pin Assignments
Input Signals Assignment Output Signals Assignment
clk E3 leds[0] H17
reset M18 leds [1] K15
rx C4 leds [2] J13
eight R15 leds[3] N14
pen M13 leds[4] R18
Ohel L16 leds[5] V17
baud[0] R17 leds[6] U17
baud[1] T18 leds[7] U16
baud[2] U18 tx D4
baud[3] R13
IV.7 Electrical Requirements
 Buttons
 3.3V equates to logic ‘1’
 0V equates to logic ‘0’
 Switches
 1.8 V equates to logic ‘1’
 0V equates to logic ‘0’
IV.8 Clock
The Nexys A7 clock is regulated by a 100MHz crystal oscillator. All flops in this design use the clock and update their
register values at rising clock edges.
IV.9 Resets
The Reset of the project is connected to Pin M18 of the Nexys A7 board. It is a button and every time that button is pressed,
the reset signal is sent to the AISO block which sends a synchronized reset signal to all flops in the design.
Source Code: Appendix VIII.18
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IV.10 Software
1 ; Paul Valenzuela
2 ; 018469189
3 ; CECS 460
4 ; This code transmits
5 ; '<CR><LF>WELCOME CECS !' banner then
6 ; prompt on reset and detect four chars
7 ; that choose to DISPLAY hometown (*)
8 ; amount of characters in line (@)
9 ; backspace (BACKSP)
10 ; new prompt (<CR>)
11 ; Also 8 onboard walking LEDS indicate that
12 ; the code is working correctly
13
14
15 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
16 ; Define and initialize global variables
17 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
18 ZERO EQU 0000
19 ONE EQU 0001
20 TWO EQU 0002
21 THREE EQU 0003
22 FOUR EQU 0004
23 FIVE EQU 0005
24 LEDDELAY EQU BA03
25 TOP EQU 0028
26 BACKSP EQU 0008
27 CARRET EQU 000D
28 PROMPTCHECK EQU 0010
29 BNCHK EQU 0014
30 HTCHK EQU 0020
31 ASTSYM EQU 002A
32 ATSYM EQU 0040
33
34 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
35 ; Define Registers
36 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
37 TEMP EQU R0 ; Temp to hold temporary data
38 POINTER EQU R1 ; Pointer to RAM
39 TXCHECK EQU R2 ; TX Check
40 VALUE EQU R3 ; Check if UART Ready
41 LEDCOUNT2 EQU R4 ; Counter for LED Delay
42 LEDS EQU R5 ; LEDs
43 COUNTER EQU R6 ; Counter
44 LEDCOUNT EQU R7 ; Counter for LED Delay
45 STATUS EQU R8 ; Status of RX and TX
46 ERROR EQU R9 ; Check possible errors
47 DIVISOR EQU RA ; Divisor for ASCII Convert
48 QUOTIENT EQU RB ; Quotient for ASCII Convert
49 TXSTATE EQU RC ; Transmit State
50 WORKS EQU RD ; Checks if value is valid
51 COUNT EQU RE ; Temporarily holds counter
52
53
54 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
55 ; Initialize variables and RAM
56 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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57 INIT
58 ENINT
59 LOAD POINTER, ZERO ; Pointer = 0
60 LOAD VALUE, ZERO ; Value = 0
61 LOAD LEDS, ONE ; LEDS = 0001
62 LOAD LEDCOUNT2, ZERO ; LEDcount2 = 0
63 LOAD LEDCOUNT, ZERO ; LEDcount = 0
64 LOAD TXSTATE, ZERO ; TXState = 0
65 LOAD STATUS, ZERO ; Status = 0
66 LOAD COUNTER, ZERO ; Counter = 0
67 CALL BANNER ; Insert Banner into Scratch RAM
68 CALL PROMPT ; Insert Prompt into Scratch RAM
69 CALL HOMETOWN ; Insert Hometown into Scratch RAM
70 CALL BACKSPACE ; Insert <bs> into Scratch RAM
71 CALL HEXCONVERT ; Initialize Binary to ASCII Converter
72
73
74 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
75 ; Main Routine that cycles through LED
76 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
77 MAIN
78 OUTPUT LEDS, ONE ; Output LED values to board
79 COMP LEDS, 0080 ; LEDS == 0080 ?
80 CALLZ RESETLEDS ; If true call reset LEDS
81 RL LEDS ; Shift LEDS left 1 bit
82 CALL LEDCOUNTER ; Call subroutine to slow LEDs
83 JUMP MAIN ; Super Loop Main
84
85 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
86 ; Resets LED value to "0000 0001"
87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
88 RESETLEDS
89 LOAD LEDS, ONE ; LEDS = 0001
90 RETURN
91
92
93 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
94 ; Counter that delays the walking '1' in LED value
95 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
96 LEDCOUNTER
97 ADD LEDCOUNT, ONE ; Increment counter1
98 NOP ; Wait
99 COMP LEDCOUNT, LEDDELAY ; Check once counter1 reaches 11
100 JUMPC LEDCOUNTER ; Loop until true
101 LOAD LEDCOUNT, ZERO ; Reset counter1
102 ADD LEDCOUNT2, ONE ; Increment counter2
103 COMP LEDCOUNT2, FOUR ; Check once counter2 reaches 4
104 JUMPNZ LEDCOUNTER ; Loop until true
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105 LOAD LEDCOUNT2, ZERO ; Reset counter2
106 RETURN
107
108 ; ISR ADDRESS
109 ADDRESS 0300
110
111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
112 ; Interrupt Service Routine
113 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
114 ISR
115 STORE POINTER, 0031 ; RAM[65] = Pointer
116 INPUT STATUS, ONE ; Read the Status Value
117
118 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
119 ; Checks if txReady is active
120 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
121 LOAD TEMP, STATUS ; Temp = status
122 COMP TXSTATE, FOUR ; TXState == 4 ?
123 JUMPZ RXCHECK ; If true, check if RX is ready
124 AND TEMP, TWO ; Temp = Temp & 0002
125 COMP TEMP, TWO ; TXReady ?
126 JUMPNZ FALSEINTERRUPT ; If False, Exit
127
128 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
129 ; Store temp value into SCRATCH RAM[POINTER]
130 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
131 STORERAM
132 STORE TEMP, POINTER ; RAM[Pointer] = Temp
133 ADD POINTER, ONE ; Pointer += 1
134 RETURN
135
136
137 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
138 ; Place initial banner in RAM[0] (<CARRET><LF>WELCOME CECS !) (16 Characters)
139 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
140 BANNER
141 LOAD TEMP, 000D ; Temp = <CARRET>
142 CALL STORERAM
143 LOAD TEMP, 000A ; Temp = <lf>
144 CALL STORERAM
145 LOAD TEMP, 0057 ; Temp = 'W'
146 CALL STORERAM
147 LOAD TEMP, 0045 ; Temp = 'E'
148 CALL STORERAM
149 LOAD TEMP, 004C ; Temp = 'L'
150 CALL STORERAM
151 LOAD TEMP, 0043 ; Temp = 'C'
152 CALL STORERAM
153 LOAD TEMP, 004F ; Temp = 'O'
154 CALL STORERAM
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155 LOAD TEMP, 004D ; Temp = 'M'
156 CALL STORERAM
158 CALL STORERAM
159 LOAD TEMP, 0020 ; Temp = ' '
160 CALL STORERAM
162 CALL STORERAM
164 CALL STORERAM
166 CALL STORERAM
167 LOAD TEMP, 0053 ; Temp = 'S'
168 CALL STORERAM
169 LOAD TEMP, 0020 ; Temp = ' '
170 CALL STORERAM
171 LOAD TEMP, 0021 ; Temp = '!'
172 CALL STORERAM
173 RETURN
174
175 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
176 ; Place prompt in RAM[16] (<CARRET><LF>--> )
177 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
178 PROMPT
179 LOAD TEMP, 000D ; Temp = <CARRET>
180 CALL STORERAM
181 LOAD TEMP, 000A ; Temp = <lf>
182 CALL STORERAM
183 LOAD TEMP, 002D ; Temp = '-'
184 CALL STORERAM
185 LOAD TEMP, 002D ; Temp = '-'
186 CALL STORERAM
187 LOAD TEMP, 003E ; Temp = '>'
188 CALL STORERAM
189 LOAD TEMP, 0020 ; Temp = ' '
190 CALL STORERAM
191 RETURN
192
193 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
194 ; Place 'La Quinta' (hometown) in RAM[22] (11 Characters)
195 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
196 HOMETOWN
197 LOAD TEMP, 004C ; Temp = 'L'
198 CALL STORERAM
199 LOAD TEMP, 0041 ; Temp = 'A'
200 CALL STORERAM
201 LOAD TEMP, 0020 ; Temp = ' '
202 CALL STORERAM
203 LOAD TEMP, 0051 ; Temp = 'Q'
204 CALL STORERAM
205 LOAD TEMP, 0055 ; Temp = 'U'
206 CALL STORERAM
207 LOAD TEMP, 0049 ; Temp = 'I'
208 CALL STORERAM
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Final Specification
209 LOAD TEMP, 004E ; Temp = 'N'
210 CALL STORERAM
211 LOAD TEMP, 0054 ; Temp = 'T'
212 CALL STORERAM
213 LOAD TEMP, 0041 ; Temp = 'A'
214 CALL STORERAM
215 LOAD TEMP, 0020 ; Temp = ' '
216 CALL STORERAM
217 RETURN
218
219
220 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
221 ; Place Backspace command in RAM[33] (<BACKSP> ' ' <BACKSP>)
222 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
223 BACKSPACE
224 LOAD TEMP, 0008 ; Temp = <BACKSP>
225 CALL STORERAM
226 LOAD TEMP, 0020 ; Temp = ' '
227 CALL STORERAM
228 LOAD TEMP, 0008 ; Temp = <BACKSP>
229 CALL STORERAM
230 RETURN
231
232 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
233 ; Checks if rxReady is active
234 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
235 RXCHECK
236 LOAD TEMP, STATUS ; Temp = Status
237 AND TEMP, ONE ; Temp = Temp & 0001
238 COMP TEMP, ONE ; Temp == 0001 ? (RXReady?)
239 JUMPNZ FALSEINTERRUPT ; If false, go to false ISR
240
241 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
242 ; Locates and outputs error
243 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
244 LOAD ERROR, STATUS ; Error = status
245 AND ERROR, 001C ; Check error status
246 SR0 ERROR ; Shift error right
247 SR0 ERROR ; Shift error right
248 OUTPUT ERROR, TWO ; Output new error
249
250 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
251 ; Read data and set it to temp
252 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
253 INPUT VALUE, ZERO ; Value = IN_PORT[0]
254 LOAD TEMP, VALUE ; Temp = Value
255
256 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
257 ; Check if <CARRET> was entered in the prompt
258 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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259 ENTERCHECK
260 COMP TEMP, CARRET ; Temp == <CARRET> ?
261 JUMPNZ BSCHECK ; If true, jump to enter subroutine
262 LOAD TXSTATE, THREE ; TXState = 3
263 LOAD POINTER, 0010 ; Pointer = 16
264 FETCH VALUE, POINTER ; Value = RAM[16]
267 JUMP TRANSMIT ; Transmit values
268
269 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
270 ; Check if <BS> was entered in the prompt
271 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
272 BSCHECK
273 COMP TEMP, BACKSP ; Temp == <BACKSP> ?
274 JUMPNZ ASTERICKS ; If true, jump to backspace subroutine
275 COMP COUNTER, ZERO ; Counter == 0 ?
276 JUMPZ FALSEINTERRUPT ; If true jump to false ISR
277 LOAD TXSTATE, FIVE ; TXState = 5
278 SUB COUNTER, ONE ; Counter -= 1
279 LOAD TXCHECK, 0023 ; TXCheck = 35
284 JUMP TRANSMIT
285
286 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
287 ; Check if '*' was entered in the prompt
288 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
289 ASTERICKS
290 COMP TEMP, ASTSYM ; Temp == '*' ?
291 JUMPNZ ATYSYMBOL ; If true, jump to display hometown
292 LOAD TXSTATE, TWO ; TXState = 2
297 JUMP TRANSMIT
298
299 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
300 ; Check if '@' was entered in the prompt
301 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
302 ATYSYMBOL
303 COMP TEMP, ATSYM ; Temp == '@' ?
304 JUMPNZ INCREMENT ; If true, check if counter maxed out
305 CALL HEXCONVERT ; Update Counter
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312 JUMP TRANSMIT
313
314 INCREMENT
315 COMP COUNTER, TOP ; Counter == Top ?
316 JUMPZ FALSEINTERRUPT ; If true, jump to false ISR
317 ADD COUNTER, ONE ; Counter += 1
318
319 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
320 ; Transmit data to terminal
321 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
322 TRANSMIT
323 OUTPUT VALUE, ZERO ; Transmit value
324 FETCH POINTER, 0031 ; Pointer = RAM[21]
325 RETEN
326
327
328 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
329 ; Output value to terminal
330 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
331 DISPLAY
332 FETCH POINTER, 0030 ; Pointer = 64
334 OUTPUT VALUE, ZERO ; Transmit Value
337 COMP POINTER, TXCHECK ; Pointer == TXCheck ?
338 JUMPZ PROMPTCHECK ; If true, check TXState
339 JUMP FALSEINTERRUPT ; Jump to false ISR
340
341
342 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
343 ; Displays hometown string in ASCII
344 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
345 PRINTH
346 COMP TXSTATE, FIVE ; TXState == 5 ?
347 JUMPZ DISPLAY ; If true, transmit values
348 COMP TXSTATE, TWO ; TXState == 2 ?
349 JUMPNZ PRINTPROMPT ; If false check if TXState == 3
352 JUMP DISPLAY ; Transmit Values
353
354 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
355 ; Displays banner
356 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
357 PRINTBANNER
358 COMP TXSTATE, ZERO ; TXState == 0 ?
359 JUMPNZ FALSEINTERRUPT ; If false, exit
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364 JUMP DISPLAY
365
366 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
367 ; Displays prompt
368 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
369 PRINTPROMPT
370 COMP TXSTATE, THREE ; TXState == 3 ?
371 JUMPNZ PRINTBANNER ; If false, check if TXState == 4
374 JUMP DISPLAY ; Transmit Values
375
376 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
377 ; Checks if TXCheck is 36 or 22
378 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
379 PROMPTCHECK
380 COMP TXCHECK, 0023 ; txCheck == 36?
381 JUMPZ TXSTATE4 ; If so, jump to TXSTATE4
382
383 COMP TXCHECK, 0016 ; txCheck == 22?
384 JUMPNZ PROMPTCHANGE ; If not, display prompt
385 LOAD COUNTER, ZERO ; Counter
386
387 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
388 ; Ensures TXState is 4
389 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
390 TXSTATE4
391 LOAD TXSTATE, FOUR ; txState = 4
393 RETEN
394
395 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
396 ; Changes Pointer Location
397 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
398 PROMPTCHANGE
400 STORE POINTER, 0030 ; RAM[64] = RAM[Pointer]
402 LOAD TXSTATE, THREE ; txState = 3
403 RETEN
404
405 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
406 ; Faulty interrupt caused by an error
407 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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408 FALSEINTERRUPT
410 RETEN
411
412
413 ADDRESS 0400
414
415
416
417
418 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
419 ; Converts binary value of counter to ASCII to output to terminal
420 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
421 HEXCONVERT
422 LOAD WORKS, ZERO ; Works = 0
424 LOAD DIVISOR, 2710 ; Divisor = 10,000
425 LOAD QUOTIENT, ZERO ; Quotient = 0
426 LOAD COUNT, COUNTER ; Count = Counter
427
428 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
429 ; Check if using the correct divisor value
430 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
431 CHECK
432 COMP COUNTER, DIVISOR ; Counter < Divisor ?
433 JUMPC CHANGEDIVISOR ; If true, jumpt to changedivisor subroutine
434 ADD QUOTIENT, ONE ; Quotient += 1
435 SUB COUNTER, DIVISOR ; Counter -= Divisor
436 JUMP CHECK ; Jump to check subroutine
437
438
439
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Makes sure quotient value is WORKS, then jumps to subroutine that changes divisor
440 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
441 CHANGEDIVISOR
442 COMP WORKS, ONE ; Works == 1 ?
443 JUMPZ QUOTASCII ; If true, jump to quotient to ascii conversion
444 COMP QUOTIENT, ZERO
445 JUMPZ SETSPACE ; If true, jump to add a hexi space subroutine
446 LOAD WORKS, ONE ; Works = 1
447
448
449
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Convert quotient value to ASCII
450
451
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
QUOTASCII
452 ADD QUOTIENT, 0030 ; Change quotient to ascii
453 JUMP DIVIDE
454
455 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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456 ; Adds a space between banner and <count> value
457 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
458 SETSPACE
459 ADD QUOTIENT, 0020 ; Make quotient a ' '
460
461 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
462 ; Algorithm that divides binary value by 10,000, 1,000, 100, then 10 to convert it to
463 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
464 DIVIDE
465 STORE QUOTIENT, POINTER ; RAM[POINTER] = Quotient
466 LOAD QUOTIENT, ZERO ; Quotient = 0
468 COMP DIVISOR, 000A ; Divisor == 10 ?
469 JUMPZ LASTVALUE ; If true, jump to lastvalue subroutine
470 COMP DIVISOR, 0064 ; Divisor == 100 ?
471 JUMPZ TEN ; If true, jump to ten subroutine
472 COMP DIVISOR, 03E8 ; Divisor == 1,000 ?
473 JUMPZ HUNDRED ; If true, jump to hundred subroutine
474 JUMP THOUSAND ; Else, jump to thousand subroutine
475
476 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
477 ; Stores the 1's place of the counter into SCRATCH RAM
478 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
479 LASTVALUE
480 ADD QUOTIENT, COUNTER ; Quotient += counter
481 ADD QUOTIENT, 0030 ; Convert quotient to ASCII
482 STORE QUOTIENT, POINTER ; RAM[POINTER] = quotient
484 LOAD COUNTER, COUNT ; Counter = count
485 RETURN
486
487 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
488 ; Subrountine to change divisor to 1000
489 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
490 THOUSAND
491 LOAD DIVISOR, 03E8 ; Divisor = 1,000
492 JUMP CHECK
493
494 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
496 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
497 HUNDRED
498 LOAD DIVISOR, 0064 ; Divisor = 100
499 JUMP CHECK
500
501 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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503 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
504 TEN
505 LOAD DIVISOR, 000A ; Divisor = 10
506 JUMP CHECK 507
508 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
509 ; Vector to Interrupt Service Routine - NO CHANGES HERE
510 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
511 ADDRESS 0FFE ; Interrupt At Vector Address 0FFE
512 ENDIT
513 JUMP ISR ; Jump to ISR
514 END
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V. External Developed Blocks
V.1 Asynchronous In, Synchronous Out (AISO)
V.1.1 Description V.1.2 Top Level Diagram
This block prevents metastability by creating
a synchronized reset signal. The reset input
of this block is connected to a button on the
Nexys A7 board. The output resets every signal.
V.1.3 Input/Output
Signal I/O Connected to
clk Input 100MHz Crystal Oscillator
reset Input Button
sRst Output mRst
V.1.4 Register Map
Register Usage Description
{d2,q2} Synchronize Once resets, sends a single pulse to all modules
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V.2 TramelBlaze
V.2.1 Description V.2.2 Top Level Diagram
The TramelBlaze is 16-bit soft-core
microcontroller that emulates the PicoBlaze.
The TramelBlaze reads and performs actions
based on instructions provided by the ROM.
The TramelBlaze is used in this project to
receive and transmit ASCII values to a Serial
terminal. The WRITE_STROBE and
READ_STROBE communicate with the
UART which helps to establish whether
the design will be using the transmit
or receive engine.
V.2.3 Input/Output
Signal I/O Connection
CLK Input 100MHz Crystal Oscillator
RESET Input AISO
INTERRUPT Input RS Flop
IN_PORT[15:0] Input UART
PORT_ID[15:0] Output UART + AddressDecoder
OUT_PORT[15:0] Output UART
READ_STROBE Output UART
WRITE_STROBE Output UART
INTERRUPT_ACK Output RS Flop
V.2.4 Register Map
TB_ROM[15:0] Read Only Memory Holds Instructions for TramelBlaze to execute
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VI. Internally Developed Blocks
VI.1 Memory Block Interface
VI.1.1 Description
The Memory Interface Block consists of a state machine and control flops. The state machine
inputs are the PORT_ID values. There are three possible states: MEMWRITE, MEMREAD, IDLE. The
outputs of each state are CE, WE, OE, and T. The flops of the MIB then use these signals to control the
memory addresses and the data being communicated between them and the Micron Memory. Prior to this,
the TramelBlaze Read Only Memory had been in charge of this data flow.
VI.1.2 Top Level Diagram
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VI.1.3 Input/Output
Signal Size (Bits) Input/Output Connection
clk 1 Input 100MHz Crystal Oscillator
rst 1 Input AISO
READ 1 Input TramelBlaze
WRITE 1 Input TramelBlaze
PORT_ID 16 Input TramelBlaze
memoryDataIn 16 Input Micron Memory
OUT_PORT 16 Input TramelBlaze
cCE 1 Output Micron Memory
cWE 1 Output Micron Memory
cOE 1 Output Micron Memory
cADV 1 Output Micron Memory
cCRE 1 Output Micron Memory
cUB 1 Output Micron Memory
cLB 1 Output Micron Memory
memoryAddress 23 Output Micron Memory
memoryDataOut 16 Output Micron Memory
IN_PORT 16 Output TramelBlaze
VI.1.4 Register Map
Register Module Description
cCE MIB Chip Enable Signal to Micron Memory
cWE MIB Write Enable Signal to Micron Memory
cOE MIB Output Enable Signal to Micron Memory
cIOBUF_T MIB Controller for IOBUF
cADV MIB Address Valid Signal for Micron Memory
CRE MIB Control Register Enable Signal for Micron Memory
cUB MIB Upper Byte Signal for Micron Memory
cLB MIB Lower Byte Signal for Micron Memory
memoryAddress MIB Memory Address Location
memoryDataOut MIB Data to Micron Memory
IN_PORT MIB Data from TramelBlaze
state MIB State of MIB
nState MIB Next State of MIB
WCLK MIB Counter to Stay in Write State for 130ns
RCLK MIB Counter to Stay in Read State for 130ns
nCE MIB Chip Enable Next State
nWE MIB Write Enable Next State
nOE MIB Output Enable Next State
nIOBUF_T MIB T Next State
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VI.1.5 State Machine
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VI.2 Universal Asynchronous Receiver and Transmitter (UART)
VI.2.1 Description
The UART module is built by five components: the Transmit Engine, the Receive Engine, the
Baud Rate Decoder, and two Positive Edge Detectors. The Transmit Engine shifts serial data out to the
Transmit Line through the micro-USB connection. The Receive Engine shifts serial data into a register. It
then takes the data in the register and sends it to the TramelBlaze to be processed. A UART module
communicates data between modules without a clock to synchronize data transmission. In order to make
sure the data is valid, a common frequency is required. This is accomplished by both engines sharing the
Baud Rate. The Baud Rate is determined by decoding the switch values from the Nexys A7 board. Baud
Rate represents the speed that data is transmitted and received.
The UART block communicated to the TramelBlaze when the receive engine/transmit engine us
ready to interpret data. This signal is communicated by an interrupt signal. The Interrupt reaches the
TramelBlaze and causes it to enter the Interrupt Service Routine. This signal sent from the UART is
called UARTready.
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VI.2.3 Detailed Level Diagram
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VI.2.4 Input/Output
Signal Size(Bits) I/O Connection
rst 1 Input AISO
rx 1 Input Nexys A7 USB
switches 8 Input Nexys A7 Switches
WRITE 8 Input Address Decoder
READ 8 Input Address Decoder
UARTready 1 Output TramelBlaze
tx 1 Output Nexys A7 USB
UART_DS 8 Output TramelBlaze
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VI.3 Transmit Engine
VI.3.1 Description
The Transmit Engine consists of five components: Bit Counter, Bit Time Counter, Shift Register,
Bit 10/9 Decoder, and the Transmit Controller. These components combine to help transmit data to the
computer terminal. The Bit Time Counter will decide the speed at which the transmit engine will shift
data out. The speed is set by the output of the Baud Rate Decoder. The Bit Counter makes sure the
register only shifts out 11 bits of data. The Shift Register helps to shift data outwards from the least
significant bit (LSB) to most significant bit (MSB). The Transmit Controller is in charge of setting the
values of the wires between the components. These wires tell the counters when to reset, and are in charge
of other circumstances such as parity enable, and the UART Interrupt. Lastly, the Bit 10/9 Decoder
decides what values to insert into bit 9 and bit 10 of the shift register. These values depend on how many
bits wide the signal to transmit is. All of these components are essential to build the Transmit Engine.
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VI.3.4 Verification
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VI.3.5 Input / Output
Signal Size (Bits) I/O Connection
rst 1 Input AISO
load 1 Input Address Decoder
eight 1 Input Nexys A7 Switch[3]
pen 1 Input Nexys A7 Switch[2]
ohel 1 Input Nexys A7 Switch[1]
k 19 Input Baud Rate Decoder
txReady 1 Output Nexys A7 USB
VI.3.6 Register Map
bit10 Decoder Bit 10 into the Shift Register
bit9 Decoder Bit 9 into the Shift Register
doit Transmit Controller Allows counter to increment
load1 Transmit Controller Delays data transmission by 1 clock period
nTX [10:0] Shift Register Holds data to be shifted out into board
lData [7:0] Shift Register Grabs data from TramelBlaze
bitTimeCount [18:0] Bit Time Counter Baud Rate Counter
bitCount [3:0] Bit Counter How many bits to shift Counter
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VI.4 Transmit Shift Register
VI.4.1 Description
The shift register is sent data from OUT_PORT on the TramelBlaze and shifts data outwards 1 bit
at a time in the output value tx. The tx usually has a value of ‘1’. The ‘start bit’ for the transmit engine is a
‘0’. So when a ‘0’ is initially sent, the tx will start outputting the register data 1 bit at a time. When the
module is reset, the shift register will continue to output 11 bits of ‘1’, to show its inactive state. The data
is sent out from LSB to MSB. With the first bit always being a ‘0’. The bit after the MSB will either be
the parity bit or the stop bit. But data transmission always ends with a ‘1’ stop bit. When the bit time
counter is done counting, a ‘1’ is sent to the TX engine and the UART interprets this as the end of the
data transmission.
VI.4.3 Input/Output
Rst 1 Input AISO
load 1 Input TX Controller
btu 1 Input TX Bit Time Counter
nTX 11 Input Bit10/9 Decoder, TX Controller
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VI.5 Bit 10 Bit 9 Decoder
VI.5.1 Description
This module oversaw deciding what values bit10 and bit9 receive. This is because these
bits depend entirely on the number of bits being transmitted and the parity of the transmission.
The data will either be 7 or 8 bits. This directly effects what bit9 will be. Also, if there is a parity,
the parity bit will be placed in bit9 or bit10, depending on how many bits the data is. All of these
conditions are evaluated and assigned based on the decoder. The inputs of the decoder are eight,
pen, and ohel.
VI.5.3 Input/Output
lData 8 Input TX Controller
bit10 1 Output TX Shift Register
bit9 1 Output TX Shift Register
VI.5.4 Logic Table
eight pen ohel bit10 bit9
0 0 0 1 1
0 0 1 1 1
0 1 0 1 ^lData[6:0]
0 1 1 1 ~^lData[6:0]
0 0 0 1 lData[7]
1 0 1 1 lData[7]
1 1 0 ^lData[7:0] lData[7]
1 1 1 ~^lData[7:0] lData[7]
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VI.6 Transmit Controller
VI.6.1 Description VI.6.2 Top Level Diagram
The transmit controller is in
charge of the wires between the flops
and indicative signals. This includes
doit, done, btu, etc. It communicates
between the flops and tells them how
to behave. It is also in charge of telling
the shift register when to load new
data with the load1 signal.
VI.5.3 Input/Output
clk 1 Input 100MHz Clock Oscillator
rst 1 Input AISO
done 1 Input TX Bit Count
load 1 Input Address Decoder
txReady 1 Output PED
load1 1 Output TX Shift Register
doit 1 Output Both TX Counters
lData 8 Output TX Shift Register
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VI.7 Transmit Bit Counter
This counter counts from 0-11 in decimal.
Each increment is to indicate how many
bits have been transmitted. It increments
every time the “doit” and “btu” signals
are high. This means that the bit time counter
has reached its value. This is important
because a bit is only sent every time the
bit time counter has reached its comparable value.
VI.7.3 Input/Output
rst 1 Input AISO
doit 1 Input TX Controller
btu 1 Input TX Bit Time Counter
done 1 Output TX Controller
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VI.8 Transmit Bit Time Counter
The bit time counter is used to
transmit bits at a very specific baud
rate. The bit time counter increments
at every clock signal and will continue
to increment until it reaches its indicated
baud rate. The bit time counter resets when
the “done” signal is high. This means that
the baud rate has been reached and a bit
is ready to transmit.
VI.8.3 Input/Output
clk 1 Input 100 MHz Clock Oscillator
rst 1 Input AISO
doit 1 Input TX Controller
btu 1 Output TX Shift Register
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VI.9 Receive Engine
VI.9.1 Description
The Receive engine works in the opposite direction of the transmit engine. It inputs data 1 bit at a
time and shifts them into a shift register. It then interprets this data and sends it to the TramelBlaze via
IN_PORT. The receive engine consists of 5 components: a Bit Time Counter, a Bit Counter, a State
Machine, Receive Controller, and the Receive Shift Register. All these components combine to allow the
UART to receive data 1 bit at a time and interpret it into a valid ASCII value. It is important that the
shifted data is shifted at the correct baud rate for the appropriate amount of times. The shift register grabs
data from the rx input and shifts it into a register. However, the number of bits of data and parity bit need
to be taken into consideration. Due to this, the data needs to be remapped accordingly.
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VI.9.4 Verification
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VI.9.5 Input/Output
clk 1 Input 100 MHz Crystal Oscillator
rst 1 Input AISO
READ 8 Input Address Decoder
rxStatus 8 Output TramelBlaze
rxReady 1 Output UART PED
UART_RDATA 8 Output TramelBlaze
VI.9.6 Register Map
start State Machine Detection of start bit
nStart State Machine Holds next start value
done State Machine Resets counter values
doit State Machine Allows counter to count
nDoit State Machine Holds the next doit value
Parity_error Receive Controller Indicates a parity error
Framing_error Receive Controller Indicates a framing error
Overflow_error Receive Controller Indicates an overflow error
State State Machine State that holds done + start values
nState State Machine Registers the next State
nRX Shift Register Register holding raw data from Nexys Board
shiftedReg Right Justify Register Register with proper parity bit
BitTimeCount Bit Time Counter Baud Rate Counter
BitCount Bit Counter How many times register shift counter
newK Baud Rate Divider Baud Rate Decoder
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VI.10 Receive Shift Register
The shift register is a shift register that operates
under specific conditions. The 2 MSBs will either
be 0s or the data interpreted from the rx line,
depending on the values of eight and pen.
This module uses a switch case statement to assess
the values of eight and pen. If both values are high,
the data is not shifted. If only one of the values is high,
the data is shifted once to the right. If both are inactive,
the data is shifted twice to the right.
VI.10.3 Input/Output
rst 1 Input AISO
shiftHigh 1 Input RX Controller
shiftedReg 10 Output RX Controller
UART_RDATA 8 Output TramelBlaze
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VI.11 Receive State Machine
The state machine is implemented using
a Modified Moore technique. The state machine
guarantees that the start bit remains low-active
until it is mid-bit time. At this point, data collection
will continue at normal bit time until all the
data is received. This state machine outputs start
and doit. Start means that the engine has just
received the start bit. Doit means that the engine
is receiving actual data. The state machine
conditions are rx, done, and btu.
VI.11.3 State Transition Diagram
clk 1 Input 100 MHz Crystal Oscillator
rst 1 Input AISO
btu 1 Input RX Bit Time Counter
done 1 Input RX Bit Counter
start 1 Output RX Bit Time Counter
doit 1 Output Both RX Counters
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VI.12 Receive Controller
The receive controller is in charge of
the wires between the flops and indicative signals.
This includes doit, done, btu, etc. It communicates
between the flops and tells them how to behave.
It in charge of when to divide the baud value
by 2, and communicating the status of the
receive engine. An example being when
there is an overflow/parity/framing error.
rst 1 Input AISO
done 1 Input RX Bit Counter
shiftedReg 10 Input Receive Shift Register
rxReady 1 Output TramelBlaze
parity_error 1 Output UART
framing_error 1 Output UART
overflow_error 1 Output UART
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VI.13 Receive Bit Counter
This counter counts from 0-11 in decimal.
Each increment is to indicate how many bits
have been received. It increments every time
the “doit” and “btu” signals are high. This means
that the bit time counter has reached its value.
This is important because a bit is only grabbed every
time the bit time counter has reached its comparable
value. In addition, the Receive Bit Counter has to
constantly change the comparable value depending
on how many bits are received. This
depends on the values of pen and eight.
rst 1 Input AISO
doit 1 Input State Machine
btu 1 Input RX Bit Time Counter
done 1 Output State Machine
VI.13.4 Logic Table
eight pen == ?
0 0 9
0 1 10
1 0 11
1 1 11
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VI.14 Receive Bit Time Counter
The bit time counter is used to receive bits
at a very specific baud rate. The bit
time counter increments at every clock
signal and will continue to increment until
it reaches its indicated baud rate. The bit time
counter resets when the “done” signal is high.
This means that the baud rate has been
reached and a bit is ready to be received. The
only difference is that this bit time counter
counts to a value of k/2, where k is the
interpreted baud rate.
clk 1 Input 100 MHz Clock Oscillator
rst 1 Input AISO
doit 1 Input State Machine
start 1 Input State Machine
btu 1 Output RX Controller
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VI.15 Baud Rate Decoder
The Baud Rate Decoder is a 4 to 19-bit
Decoder that chooses the speed that the UART
communicates data. The 4 inputs of the decoder come
from switches[7:4] on the Nexys A7 board.
switches 4 Input Nexys A7 Switches[7:4]
k 19 Output Transmit + Receive Engine
VI.15.4 Register Map
k[18:0] Constant The rate that data is sent/received
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VI.16 Positive Edge Detect
This block detects a rising edge on
A given signal. It is used in the UART block to
detect when txReady and rxReady reach a
rising edge.
rst 1 Input AISO
in 1 Input Transmit + Receive Engine
yes 1 Output UART
q[1:0] PED Sends PED values when flop goes from {1,0} to {0,1}
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VI.17 RS Flop
The RS Flop behaves as a typical
RS flop. It holds a value until each rising
clock signal. If input s is high, the flop
outputs 1. The flop will then hold this value
until the flop reset or functional reset are high.
rst 1 Input AISO
funcrst 1 Input TramelBlaze
set 1 Input Transmit PED + Receive PED
q 1 Output TramelBlaze
q Interrupt Output interrupt when set high
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VI.18 Address Decode (READ)
This module determines the values
of READ[7:0] based on READ_STROBE
and PORT_ID[15:0]. It helps the UART
understand which values to send to the
TramelBlaze.
READ_STROBE 1 Input TramelBlaze
PORT_ID[15] 1 Input TramelBlaze
READS 8 Output Receive Engine
VI.9.1 Register Map
enable {READ_STROBE &
PORT_ID[15]}
Determines whether to write to TramelBlaze
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VI.19 Address Decode (WRITE)
This module determines the values
of WRITE[7:0] based on WRITE_STROBE
and PORT_ID[15:0]. It helps the UART
understand which values to grab from the
TramelBlaze.
WRITE_STROBE 1 Input TramelBlaze
WRITE 8 Output Transmit Engine
VI.9.4 Register Map
enable {WRITE_STROBE &
PORT_ID[15]}
Determines whether to read from TramelBlaze
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VII. Chip Level Verification
VII.1 Transmit Engine
As demonstrated by the screenshot above, the transmit engine works appropriately by transmitting a
banner to the terminal and incrementing the counter every time the banner is printed
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VII.2 UART Engine
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Input
The following keyboard inputs were entered into the terminal:
1. *
2. 12345<cr>
3. 12345@
4. 01234567@
5. <cr>
6. Paull
7. <bs>
8. <cr>
9. The Backspace Works…
Requirements
This demonstrates that the UART engine works as expected. It is able to receive data from the terminal,
interpret that data, and transmit new data to the terminal. In this specific design,
 “*” - Prints hometown
 <cr> - Creates newline
 “@” - Counts the amount of characters entered
 <bs> - Deletes the previous character
Verified
As shown above, all of the inputs gave the expected outputs. This means that the UART design satisfied
its requirements.
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VIII.Appendix
VIII.1 AISO
1 `timescale 1ns / 1ps
2 //******************************************************************************//
3 // File name: AISO.v //
4 // //
5 // Created by Paul Valenzuela on 9/16/19. //
6 // Copyright (C) 2018 Paul Valenzuela. All rights reserved. //
7 // //
8 // //
9 // In submitting this file for class work at CSULB //
10 // I am confirming that this is my work and the work //
11 // of no one else. In submitting this code I acknowledge that //
12 // plagiarism in student project work is subject to dismissal //
13 // from the class //
14 //******************************************************************************//
15 //******************************************************************************//
16 // AISO.v //
17 // //
18 // The AISO block ensures that all the blocks within the design share a //
19 // synchronous reset input. The AISO block works by converting the input //
20 // of reset into two flops. This makes sure that reset is stable and //
21 // helps prevent metastability //
22 // //
23 // @input clk, rst, //
24 // @output sRst //
25 // //
26 //******************************************************************************//
27 module AISO(clk, rst, sRst);
28 //Declare Variables
29 input wire clk,rst;
30 output wire sRst;
31 reg d2, q2;
32
33 //Sequential Block
34 always@(posedge clk,posedge rst)
35 //If Rst is on, both flops input 0
36 if(rst)
37 d2 <= 1'b0;
38 //Otherwise, the first flop gets 1 and the second gets the output of the first
flop
39 else
40 {d2,q2} <= {1'b1,d2};
41
42 //Output wire is assigned to the inverted output of the second flop
43 assign sRst = ~q2;
44
45 endmodule
46
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VIII.2 TramelBlaze Top
1 //****************************************************************//
2 // This document contains information proprietary to the //
3 // CSULB student that created the file - any reuse without //
4 // adequate approval and documentation is prohibited //
5 // //
6 // Class: CECS 460 //
7 // Project name: TRAMBLAZE PROCESSOR //
8 // File name: tramelblaze_top3.0_sim.v //
9 // Release: 3.0 Release Date 02mar2017 //
10 // Release: 5.0 Release Date 07nov2017 //
11 // to be used for simulation only //
12 // assumes following hierarchy //
13 // project //
14 // assembler//
15 // design (file in design looks in assembler for instr) //
16 // //
17 // Created by John Tramel on 20Feburary2016 //
18 // Copyright 2016 John Tramel. All rights reserved. //
19 // //
20 // Abstract: Top level for TRAMBLAZE processor //
21 // Edit history: 2016JAN25 - created //
22 // 20FEB - top created for processor and memory //
23 // tramelblaze_top //
24 // - tramelblaze //
25 // - tramelblaze_mem //
26 // 14feb2020 - modified path for sim.sim for Vivado //
27 // assumes Assembler directory same level as project //
28 // Top Level Directory //
29 // Assembler //
30 // code.tba, code.lst, sim.sim //
31 // Project //
32 // vivado project file //
33 // 18apr202 - startup error with memory - 1st instruction //
34 // not executed properly. Believe I fixed it //
35 // //
38 // of no one else. //
39 // //
40 // In the event other code sources are utilized I will //
41 // document which portion of code and who is the author //
42 // //
43 // In submitting this code I acknowledge that plagiarism //
44 // in student project work is subject to dismissal from the class //
45 //****************************************************************//
46
47 `timescale 1ns/1ns
48
49 module tramelblaze_top (CLK, RESET, IN_PORT, INTERRUPT,
50 OUT_PORT, PORT_ID, READ_STROBE, WRITE_STROBE, INTERRUPT_ACK);
51
52 input CLK;
53 input RESET;
54 input [15:0] IN_PORT;
55 input INTERRUPT;
56
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57 output [15:0] OUT_PORT;
58 output [15:0] PORT_ID;
59 output READ_STROBE;
60 output WRITE_STROBE;
61 output INTERRUPT_ACK;
62
63 wire [15:0] INSTRUCTION;
64 wire [11:0] ADDRESS;
65
66 tramelblaze tramelblaze
67 (
68 .CLK(CLK),
69 .RESET(RESET),
70 .IN_PORT(IN_PORT),
71 .INTERRUPT(INTERRUPT),
72
73 .OUT_PORT(OUT_PORT),
74 .PORT_ID(PORT_ID),
75 .READ_STROBE(READ_STROBE),
76 .WRITE_STROBE(WRITE_STROBE),
77 .INTERRUPT_ACK(INTERRUPT_ACK),
78
79 .ADDRESS(ADDRESS),
80 .INSTRUCTION(INSTRUCTION)
81 );
82
83
84 reg [15:0] memory [0:4095];
85 reg [15:0] ADDRESSQ;
86 /*
87 initial
88 $readmemh("/assembler/sim.sim",memory);
89
90 always@(*) INSTRUCTION = memory[ADDRESSQ];
91
92 always @(posedge CLK,posedge RESET)
93 if (RESET) ADDRESSQ <= 12'b0;
94 else ADDRESSQ <= ADDRESS; 95 */
96
97
98 tb_rom tb_rom
99 (
100 .clk (CLK), // input clka
101 .a (ADDRESS), // input [11 : 0] addra
102 .spo (INSTRUCTION) // output [15 : 0] douta
103 );
104
105 endmodule
106
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VIII.3 UART
2 //******************************************************************************//
3 // File name: UART.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // UART.v //
17 // //
18 // This module serves as the Universal Asynchronous //
19 // Receiver Transmitter block. It does this by holding an instantiation //
20 // of the transmit block and UART decoder. //
21 // //
22 // @input clk, rst, [7:0] READS, [7:0] WRITE, OUT_PORT[7:0], switches, rx //
23 // @output txReady, tx,
UART_DS //
24 // //
25 //******************************************************************************//
26 module UART(clk,rst,WRITE,READS,OUT_PORT,UARTready,tx,rx,switches,UART_DS);
27
28 input clk, rst, rx;
29 input [7:0] OUT_PORT, WRITE, READS;
30 output wire UARTready, tx;
31 output reg [7:0]UART_DS;
32 wire [7:0] UART_RDATA;
33 input [7:0] switches;
34
35 wire [18:0] k;
36 wire txReady, rxReady, txReadyYes, rxReadyYes;
37 wire [7:0] UART_STATUS;
38 wire [7:0] rxStatus;
39 reg [7:0] BAUD_VAL;
40
41
42 // Transmit
43 transmit transmit_engine(.clk(clk), .rst(rst),
44 .load(WRITE[0]), .k(k[18:0]),
45 .eight(switches[3]), .pen(switches[2]),
46 .ohel(switches[1]), .OUT_PORT(OUT_PORT[7:0]),
47 .txReady(txReady), .tx(tx));
48
49
50 // Recieve
51 recieve recieve_engine(.clk(clk), .rst(rst),
52 .eight(switches[3]),.pen(switches[2]),.ohel(switches[1]),
53 .READ(READS[7:0]),.k(k[18:0]),
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54 .rxReady(rxReady),.rx(rx),
55 .UART_RDATA(UART_RDATA[7:0]),
56 .rxStatus(rxStatus[7:0]));
57
58 // Assign K Value based on decoder
59 uart_decode decoder(.switches(switches[7:4]),.k(k[18:0]));
60
61 // PED txReady
62 posEdgeDetect txr(.clk(clk), .rst(rst), .in(txReady), .yes(txReadyYes));
63
64 // PED rxReady
65 posEdgeDetect rxr(.clk(clk), .rst(rst), .in(rxReady), .yes(rxReadyYes));
66
67 // UART Ready
68 assign UARTready = (txReadyYes || rxReadyYes);
69
70 // UART Status
71 assign UARTStatus = {rxStatus[7:2], txReady, rxStatus[0]};
72
73 // Decide which values to write to Tramelblaze
74 always@(*)
75 if(READS[0])
76 UART_DS = UART_RDATA;
77 else if(READS[1])
78 UART_DS = UART_STATUS;
79 else
80 UART_DS = 8'b0;
81
82 endmodule
83
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VIII.4 UART Decode
2 //******************************************************************************//
3 // File name: uart_decode.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // uart_decode.v //
17 // //
18 // The uart_decode module decodes values from switches to determine //
19 // baud rate //
20 // //
21 // @input [3:0] switches //
22 // @output [18:0] k //
23 // //
24 //******************************************************************************//
25 module uart_decode(switches,k);
26
27 input [ 3:0] switches; // Switches [7:4]:
28 output reg [18:0] k; // output as seen in transmit engine diagram
29
30 always @(*) begin
31 case (switches)
32 4'b0000: k = 19'd333333; //300 -- RATE
33 4'b0001: k = 19'd83333; //1200
34 4'b0010: k = 19'd41667; //2400
35 4'b0011: k = 19'd20833; //4800
36 4'b0100: k = 19'd10417; //9600
37 4'b0101: k = 19'd5208; //19200
38 4'b0110: k = 19'd2604; //38400
39 4'b0111: k = 19'd1736; //57600
40 4'b1000: k = 19'd868; //115200
41 4'b1001: k = 19'd434; //230400
42 4'b1010: k = 19'd217; //460800
43 4'b1011: k = 19'd109; //921600
44 default: k = 19'd333333; //300
45 endcase
46 end
47 endmodule
48
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VIII.5 Transmit Engine
2 //******************************************************************************//
3 // File name: transmit.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // transmit.v //
17 // //
18 // The transmit module serves as the top level for the trasnmit block. //
19 // It consists of several components and will later be used in the UART //
20 // block //
21 // //
22 // @input clk, rst, load, eight, pen, ohel, [7:0] OUT_PORT, [19:0] k //
23 // @output txReady, tx //
24 // //
25 //******************************************************************************//
26 module transmit(clk, rst, load, k, eight, pen, ohel, OUT_PORT, txReady, tx);
27 input clk, rst, load, eight, pen, ohel;
28 input [7:0] OUT_PORT;
29 input [18:0] k;
30
31 output reg txReady;
32 output wire tx;
33
34 wire btu, done;
35 reg bit10, bit9, doit, load1;
36 reg [10:0] nTX;
37 reg [7:0] lData;
38 reg [18:0] bitTimeCount;
39 reg [3:0] bitCount;
40
41
42 // Bit Counter
43 always@(posedge clk, posedge rst)
44 if (rst)
45 bitCount <= 4'b0;
46 else if(done)
48 else if({doit,btu} == 2'b11)
49 bitCount <= bitCount + 4'b1;
50 else
51 bitCount <= bitCount;
52
53 assign done = (bitCount == 4'b1011);
54
55
56 // DOIT Signal
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58 if (rst)
59 doit <= 1'b0;
60 else if(done)
61 doit <= 1'b0;
62 else if(load1)
63 doit <= 1'b1;
64 else
65 doit <= doit;
66
67 // Bit Time Counter
69 if (rst)
70 bitTimeCount <= 19'b0;
71 else if(btu)
73 else if(doit)
74 bitTimeCount <= bitTimeCount + 19'b1;
75 else
76 bitTimeCount <= bitTimeCount;
77
78 assign btu = (bitTimeCount == k) ? 1'b1 : 1'b0;
79
80
81 // LOAD1 Signal
83 if (rst)
84 load1 <= 1'b0;
85 else
86 load1 <= load;
87
88 // Loadable 8-Bit Register
90 if (rst)
91 lData <= 8'b0;
92 else if(load)
93 lData <= OUT_PORT[7:0];
94 else
95 lData <= lData;
96
97 // Decoder
98 always@(*)
99 case({eight,pen,ohel})
100 3'b000: {bit10,bit9} = 2'b11;
101 3'b001: {bit10,bit9} = 2'b11;
102 3'b010: {bit10,bit9} = {1'b1,(^lData[6:0])};
103 3'b011: {bit10,bit9} = {1'b1,(~(^lData[6:0]))};
104 3'b100: {bit10,bit9} = {1'b1,lData[7]};
105 3'b101: {bit10,bit9} = {1'b1,lData[7]};
106 3'b110: {bit10,bit9} = {(^lData[7:0]),lData[7]};
107 3'b111: {bit10,bit9} = {(~(^lData[7:0])),lData[7]};
108 default: {bit10,bit9} = 2'b0;
109 endcase
110
111
112 // Shift Register
113 always @(posedge clk, posedge rst)
114 begin
115 if(rst)
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116 nTX <= 11'b11111111111;
117 else if(btu)
118 nTX <= {1'b1, nTX[10:1]};
119 else if(load1)
120 nTX <= {bit10,bit9,lData[6:0],2'b01};
121 else
122 nTX <= nTX;
123 end
124
125 // Transmit tx signal
126 assign tx = (nTX[0]);
127
128 // TXREADY Signal
130 if (rst)
131 txReady <= 1'b1;
132 else if (load)
134 else if (done)
136 else
137 txReady <= txReady;
138
139 endmodule
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VIII.6 Receive Engine
2 //******************************************************************************//
3 // File name: recieve.v //
4 // //
7 // //
8 // //
14 //******************************************************************************//
15 //******************************************************************************//
16 // recieve.v //
17 // //
18 // The recieve module serves as the trasnmit block for UART communiaction. //
19 // It consists of several components and will later be used in the UART //
20 // block //
21 // //
22 // @input clk, rst, READ, [19:0] k, [7:0] switches, rx //
23 // @output rxReady, [7:0]rxStatus, [7:0] UART_RDATA //
24 // //
25 //******************************************************************************//
26 module recieve(clk, rst, READ, k, rx, eight, pen, ohel, rxStatus, rxReady, UART_RDATA);
27 input clk, rst, rx, eight, pen, ohel;
28 input [18:0] k;
29 input [7:0] READ;
30 output reg rxReady;
31 output reg [7:0] UART_RDATA, rxStatus;
32
33 wire btu, shiftHigh;
34 reg start, nStart,done, doit, nDoit, parity_error, framing_error, overflow_error;
35 reg [1:0] state, nState;
36 reg [9:0] nRX, shiftedReg;
37 reg [18:0] bitTimeCount;
38 reg [3:0] bitCount;
39 reg [18:0] newK;
40
41 // Assign new K Value
42 always@(*)
43 if ({start,doit} == 2'b11)
44 newK = k >> 1;
45 else
46 newK = k;
47
48 // Assign btu wire
49 assign btu = (bitTimeCount == newK);
50
51 // Bit Time Counter
53 if (rst)
55 else if (btu)
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57 else if (doit)
58 bitTimeCount <= bitTimeCount + 19'b1;
59 else
60 bitTimeCount <= bitTimeCount;
61
62 // Done is based on which bitCount value is reached
63 always@(*)
64 case({pen,eight})
65 2'b00: done = (bitCount == 4'b1001);
66 2'b01: done = (bitCount == 4'b1010);
67 2'b10: done = (bitCount == 4'b1010);
68 2'b11: done = (bitCount == 4'b1011);
69 default: done = (bitCount == 4'b1001);
70 endcase
71
72 // Bit Counter
74 if (rst)
76 else if (done)
78 else if ({doit,btu} == 2'b11)
79 bitCount <= bitCount + 4'b1;
80 else
81 bitCount <= bitCount;
82
83 // Assign Shift High
84 assign shiftHigh = (~start & btu);
85
86 // Fill Shift Register with RX values
88 if (rst)
89 nRX <= 10'b0;
90 else if (shiftHigh)
91 nRX <= {rx,nRX[9:1]};
92 else
93 nRX <= nRX;
94
95 // Right Justify Module
96 always@(*)
97 case({eight,pen})
98 2'b00:
99 begin
100 shiftedReg = {2'b0, nRX[9:2]};
101 UART_RDATA = {1'b0, nRX[6:0]};
102 end
103 2'b01:
104 begin
106 UART_RDATA = {1'b0, nRX[6:0]};
107 end
108 2'b10:
109 begin
111 UART_RDATA = { nRX[7:0] };
112 end
113 2'b11:
114 begin
115 shiftedReg = { nRX[9:0] };
Valenzuela 72

Prepared by:
Paul Valenzuela
Date:
May 12, 2020
Document Name:
Final Specification
116 UART_RDATA = { nRX[7:0] };
117 end
118 default:
119 begin
121 UART_RDATA = {1'b0, nRX[6:0]};
122 end
123 endcase
124
125 // Assign RX Status
126 always@(*)
127 rxStatus = {3'b0, overflow_error, framing_error, parity_error, 1'b0, rxReady};
128
129 // Parity Error RS flop
131 if (rst)
132 parity_error <= 1'b0;
133 else if (READ[0])
134 parity_error <= 1'b0;
135 else if ({done,pen} == 2'b11)
136 case ({eight,ohel})
137 2'b00 : parity_error <= shiftedReg[7] ^ (^(shiftedReg[6:0]));
138 2'b01 : parity_error <= shiftedReg[7] ^ (~^(shiftedReg[6:0]));
139 2'b10 : parity_error <= shiftedReg[8] ^ (^(shiftedReg[7:0]));
140 2'b11 : parity_error <= shiftedReg[8] ^ (~^(shiftedReg[7:0]));
141 endcase
142 else
143 parity_error <= parity_error;
144
145 // Framing Error RS Flop
147 if (rst)
148 framing_error <= 1'b0;
150 framing_error <= 1'b0;
151 else if(done)
152 case({eight,pen})
153 2'b00 : framing_error <= ~shiftedReg[7];
157 endcase
158 else
159 framing_error <= framing_error;
160
161 // Overflow Error RS Flop
163 if(rst)
164 overflow_error <= 1'b0;
167 else if (rxReady & done)
169 else
170 overflow_error <= overflow_error;
171
172 // RXReady RS Flop
174 if (rst)
Valenzuela 73

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