ANALOG INTEGRATED CIRCUIT DESIGN Chapter 15 presented by Oveis Dehghantanha in University of Birjand

1. Data Converter
Fundamentals
1
Seyyed Mohammad Razavi, Associate Professor
Oveis Dehghantanha, PhD candidate
Faculty of Electrical and Computer Engineering, University
of Birjand, Birjand, South Khorasan, Iran
November 2019

2. 2
4. IDEAL D/A CONVERTER
5. IDEAL A/D CONVERTER
6. QUANTIZATION ERROR
7. SIGNED CODES
8. PERFORMANCE LIMITATIONS
8.1 RESOLUTION
8.2 OFFSET ERROR AND GAIN ERROR
8.3 LINEARITY
8.4 ACCURACY
8.5 SETTLING TIME
8.6 GLITCH
8.7 SIGNAL TO NOISE RATIO (SNR)
8.8 TOTAL HARMONIC DISTORTION (THD)
8.9 SIGNAL TO NOISE AND DISTORTION (SINAD)
8.10 EFFECTIVE NUMBER OF BITS (ENOB)
8.11 CRITICAL PERFORMANCE LIMITATIONS SUMMERY
3. ALIASING
1. INTRODUCTION TO A/D AND D/A
2. SAPMLING THEOREM
9. DATA SHEETS

3. 1. INTRODUCTION TO A/D AND D/A
3

4. 4 Introduction to A/D and D/A

5. 5 Introduction to A/D and D/A

6. 6 Introduction to A/D and D/A

7. 7 Introduction to A/D and D/A

8. 8 Introduction to A/D and D/A

9. 9 Introduction to A/D and D/A

10. 10 Introduction to A/D and D/A

11. 11 Introduction to A/D and D/A

12. 12 Introduction to A/D and D/A

13. 13 Introduction to A/D and D/A

14. 14 Introduction to A/D and D/A

15. 15 Introduction to A/D and D/A

16. 2. SAPMLING THEOREM
16

17. 17 Sampling Theorem

18. 18 Sampling Theorem

19. 19 Sampling Theorem

20. 20 Sampling Theorem

21. 21 Sampling Theorem

22. 22 Sampling Theorem

23. 23 Sampling Theorem

24. 3. ALIASING
24

25. 25 Aliasing

26. 4. IDEAL D/A CONVERTER
26

27. 27
 𝑉𝑜𝑢𝑡 = 𝑉𝑟𝑒𝑓 . ( 𝑏1.2−1
+ 𝑏2.2−2
+ … + 𝑏 𝑁.2−𝑁
)
 𝑉𝐿𝑆𝐵 : the voltage change when one bit changes.
𝑉𝐿𝑆𝐵 =
𝑉 𝑟𝑒𝑓
2 𝑁
 1 LSB : useful in measuring errors.
1 LSB =
1
2 𝑁
Ideal D/A Converter

28. 28
The ideal Transfer Function (D/A)
Ideal D/A Converter

29. 5. IDEAL A/D CONVERTER
29

30. 30
 𝑉𝑟𝑒𝑓 . ( 𝑏1.2−1 + 𝑏2.2−2 + … + 𝑏 𝑁.2−𝑁 ) = 𝑉𝑖𝑛 ± 𝑉𝑥
-
1
2
𝑉𝐿𝑆𝐵 < 𝑉𝑥 <
1
2
𝑉𝐿𝑆𝐵
 There is a range of valid input values that produce the same digital output word. This
signal ambiguity produces what is known as quantization error.
 Note that no quantization error occurs in the case of a D/A converter since the output
signals are well defined.
Ideal A/D Converter

31. 31
The ideal Transfer Function (A/D)
Ideal A/D Converter

32. 6. QUANTIZATION ERROR
32

33. 33
 Quantization error can be modelled as an additive noise source and then the
power of this noise source can be found.
 𝑉𝑄 = 𝑉1 - 𝑉𝑖𝑛 or 𝑉1 = 𝑉𝑖𝑛 + 𝑉𝑄
 Quantized signal, 𝑉1, can be modelled as the input signal plus some additive
quantization noise.
Quantization Error

34. 34
Quantization Error Types
Quantization Error

35. 7. SIGNED CODES
35

36.  In many applications, it is necessary to create a converter that operates with both
positive and negative analog signals, resulting in the need for both positive and
negative digital representations. Typically, the analog signal is bounded by
±0.5𝑉𝑟𝑒𝑓, such that its full-scale range is the same magnitude as in the unipolar
case.
 Some common signed digital representations are sign magnitude, 1’s complement,
offset binary, and 2’s complement.
36 Signed Codes

37. Some 4-bit signed digital representations
37 Signed Codes

38. Sign Magnitude
 For negative numbers in the sign-magnitude case, all the bits are the same as for
the positive number representation, except that the MSB is complemented.
 For example, the sign-magnitude representation for 5 is 0101, whereas for –5 it is
1101
38 Signed Codes

39. 1’s Complement
 In 1’s-complement representation, negative numbers are represented as the
complement of all the bits for the equivalent positive number.
 For example, here, 5 is once again 0101, whereas –5 is now 1010.
39 Signed Codes

40. Offset Binary
 The offset-binary representation is obtained by assigning 0000 to the most negative
number and then counting up, as in the unipolar case.
 For example, the offset-binary code for the number 5 in the 4-bit case is the same as the
unipolar code for the number 13, which is 1101 and The offset-binary code for –5 is the
same as the unipolar code for 3, which is 0011.
 offset-binary code does not suffer from redundancy, and all sixteen numbers are uniquely
represented.
 This code has the advantage that it is closely related to the unipolar case through a simple
offset.
40 Signed Codes

41. 2’s Complement
 2’s-complement representation is obtained from the offset-binary number by simply
complementing the MSB.
 For the 4-bit example, 5 becomes 0101 in 2’s complement, whereas –5 is now 1011.
 2’s-complement code for negative numbers can also be obtained by adding 1 LSB to
the equivalent 1’s-complement code.
41 Signed Codes

42. Some 4-bit signed digital representations
42 Signed Codes

43. 8. PERFORMANCE LIMITATIONS
43

44. 44
8.1. RESOLUTION

45.  The resolution of a converter is defined to be the number of distinct analog levels
corresponding to the different digital words.
 An N-bit resolution implies that the converter can resolve 2 𝑁 distinct analog levels.
 Resolution is not necessarily an indication of the accuracy of the converter, but instead it
usually refers to the number of digital input or output bits.
45 Resolution

46. 46
 The resolution of data converters may be expressed in several different ways: the weight of
the Least Significant Bit (LSB), parts per million of full-scale (ppm FS), millivolts (mV)
Resolution

47. 47
8.2. OFFSET ERROR & GAIN ERROR

48. 48 Offset Error
 The offset error is defined as the deviation of the actual ADC’s transfer function from the
perfect ADC’s transfer function at the point of zero to the transition measured in the LSB bit.
 When the transition from output value 0 to 1 does not occur at an input value of 0.5LSB,
then we say that there is an offset error.

49. 49 Offset Error
 With positive offset errors, the output value is larger than 0 when the input voltage is less
than 0.5LSB from below.
 In below, the first transition occurs at 0.5LSB and the transition is from 1 to 2. But 1 to 2
transitions should occur at 1.5LSB for perfect case. So the difference (Perfect – Actual =
1.5LSB – 0.5LSB = +1LSB) is the offset error.

50. 50 Offset Error
 With negative offset errors, the input value is larger than 0.5LSB when the first output value
transition occurs.
 In the Figure 3-2 Negative Offset Error, the first transition occurs at 2LSB and the transition
is from 0 to 1. But 0 to 1 transition should occur at 0.5LSB for perfect case. So the difference
(Perfect – Actual = 0.5LSB– 2LSB = -1.5LSB) is the offset error.

51. 51 Offset Error
 Offset errors limit the available range for the converter.
 A large positive offset error causes the output value to saturate at maximum before the input
voltage reaches maximum.
 A large negative offset error gives output value as 000 for the smallest input voltages.

52. 52 Gain Error
 The gain error is defined as the deviation of the midpoint of the last step of the actual
ADC from the midpoint of the last step of the ideal ADC, after compensated for offset
error.
 Gain errors cause the actual transfer function slope to deviate from the ideal slope.

53. 53 Gain Error
 If the transfer function of the actual ADC occurs above the ideal straight line, then it
produces positive gain error.
 In positive gain error, the output value saturates before the input voltage reaches its
maximum. The vertical arrow shows the midpoint of the last output step.

54. 54 Gain Error
 If the transfer function of the actual ADC occurs below the ideal straight line, then it
produces negative gain error.
 In negative gain error, the output value has only reached six when the input voltage is at
its maximum. This results in a negative deviation for the actual transfer function.

55. 55 Gain Error
 This gain error can be measured and compensated by scaling the output values.
 The gain error is calculated as LSBs from a vertical straight line drawn between the
midpoint of the last step of the actual transfer curve and the ideal straight line.
 Typically gain/offset is most easily compensated by the digital pre/post-processor.

56. 56 Full Scale Error
 Full scale error is the deviation of the last transition (full scale transition) of the
actual ADC from the last transition of the perfect ADC, measured in LSB or volts.
Full scale error is due to both gain and offset errors.

57. 57
8.3. LINEARITY

58. 58 Linearity
Non-Linearity
 When offset and gain errors are compensated, the actual transfer function should now
be equal to the transfer function of perfect ADC.
 However, non-linearity in the ADC may cause the actual curve to deviate slightly from
the perfect curve, even if the two curves are equal around 0V and at the point where the
gain error was measured.
 There are two major types of non-linearity that degrade the performance of ADC. They
are differential non-linearity (DNL) and integral non-linearity (INL).

59. 59 Linearity
 Differential nonlinearity (DNL) is defined as the maximum and minimum difference in
the step width between actual transfer function and the perfect transfer function.
 Non-linearity produces quantization steps with varying widths.

60. 60 Linearity
Steps for Differential Nonlinearity Measurement:
1. Endpoints connected
2. Ideal Characteristics derived
3. DNL measured

61. 61 Linearity
1. Endpoints connected

62. 62 Linearity
2. Ideal Characteristics derived

63. 63 Linearity
3. DNL measured

64. 64
 Typically, worst-case DNL along with the vector for
the entire code is reported.
Linearity

65. 65 Linearity
Differential Non-Linearity & Missing Code & Non-Monotonicity

66. 66 Linearity
Integral Nonlinearity (INL)
 Integral Nonlinearity is the deviation of code transition from
its ideal location.
 Offset and Gain errors are ignored in INL calculation.
 A straight line through the endpoints is usually used as
reference.
 Ideal converter steps is found for the endpoint line, then INL
is measured.

67. 67 Linearity
 INL is found by computing the cumulative sum of DNL :
INL[ m] = 𝑖=1
𝑚−1
DNL[i]

68. 68 Linearity
 INL is found by computing the cumulative sum of DNL :
INL[ m] = 𝑖=1
𝑚−1
DNL[i]

69. 69 Linearity

70. 70 Linearity

71. 71 Linearity
Methods for Integral Nonlinearity(INL) Measurement:
1. End-Point
2. Best-Fit

72. 72 Linearity
1. End-Point
 A straight line through the endpoints is used as reference.
 Offset and Gain errors are ignored.
 Ideal converter steps is found for the endpoint line, then INL is
measured.

73. 73 Linearity

74. 74 Linearity

75. 75 Linearity
2. Best-Fit
 A best-fit line (in the least mean squared sense).
 Offset and Gain errors are not ignored.
 Ideal converter steps is found, then INL is measured.

76. 76 Linearity

77. 77 Linearity

78. 78
8.4. ACCURACY

79.  The accuracy of a converter is a measure of the difference between the actual output
voltage and the expected output voltage.
79 Accuracy

80.  Total Unadjusted Error (TUE) or Absolute Error includes offset, gain, and integral
linearity errors and also the quantization error in the case of an ADC.
 As seen from earlier sections, offset and gain error reduces the effective converter range.
The Total Unadjusted Error represents a reduction in the converter range.
 It is specified as a percentage of full-scale or maximum output voltage.
80 Accuracy

81. 81
8.5. SETTLING TIME

82.  The settling time of a D/A is the time from a change of digital code to when the output
comes within and remains within some error band (±1/2LSB).
 The settling time of a DAC is made up of four different periods:
1. The switching time or dead time
2. The slewing time
3. The recovery time
4. The linear settling time
82 Settling Time (D/A)

83.  The switching time or dead time: during which the digital switching, but not the output, is
changing
 The slewing time: during which the rate of change of output is limited by the slew rate of
the DAC output
 The recovery time: when the DAC is recovering from its fast slew and may overshoot
 The linear settling time: when the DAC output approaches its final value in an exponential
or near-exponential manner.
 Settling time is one of the important parameters for DACs.
 Settling time should be kept as small as possible to keep the distortion on the analog
output signal low.
83 Settling Time (D/A)

84. 84
8.6. GLITCH

85.  Ideally, when a DAC output changes it should move from one value to its new one
monotonically.
 In practice, the output is likely to overshoot, undershoot, or both (see Figure below).
 The uncontrolled movement of DAC output from one value to a new value during the
transition is called as glitch.
85 Glitch (D/A)

86.  Glitch can arise from two mechanisms:
1. capacitive coupling of digital transitions to the analog output.
2. the effects of some switches in the DAC operating more quickly than others and
producing temporary spurious outputs.
 Capacitive coupling frequently produces roughly equal positive and negative spikes
(sometimes called a doublet glitch) which more or less cancel in the longer term.
 The glitch produced by switch timing differences is generally unipolar, much larger, and
of greater concern.
86 Glitch (D/A)

87. 87
8.7. SIGNAL TO NOISE RATIO (SNR)

88.  SNR is defined as the ratio of the output signal voltage level to the output noise level. It is
usually represented in decibels (dB) and calculated using the following formula.
For example if the output signal amplitude is 1V(RMS) and the output noise amplitude is 1mV(RMS), then
the SNR value would be 60dB.
 The above formula is a general definition for SNR.
 The SNR value of an ideal ADC is calculated using the following formula:
SNR (dB) = 6.02N+1.76(dB) ; N is the resolution (no. of bits) of the ADC
For example an ideal 10-bit ADC will have an SNR of approximately 62dB.
 In practical applications, to achieve better performance, the SNR value of an ADC should
be higher.
88 Signal to Noise Ratio (A/D)

89. 89
8.8. TOTAL HARMONIC DISTORTION (THD)

90.  Whenever an input signal of a particular frequency passes through a non-linear device(for
example a converter), it will produce harmonics that were not present in the original
signal. These harmonic frequencies usually distort the output which degrades the
performance of the system.
 This effect can be measured using the term called total harmonic distortion (THD).
 In terms of RMS voltage, the THD is given by:
 The THD value increases with the increase in the input signal amplitude and frequency.
 In practical applications, to achieve better performance, the THD value of an ADC should
be lesser.
90
Total Harmonic Distortion (A/D)

91. 91
8.9. SIGNAL TO NOISE AND DISTORTION
(SINAD)

92.  Signal to noise and distortion (SINAD) is a combination of SNR and THD parameters. It
is defined as the ratio of the RMS value of the signal amplitude to the RMS value of all
other spectral components, including harmonics, but excluding DC.
 For representing the overall dynamic performance of an ADC, SINAD is a good choice
since it includes both the noise and distortion components.
 SINAD can be calculated with SNR and THD by:
 In practical applications, to achieve better performance, the SINAD value of an ADC
should be higher.
92
Signal to Noise and Distortion (A/D)

93. 93
8.10. EFFECTIVE NUMBER OF BITS (ENOB)

94.  Effective number of bits (ENOB) is the number of bits with which the ADC behaves like
a perfect ADC.
 It is another way of representing the signal to noise ratio and distortion (SINAD) and can
be derived from the following formula.:
 In practical applications, to achieve better performance, the ENOB value of an ADC
should be as close as possible to the resolution of the ADC.
94
Effective Number of Bits (A/D)

95. 95
8.11. CRITICAL PERFORMANCE LIMITATIONS SUMMERY

96. 96
 Performance limitations which are critical to choose appropriate data converter are
gathered in one figure.
 This figure includes not only common specifications of both A/D and D/A, but also
specific factures of them.
 It is a wide figure, so click here to see it with original size and quality.
Critical Performance Limitations Summery

97. 97
10. DATA SHEET

98.  AD7225 : Quad 8-Bit DAC, Fabricated by Analog Devices.
 AD7228A : Octal 8-Bit DAC, Fabricated by Analog Devices.
 DAC0800 : 8-Bit DAC, Fabricated by Texas Instruments.
 MAX5360 : 6-Bit DAC, Fabricated by Maxim Integrated.
98
D/A Data Sheets

99.  AD7822 : 8-Bit ADC, Fabricated by Analog Devices.
 TLC0820AC : 8-Bit ADC, Fabricated by Texas Instruments.
 MAX105 : Dual 6-Bit ADC, Fabricated by Maxim Integrated.
 MAX1003 : Dual 6-Bit ADC, Fabricated by Maxim Integrated.
99
A/D Data Sheets

100. 100
Thank You
For Your Attention