a detail and comprehensive detail about piplining

2. PRESENTED BY
OSAMA TAHIR
09-EE-88

4. Shibu lijack

5.  A Technique used in Advance Microprocessor where
Microprocessor begins executing the second instruction
before the first has been completed
 An implementation technique that overlaps the execution
of multiple instructions.

6. Instruction
Fetch
We devide its execution into
5 stages
Instruction
Decode
1)
2) (ID) Execution
cycle
3)
Memory
5)
Access
Write Back
Cycle

7. Instruction Instr. Decode Execute Memory Write
Fetch Reg. Fetch Addr. Calc Access Back
Next PC
MUX
Next SEQ PC
Adder
Zero?
4 RS1
MUX MUX
RS2
Address
Memory
Reg File
Inst
ALU
L
Memory
RD
Data
M
MUX
D
Sign
Imm Extend
WB Data

8.  TO MAKE FAST CPU’S

 It yields a reduction in the average execution time per
execution.

9.  Hazards are those situations ,that prevent the next
instruction in the instruction stream from
executing during its designated clock cycle
 It may reduce the speed and the performance of
The microprocessor

10. 



11. 



12.  Strucural Hazard arises due to the Resource conflict
 hardware cannot support this combination of instructions - two
instructions need the same resource.
 Attempt to use the same resource by two or more instructions at the
same time

14. Example:
Single Memory for instructions and data
 Accessed by IF stage
 Accessed at same time by MEM stage

17. Solution 1: Delay Access to Resource
 Must have mechanism to delay access to resource
 Stall the pipeline until resource is available
Solution 2: Add more hardware resources
This is most appropriate to structural hazards; if a piece of hardware
has to be used twice in an instruction, see if there is a way to
duplicate the hardware.

19. TYPES...




20.  Data hazards occur when the pipeline changes the order of
read/write accesses to operands so that the order differs from
the order they see by sequentially executing instructions on
an unpipelined machine.
 Data hazards can occur when two instructions use data from
the same register.
 Arises due to data dependency between instructions

21. CLASSIFICATION
RAW (read after write )
 the current instruction must wait to read data until after a
previous instruction writes the correct data.
 Instruction J should read an operand after it is written by I
Called a data dependence in compiler terminology
I: mul R1, R2, R3 # R1 is written
J: sub R4, R1, R3 # R1 is read
 Hazard occurs when J reads the operand before I writes
it

22. (WAR) Write After Read
 the current instruction must wait to write data until after a previous
instruction reads the old data,
 Instruction J should write its result after it is read by I
I: sub R4, R1, R3 # R1 is read
J: add R1, R2, R3 # R1 is written
 Hazard occurs when J writes R1 before I reads it

23. Write After Write(WAW)
 The current instruction must wait to write data until after a
previous instruction writes to the same register.
 Inst J should write its result after I
 Called output-dependence in compiler terminology
 I: sub R1, R4, R3 # R1 is written
 J: add R1, R2, R3 # R1 is written
again

25. 
writes a state element in the first half of clock cycle and reads it in
the next half)

If the data is available somewhere, but is just not where we want
it, we can create extra data paths to ``forward'' the data to where it is needed.
This is the best solution, since it doesn't slow the machine down and doesn't
change the semantics of the instruction set.

We can simply make the later instruction wait until the hazard
resolves itself. This is undesireable because it slows down the machine, but
may be necessary.

26. TYPES...




27.  we fetch instructions one after another in order. As long
as location of the next instruction is known, this process
can go forward. When a branch instruction is fetched, the
next instruction location is not known until the branch
instruction finishes execution. Thus, we may have to wait
until the correct location of the next instruction is known
before fetching more instructions.
 Control hazards occur less frequently than data hazards

28.  Stall
We can simply make the later instruction wait until the hazard
resolves itself. This is undesireable because it slows down the machine, but
may be necessary
 Forward Data
If the data is available somewhere, but is just not where we want
it, we can create extra data paths to ``forward'' the data to where it is needed.
 Predict
assume an outcome and continue fetching (undo if prediction is
wrong)

30. References
 http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=4237770
&queryText%3Dcontrol+hazards+in+pipelining%26openedRefinements%
3D*%26searchField%3DSearch+All
 http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/hazards.html
 http://wearcam.org/ece385/lectureB/structuralhazardwithsinglecache.gif
 http://www.scribd.com/doc/21393075/Pipeline-Hazards-Part-1