The OnePlus 5T uses the Qualcomm Snapdragon 835 system on chip which features an octa-core CPU called Kryo 280 consisting of four high-performance cores running up to 2.45 GHz and four efficiency cores running up to 1.9 GHz. The Kryo 280 uses a 64-bit ARMv8-A instruction set and employs a multi-level cache hierarchy with separate 4KB L0 caches for each core, 16KB L1 caches, and a shared 2MB L2 cache.

2. OnePlus 5T
MUHAMMAD OSAMA KHALID BCS163024
MUHAMMAD MOHSIN ALI BCS163999
ABDUL RAFAY BCS163070

3. ABSTRACT VIEW
1 SoC Qualcomm SnapDragon
835 MSM8998
2 Process Technology 10nm
3 CPU 4x 2.54 GHz karyo 280
4x 1.9 GHz karyo 280
4 CPU Bits 64Bits
5 Instruction Set ARMv8-A
Level 0 Cache Memory (L0) 4Kb+4Kb
6 Level 1 Cache Memory (L1) 16Kb+16Kb(Split)
7 Level 2 Cache Memory (L2) 2MB(Shared)
8 CPU Cores 8

4. ABOUT ONEPLUS 5T
1) ANDROID
ONEPLUS
2) OS
3) CHIPSET
4) CPU
5) GPU

5. SYSTEM ON CHIP (SOC)
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6. QUALCOMM SNAPDRAGON 835
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8. CPU
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9. KRYO 280
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10. ARCHITECTURAL DESIGN OF KRYO 280:
CPU Core 1
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
CPU Core 4
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
CPU Core 3
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
CPU Core 2
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
Shared L2 Cache(2Mb)
Bi-Directional Bus
Memory Controller
THE SNAPDRAGON 835 IS COMPRISED OF FOUR PERFORMANCE KRYO
280 CORES RUNNING AT UP TO 2.45 GHZ

11. ARCHITECTURAL DESIGN OF KRYO 280:
CPU Core 5
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
CPU Core 8
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
CPU Core 7
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
CPU Core 6
L0 Cache(4kb+4kb)
L1
Instruction
Cache
(16kb)
L1
Data
Cache
(16kb)
Shared L2 Cache(1Mb)
Bi-Directional Bus
Memory Controller
THE SNAPDRAGON 835 IS COMPRISED OF FOUR EFFICIENCY KRYO
280 CORES RUNNING AT UP TO 1.9 GHZ

12. CPU BITS
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13. ARMV8-A INSTRUCTION SET ARCHITECTURE:
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Family Cache Typical
MIPS @
MHz
Cache
Size
Cache
Line Size
Associativi
ty
Location Write
Buffer
Size
ARM8-A 8 Kb
Unified
84 MIPS
@ 72 MHz
8 Kb 4 Words 4-Way Logical 8 Words

14. CACHE
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15. LEVEL 0 CACHE
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16. LEVEL 1 CACHE
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17. ARM CACHE AND WRITE BUFFER ORGANIZATION:
Arm
Core
R15
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R0
Address
Translatio
n
Write
Buffer
Level 1
Cache
Level 0
Cache
Main
Memory
Physical Address

18. ARM CACHE ADDRESSING:
CPU MM
MMU
Cache
MMCPU
MMU
Cache
Logical Address Physical Address Physical Address
Logical Cache
Data
Data
Physical Cache
Logical Address

19. Thank You!