6. 6
A step equal to ∆𝑉 at X results in a change of −𝐴∆𝑉 at Y yielding a total change of (1 + A)∆𝑉 in the voltage across 𝐶𝐹.
General
Example with 2 different Gain(A):
𝑄𝐶𝐹 = 𝐶𝐹 ∗ 𝑉𝐶𝐹
𝑉𝐶𝐹 = −∆𝑉 − ∆𝑉 = −2∆𝑉
𝑉𝐶𝐹 = −100∆𝑉 − ∆𝑉 = −101∆𝑉
The charge drawn by 𝑪𝑭 from Vin is equal to 𝟏 + 𝑨 𝑪𝑭∆𝑽 ,so the equivalent input capacitance equal to 𝟏 + 𝑨 𝑪𝑭.
9. Small signal Common-Source amplifier:
The excel model uses quantitively analysis to confirm the simulations results.
The model is based on small signal model of 2 stages amplifier.
The second stage based on small signal Common-Source amplifier.
10. 10
𝜔𝑖𝑛 =
1
𝑅𝑠 𝐶𝐺𝑆 + 1 + 𝑔𝑚𝑅𝐷 𝐶𝐺𝐷
𝜔𝑜𝑢𝑡 =
1
𝑅𝐷 𝐶𝐷𝐵 + 𝐶𝐺𝐷
CS Small signal
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛
𝑠 =
−𝑔𝑚𝑅𝐷
(1 +
𝑠
𝜔𝑖𝑛
)(1 +
𝑠
𝜔𝑜𝑢𝑡
)
Miller effect is expressed within the
expression
𝑪_𝑴𝒊𝒍𝒍𝒆𝒓
This estimation lacked by two major
assumptions:
The existence of zeros in the circuit
The varies of the gain (e.g. ,output
𝑂𝑢𝑡𝑝𝑢𝑡 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒 ∶ 𝐶𝐷𝐵 + 1 − 𝐴𝑣
−1
𝐶𝐺𝐷 ≈ 𝐶𝐷𝐵 + 𝐶𝐺𝐷
High frequency model for CS stage:
Small signal CS model:
11. (gmRD+1)*c gd+CGS fp1[kHz]
8.8548E-11 1.11
(CDB+CGD)*RD fp2[kHz]
1.4784E-06 1062.50
Poles simple model
• Pole1:quite matches to the analytic calculation (1.1[kHz] compared to 1.095 [kHz] )
• Pole2: big difference between analytic to simulation results (1.062[MHz] compared to 38
[MHz] )
The Gain varies a lot with frequency.thus,pole2 calculation is deviant from
simulation.
Analytic calculation:
12. 12
𝜔𝑃,𝐴 =
1
𝑅𝑠 𝐶𝐺𝑆1 + 1 +
𝑔𝑚1
𝑔𝑚2
𝐶𝐺𝐷1
CGD1 is multiplied by ~2 rather than a large voltage gain in a simple Common-
Source stage
𝜔𝑃,𝑋 =
𝑔𝑚2
2𝐶𝐺𝐷1 + 𝐶𝐷𝐵1 + 𝐶𝑆𝐵2 + 𝐶𝐺𝑆2
This pole is much far from the origin than the other two
The output pole:
𝜔𝑃,𝑌 =
1
𝑅𝐷(𝐶𝐷𝐵2 + 𝐶𝐿 + 𝐶𝐺𝐷2)
An example of a circuit which miller effect is negligible
Let consider the Cascode shown on the right.
The miller effect of CGD1 is determined by the gain from A to
X
By the assumption M1&M2 have roughly equal dimensions:
Cascode with CG over CS
13. 13
We now obtain the exact transfer function by the precise
small signal analytic model.
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛
𝑠 =
(𝐶𝐺𝐷𝑠 − 𝑔𝑚)𝑅𝐷
𝑅𝑆𝑅𝐷𝞮𝑠2 + 𝑠 𝑅𝑆 1 + 𝑔𝑚𝑅𝐷 𝐶𝐺𝐷 + 𝑅𝑆𝐶𝐺𝑆 + 𝑅𝐷 𝐶𝐺𝐷 + 𝐶𝐷𝐵 + 1
𝞮 = 𝐶𝐺𝑆𝐶𝐺𝐷 + 𝐶𝐺𝑆𝐶𝐷𝐵 + 𝐶𝐺𝐷𝐶𝐷𝐵
𝜔𝑝1 =
1
𝑅𝑆 1 + 𝑔𝑚𝑅𝐷 𝐶𝐺𝐷 + 𝑅𝑆𝐶𝐺𝑆 + 𝑅𝐷 𝐶𝐺𝐷 + 𝐶𝐷𝐵
Two of the input poles expressions 𝜔𝑖𝑛, 𝜔𝑝1(𝜔𝑖𝑛 in slide 7: ) are not identical.
The difference is 𝑅𝐷 𝐶𝐺𝐷 + 𝐶𝐷𝐵 ,that is negligible for most of the cases.
As for the output pole:
𝑪_𝑴𝒊𝒍𝒍𝒆𝒓
𝜔𝑝2 =
𝑅𝑆 1+𝑔𝑚𝑅𝐷 𝐶𝐺𝐷+𝑅𝑆𝐶𝐺𝑆+𝑅𝐷 𝐶𝐺𝐷+𝐶𝐷𝐵
𝑅𝑆𝑅𝐷(𝐶𝐺𝑆𝐶𝐺𝐷+𝐶𝐺𝑆𝐶𝐷𝐵+𝐶𝐺𝐷𝐶𝐷𝐵)
𝑝𝑟𝑜𝑝𝑜𝑟𝑡𝑖𝑜𝑛𝑎𝑙 𝑡𝑜
1
𝜔𝑝1
Common-Source with RD
Small signal model
15. In addition to lowering the required capacitor value (𝐶𝑔𝑑), miller compensation entails another important
property: pole splitting
• 𝜔𝑝1 is proportional to 𝐶𝐺𝐷
• 𝜔𝑝2 has weak impact by 𝐶𝐺𝐷
17. As for 𝝎𝑷𝟐 ,the pole location should not be dependent by the gain : 𝜔𝑝2 ≈
1
𝑅𝐷 𝐶𝐷𝐵+𝐶𝐺𝐷
For large Cgs that satisfy the condition 𝐶𝐺𝑆≫ 1 + 𝑔𝑚𝑅𝐷 𝐶𝐺𝐷 +
𝑅𝐷 𝐶𝐺𝐷+𝐶𝐷𝐵
𝑅𝑆
By doubling gm(gain) ,both poles are at the same location, not dependent by gain.
18. 18
Example of Common-Source with an ideal current source (i.e., large RD)
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛
𝑠 =
𝐶𝐺𝐷𝑠 − 𝑔𝑚
𝑅𝑆𝞮𝑠2 + 𝑠 𝑅𝑆𝑔𝑚𝐶𝐺𝐷 + 𝐶𝐺𝐷 + 𝐶𝐷𝐵
As expected, the circuit exhibits two poles- one at the origin because the
DC gain is infinity. Poles can switch positions
The magnitude of the output pole given by:
𝜔𝑝2 ≈
1 + 𝑔𝑚𝑅𝑆 𝐶𝐺𝐷 + 𝐶𝐷𝐵
𝑅𝑆(𝐶𝐺𝐷𝐶𝐺𝑆 + 𝐶𝐺𝑆𝐶𝐷𝐵 + 𝐶𝐺𝐷𝐶𝐷𝐵)
For large CDB we get:
𝜔𝑝2 ≈
1
𝑅𝑆(𝐶𝐺𝑆 + 𝐶𝐺𝐷)
Indicating that CGD experiences no Miller multiplication, the voltage gain from node X to the
output begins to drop at low frequencies, as a result for close frequencies to 𝑅𝑆[𝐶𝐺𝑆 + 𝐶𝐺𝐷]
the effective gain is quite small so 𝐂𝐆𝐃 1 − 𝐴𝑉 ≈ 𝐶𝐺𝐷
Transient response for Larger Cload:
Common-Source with Large RD
19. On the left: 10x gm with large 𝑪𝑫𝑩 . Results :small change on 𝝎𝒑𝟏,bearly change at 𝝎𝒑𝟐
On the right: 10x gm with small 𝑪𝑫𝑩. Results: two-decade(100x) change of 𝝎𝒑𝟏,10x change at 𝝎𝒑𝟐
• As CDB is larger the less it dependent on the gain
21. 21
𝜔𝑧 =
𝑔𝑚
𝐶𝐺𝐷
The exact transfer function for small signal:
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛
𝑠 =
(𝐶𝐺𝐷𝑠 − 𝑔𝑚)𝑅𝐷
𝑅𝑆𝑅𝐷𝞮𝑠2 + 𝑠 𝑅𝑆 1 + 𝑔𝑚𝑅𝐷 𝐶𝐺𝐷 + 𝑅𝑆𝐶𝐺𝑆 + 𝑅𝐷 𝐶𝐺𝐷 + 𝐶𝐷𝐵 + 1
𝞮 = 𝐶𝐺𝑆𝐶𝐺𝐷 + 𝐶𝐺𝑆𝐶𝐷𝐵 + 𝐶𝐺𝐷𝐶𝐷𝐵
Which exhibits a right-half plane zero given by:
Located in the right-half plane Cgd provides a feedforward path that conduct the input
signal to the output at very high frequencies.
As Cgd gets larger it provides lower impedance path between the gate and the drain
22. 22
The right-half plane zero is bad. How?
• By moving the phase crossover towards the origin
• By pushing the gain crossover away from the origin
And by that, Causing the stability degrades considerably
𝜔𝑧𝑒𝑟𝑜 =
𝑔𝑚
𝐶𝐶 + 𝐶𝐺𝐷
Various techniques of eliminating or moving the zero have been invented.
Here some of them.
1.Place a resistor
By placing a resistor in series with CGD the zero frequency is being modify.
In addition, the zero can be eliminated so it moves into left-half plane and cancel the second pole by:
𝜔𝑧 ≈
1
𝐶𝐶(𝑔𝑚−1 − 𝑅𝑧)
𝑅𝑍 =
𝐶𝐿 + 𝐶𝐶
𝑔𝑚 ∗ 𝐶𝑐
23. 23
Disadvantges of the resistor technique:
It is difficult to guarantee the relationship 𝑅𝑍 =
𝐶𝐿+𝐶𝐶
𝑔𝑚∗𝐶𝑐
especially when 𝐶𝐿 is variable.
The implementation of 𝑅𝑍 is typically by MOS in triode region, while
voltage is excursion are coupled through Cc.
Output swing on Rz
Rz in series with Cc to move RHP
zero
24. Simulation with/without zero compensation by resistor Rz
• Red graph with RHP zero contributes gain and decreases phase,3 poles
total
• Yellow graph represents zero compensation so there are only two poles
Extracting Rz value by the analytic excel model:
CGD[pF] CDB[pF] CGS[fF] gm[uS] RS[kohm] f1_pole[kHz] f2_pole[MHz] f_zero[MHz] RZero[kΩ] GBW[MHz]
1 0.2 1 71 1625 1.095 42.294 11.30 16.90 5.54
25. 25
Another technique for eliminating a Zero would be inserting a
source follower in series with Cc.
2.Source follower
If Cc could conduct current from the output to X but not vice versa
Then the zero would move to a very high frequency.
Additional Source follower to remove the zero
Simplified equivalent circuit
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛
𝑠 =
−𝑔𝑚1𝑅𝐿𝑅𝑆(𝑔𝑚2 + 𝐶𝐶𝑠)
…
This circuit contains a zero in left-half plane which chosen to
cancel one of the poles
𝜔𝑧𝑒𝑟𝑜 =
−𝑔𝑚2
𝐶𝐶 + 𝐶𝐺𝐷
𝜔𝑝1 ≈
1
𝑔𝑚1𝑅𝐿𝑅𝑆𝐶𝑐
𝜔𝑝2 ≈
𝑔𝑚1
𝐶𝐿𝑜𝑎𝑑
26. The primary issue of this technique is that the source follower limits the lower
end of the output voltage to 𝑉𝐺𝑆2 + 𝑉𝐼2.
𝑉𝐼2 − The Vds that I2 requires
OTA simulation with source follower remove the zero to LHP(yellow graph)
The new values of the poles like those obtained by miller approximation
Additional Source follower to remove the zero
27. 27
To prevent from Vout DC voltage to decrease it is desirable to utilize Cc to isolate
the DC levels in the active feedback stage from that at Vout.
𝐼2 = 𝐼3
𝑉𝑜𝑢𝑡
𝑉𝑖𝑛
𝑠 =
−𝑔𝑚1𝑅𝐿𝑅𝑆(𝑔𝑚2 + 𝐶𝐶𝑠)
…
Cc using as DC levels separation
Simplified equivalent circuit
𝜔𝑝1 ≈
1
𝑔𝑚1𝑅𝐿𝑅𝑆𝐶𝑐
𝜔𝑝2 ≈
𝑔𝑚2𝑅𝑠𝑔𝑚1
𝐶𝐿𝑜𝑎𝑑
The second pole has risen in magnitude by factor of 𝑔𝑚2𝑅𝑠.
-Input capacitance is measured by applying voltage step at the input and calc the charge supplied by voltage source
Cascode increase voltage gain of amplifier and the output impedance of CS while shielding as well Wx is chosen to be far
Suppressing miller effect
B
Now the transfer function is accurate
Split the poles allowing bigger BW the choice of the capacitor requires some iteration
Big cgs makes wp1 and wp2 not dependent on the Gain!
-For large CDB both poles can switch positions and miller is negligible (the gain is low far from origin) -If CDB is large wp2 isn’t dependent on the gain
-for one stage op-amp higher Cload brings the dominant pole closer to origin and improve PM (albeit, overdamped the system(slow response))
Zeta-damping ratio:zeta >=1 poles at LHP PM=100*zeta, for zeta<0.8 for second order closed loop system for zeta>0.8 PM is ~60*zeta
-while in cascode the zeros are far, in two stage amp the zero location is important
-The capacitance form parasitic path from input to output
-Like poles in LHP zero in RHP contributes phase shift -The zero slows down the drop of the magnitude pushing the gain crossover far away
the output stage exhibits 3 poles, the thirs pole is far Rz=CL+CC/gm*CC under the assumption of CE<<CL+CC
-Canceling the nondominant pole makes this technique attractive
-If Cload is variable from one part of period to another in switched capacitor circuit as example
-Cload variance requires change in Rz-Complicating the design
Output voltage excursions coupled though Cc degrading the large signal step response
-Two stages op amp without RHP zero due to source follower
-Cgs of M2is typically lower than Cc to we expect the RHP zero to be pushed further
-The output pole has moved from RLCL to gm1/CL closer to origin
-Vout now requires VDSM1 or VGS2+VI2, the largest of them
-The purpose of M2 is to use as a resistor(1/gm2) which moving the RHP zero to LHP -The topology depicted where Cc and CG stage M2 convert the output voltage swing to a current back to M1 gate
-V1 changes by deltaV and Vout by A*deltaV the current through Cc is A*deltaV*Cc*s (assumption: 1/gm2 is small)
-I2=I3 to draw the same current
