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MIPS Instruction Encoding
8/20/2022 CDA3100 2
Representing Instructions in Computers
• Note that computers only have 0’s and 1’s
• Before we can load MIPS instructions into memory,
they need to be translated into machine instructions,
which consist of only 0’s and 1’s
– In other words, we need to encode or represent
instructions
– The symbolic representation of machine instructions is
called assembly language
– The binary representation of instructions is called machine
language
• A sequence of instructions in binary form is called machine code
8/20/2022 CDA3100 3
Example
8/20/2022 CDA3100 4
MIPS Instruction Encoding
• Each MIPS instruction is exactly 32 bits
– R-type (register type)
– I-type (immediate type)
– J-type (jump type)
op rs rt rd shamt funct
op rs rt 16 bit address or constant
op 26 bit address
8/20/2022 CDA3100 5
R-Type Encoding
31
opcode rs rt rd
26 25 21 20 16 15 11 10 6 5 0
shamt funct
0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0
31
opcode rs rt rd
26 25 21 20 16 15 11 10 6 5 0
shamt funct
add $4, $3, $2
rt
rs
rd
0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0
Encoding = 0x00622020
8/20/2022 CDA3100 6
I-type Encoding
31
opcode rs rt Immediate Value
26 25 21 20 16 15 0
lw $5, 3000($2)
Immediate
rs
rt
0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
1 0
Encoding = 0x8C450BB8
0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
1 0
31
opcode rs rt
26 25 21 20 16 15 0
Immediate Value
8/20/2022 CDA3100 7
I-type Encoding
31
opcode rs rt Immediate Value
26 25 21 20 16 15 0
sw $5, 3000($2)
Immediate
rs
rt
Encoding =
31
opcode rs rt
26 25 21 20 16 15 0
Immediate Value
8/20/2022 CDA3100 8
I-type Encoding
31
opcode rs rt Immediate Value
26 25 21 20 16 15 0
sw $5, 3000($2)
Immediate
rs
rt
1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
1 0
Encoding = 0xAC450BB8
1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
1 0
31
opcode rs rt
26 25 21 20 16 15 0
Immediate Value
8/20/2022 CDA3100 9
I-type Encoding
31
opcode rs rt Immediate Value
26 25 21 20 16 15 0
addi $s0, $s0, 95
Immediate
rs
rt
Encoding =
31
opcode rs rt
26 25 21 20 16 15 0
Immediate Value
8/20/2022 CDA3100 10
I-type Encoding
31
opcode rs rt Immediate Value
26 25 21 20 16 15 0
addi $s0, $s0, 95
Immediate
rs
rt
1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1
0 0
Encoding = 0x2210005F
1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1
0 0
31
opcode rs rt
26 25 21 20 16 15 0
Immediate Value
J-type Encoding
31
opcode Jump Address
26 25 0
j 0x0040007c
Jump Address
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
0 0
Encoding = 0x0810001F
opcode
j 0x0040007c
0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
0 0
31
Jump Address
26 25 0
0x0040007c: the address of the instruction to jump to.
When encoding it, take bit 2 to bit 27.
8/20/2022 week04-3.ppt 12
How to Encode Branch Instructions
• To encode these branch instructions, we first
need to figure out the value for the
associated label
– This will be done by the assembler
– Note that the MIPS has the alignment
restriction, which means all the labels will be a
multiple of 4
– To increase the range, the address divided by 4 is
actually encoded
• In other words, the address is in terms of words (32
bits), rather than bytes
8/20/2022 week04-3.ppt 13
Encoding Conditional Branch Instructions
• It branches the number of the instructions
specified by the offset if register rs equals to
register rt
– In the stored-program concept, we implicitly need a
register to hold the address of the current instruction
being executed
• Which is called program counter (PC) (should be called
instruction address register)
– What is the value of PC after we finish executing the
current instruction?
8/20/2022 week04-3.ppt 14
Encoding Conditional Branch Instructions
• PC-relative addressing
– The offset of conditional branch instructions is
relative to PC + 4
– Since all MIPS instructions are 4 bytes long, the
offset refers to the number of words to the next
instruction instead of the number of bytes
8/20/2022 week04-3.ppt 15
Encoding bne
31
opcode rs rt Immediate Value
26 25 21 20 16 15 0
bne $19, $20, Else
Label/Offset
rt
rs
0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 0
Encoding = 0x16740002
0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 0
31
opcode rs rt
26 25 21 20 16 15 0
Immediate Value

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14941634.ppt

  • 2. 8/20/2022 CDA3100 2 Representing Instructions in Computers • Note that computers only have 0’s and 1’s • Before we can load MIPS instructions into memory, they need to be translated into machine instructions, which consist of only 0’s and 1’s – In other words, we need to encode or represent instructions – The symbolic representation of machine instructions is called assembly language – The binary representation of instructions is called machine language • A sequence of instructions in binary form is called machine code
  • 4. 8/20/2022 CDA3100 4 MIPS Instruction Encoding • Each MIPS instruction is exactly 32 bits – R-type (register type) – I-type (immediate type) – J-type (jump type) op rs rt rd shamt funct op rs rt 16 bit address or constant op 26 bit address
  • 5. 8/20/2022 CDA3100 5 R-Type Encoding 31 opcode rs rt rd 26 25 21 20 16 15 11 10 6 5 0 shamt funct 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 31 opcode rs rt rd 26 25 21 20 16 15 11 10 6 5 0 shamt funct add $4, $3, $2 rt rs rd 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Encoding = 0x00622020
  • 6. 8/20/2022 CDA3100 6 I-type Encoding 31 opcode rs rt Immediate Value 26 25 21 20 16 15 0 lw $5, 3000($2) Immediate rs rt 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 Encoding = 0x8C450BB8 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 31 opcode rs rt 26 25 21 20 16 15 0 Immediate Value
  • 7. 8/20/2022 CDA3100 7 I-type Encoding 31 opcode rs rt Immediate Value 26 25 21 20 16 15 0 sw $5, 3000($2) Immediate rs rt Encoding = 31 opcode rs rt 26 25 21 20 16 15 0 Immediate Value
  • 8. 8/20/2022 CDA3100 8 I-type Encoding 31 opcode rs rt Immediate Value 26 25 21 20 16 15 0 sw $5, 3000($2) Immediate rs rt 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 Encoding = 0xAC450BB8 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 0 31 opcode rs rt 26 25 21 20 16 15 0 Immediate Value
  • 9. 8/20/2022 CDA3100 9 I-type Encoding 31 opcode rs rt Immediate Value 26 25 21 20 16 15 0 addi $s0, $s0, 95 Immediate rs rt Encoding = 31 opcode rs rt 26 25 21 20 16 15 0 Immediate Value
  • 10. 8/20/2022 CDA3100 10 I-type Encoding 31 opcode rs rt Immediate Value 26 25 21 20 16 15 0 addi $s0, $s0, 95 Immediate rs rt 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 Encoding = 0x2210005F 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 31 opcode rs rt 26 25 21 20 16 15 0 Immediate Value
  • 11. J-type Encoding 31 opcode Jump Address 26 25 0 j 0x0040007c Jump Address 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 Encoding = 0x0810001F opcode j 0x0040007c 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 31 Jump Address 26 25 0 0x0040007c: the address of the instruction to jump to. When encoding it, take bit 2 to bit 27.
  • 12. 8/20/2022 week04-3.ppt 12 How to Encode Branch Instructions • To encode these branch instructions, we first need to figure out the value for the associated label – This will be done by the assembler – Note that the MIPS has the alignment restriction, which means all the labels will be a multiple of 4 – To increase the range, the address divided by 4 is actually encoded • In other words, the address is in terms of words (32 bits), rather than bytes
  • 13. 8/20/2022 week04-3.ppt 13 Encoding Conditional Branch Instructions • It branches the number of the instructions specified by the offset if register rs equals to register rt – In the stored-program concept, we implicitly need a register to hold the address of the current instruction being executed • Which is called program counter (PC) (should be called instruction address register) – What is the value of PC after we finish executing the current instruction?
  • 14. 8/20/2022 week04-3.ppt 14 Encoding Conditional Branch Instructions • PC-relative addressing – The offset of conditional branch instructions is relative to PC + 4 – Since all MIPS instructions are 4 bytes long, the offset refers to the number of words to the next instruction instead of the number of bytes
  • 15. 8/20/2022 week04-3.ppt 15 Encoding bne 31 opcode rs rt Immediate Value 26 25 21 20 16 15 0 bne $19, $20, Else Label/Offset rt rs 0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Encoding = 0x16740002 0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 31 opcode rs rt 26 25 21 20 16 15 0 Immediate Value